[PATCH 17/34] common/cnxk: add mbox define for inline profile support

[Nithin Dabilpuram <ndabilpuram@marvell.com>]

Add mbox support for global inline profile allocation.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h    | 45 ++++++++++++++++++++++++++
 drivers/common/cnxk/roc_nix_inl.c | 53 +++++++++++++++++++++++--------
 2 files changed, 85 insertions(+), 13 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index ab19387330..343ce81efc 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -336,6 +336,13 @@ struct mbox_msghdr {
 	  nix_mcast_grp_update_rsp)                                                                \
 	M(NIX_GET_LF_STATS,    0x802e, nix_get_lf_stats, nix_get_lf_stats_req, nix_lf_stats_rsp)   \
 	M(NIX_CN20K_AQ_ENQ, 0x802f, nix_cn20k_aq_enq, nix_cn20k_aq_enq_req, nix_cn20k_aq_enq_rsp)  \
+	M(NIX_LSO_ALT_FLAGS_CFG, 0x8030, nix_lso_alt_flags_cfg, nix_lso_alt_flags_cfg_req, \
+				nix_lso_alt_flags_cfg_rsp)			\
+	M(NIX_RX_INLINE_PROFILE_CFG, 0x8031, nix_rx_inl_profile_cfg,			\
+				nix_rx_inl_profile_cfg_req,			\
+				nix_rx_inl_profile_cfg_rsp)			\
+	M(NIX_RX_INLINE_LF_CFG, 0x8032, nix_rx_inl_lf_cfg, nix_rx_inl_lf_cfg_req,	\
+				msg_rsp)					\
 	/* MCS mbox IDs (range 0xa000 - 0xbFFF) */                                                 \
 	M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,                    \
 	  mcs_alloc_rsrc_rsp)                                                                      \
@@ -2008,6 +2015,32 @@ struct nix_inline_ipsec_cfg {
 	uint32_t __io credit_th;
 };
 
+#define NIX_RX_INL_PROFILE_PROTO_CNT 9
+struct nix_rx_inl_profile_cfg_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io def_cfg;
+	uint64_t __io extract_cfg;
+	uint64_t __io gen_cfg;
+	uint64_t __io prot_field_cfg[NIX_RX_INL_PROFILE_PROTO_CNT];
+	uint64_t __io rsvd[32];		/* reserved fields for future expansion */
+};
+
+struct nix_rx_inl_profile_cfg_rsp {
+	struct mbox_msghdr hdr;
+	uint8_t __io profile_id;
+	uint8_t __io rsvd[32];		/* reserved fields for future expansion */
+};
+
+struct nix_rx_inl_lf_cfg_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io rx_inline_cfg0;
+	uint64_t __io rx_inline_cfg1;
+	uint64_t __io rx_inline_sa_base;
+	uint8_t __io enable;
+	uint8_t __io profile_id;
+	uint8_t __io rsvd[32];		/* reserved fields for future expansion */
+};
+
 /* Per NIX LF inline IPSec configuration */
 struct nix_inline_ipsec_lf_cfg {
 	struct mbox_msghdr hdr;
@@ -2064,6 +2097,17 @@ struct nix_bandprof_get_hwinfo_rsp {
 	uint32_t __io policer_timeunit;
 };
 
+struct nix_lso_alt_flags_cfg_req {
+	struct mbox_msghdr hdr;
+	uint64_t __io cfg;
+	uint64_t __io cfg1;
+};
+
+struct nix_lso_alt_flags_cfg_rsp {
+	struct mbox_msghdr hdr;
+	uint8_t __io lso_alt_flags_idx;
+};
+
 /* SSO mailbox error codes
  * Range 501 - 600.
  */
@@ -3088,6 +3132,7 @@ struct nix_spi_to_sa_add_req {
 	uint32_t __io spi_index;
 	uint16_t __io match_id;
 	bool __io valid;
+	uint8_t __io inline_profile_id;
 };
 
 struct nix_spi_to_sa_add_rsp {
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 991a81b50d..37e1bfc0ed 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -395,7 +395,8 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 	uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
 	uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
-	struct roc_nix_ipsec_cfg cfg;
+	struct mbox *mbox = mbox_get((&nix->dev)->mbox);
+	struct nix_inline_ipsec_lf_cfg *lf_cfg;
 	uint64_t max_sa, i;
 	size_t inb_sa_sz;
 	void *sa;
@@ -419,8 +420,9 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 	nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
 				       ROC_NIX_INL_SA_BASE_ALIGN);
 	if (!nix->inb_sa_base) {
+		rc = -ENOMEM;
 		plt_err("Failed to allocate memory for Inbound SA");
-		return -ENOMEM;
+		goto exit;
 	}
 
 	if (!roc_model_is_cn9k()) {
@@ -433,23 +435,36 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 		}
 	}
 
-	memset(&cfg, 0, sizeof(cfg));
-	cfg.sa_size = inb_sa_sz;
-	cfg.iova = (uintptr_t)nix->inb_sa_base;
-	cfg.max_sa = max_sa;
-	cfg.tt = SSO_TT_ORDERED;
-
 	/* Setup device specific inb SA table */
-	rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
+	lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);
+	if (lf_cfg == NULL) {
+		rc = -ENOSPC;
+		plt_err("Failed to alloc nix inline ipsec lf cfg mbox msg");
+		goto free_mem;
+	}
+
+	lf_cfg->enable = 1;
+	lf_cfg->sa_base_addr = (uintptr_t)nix->inb_sa_base;
+	lf_cfg->ipsec_cfg1.sa_idx_w = plt_log2_u32(max_sa);
+	lf_cfg->ipsec_cfg0.lenm1_max = roc_nix_max_pkt_len(roc_nix) - 1;
+	lf_cfg->ipsec_cfg1.sa_idx_max = max_sa - 1;
+	lf_cfg->ipsec_cfg0.sa_pow2_size = plt_log2_u32(inb_sa_sz);
+	lf_cfg->ipsec_cfg0.tag_const = 0;
+	lf_cfg->ipsec_cfg0.tt = SSO_TT_ORDERED;
+
+	rc = mbox_process(mbox);
 	if (rc) {
 		plt_err("Failed to setup NIX Inbound SA conf, rc=%d", rc);
 		goto free_mem;
 	}
 
+	mbox_put(mbox);
 	return 0;
 free_mem:
 	plt_free(nix->inb_sa_base);
 	nix->inb_sa_base = NULL;
+exit:
+	mbox_put(mbox);
 	return rc;
 }
 
@@ -457,17 +472,29 @@ static int
 nix_inl_sa_tbl_release(struct roc_nix *roc_nix)
 {
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct mbox *mbox = mbox_get((&nix->dev)->mbox);
+	struct nix_inline_ipsec_lf_cfg *lf_cfg;
 	int rc;
 
-	rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, NULL, false);
+	lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);
+	if (lf_cfg == NULL) {
+		rc = -ENOSPC;
+		goto exit;
+	}
+
+	lf_cfg->enable = 0;
+
+	rc = mbox_process(mbox);
 	if (rc) {
-		plt_err("Failed to disable Inbound inline ipsec, rc=%d", rc);
-		return rc;
+		plt_err("Failed to cleanup NIX Inbound SA conf, rc=%d", rc);
+		goto exit;
 	}
 
 	plt_free(nix->inb_sa_base);
 	nix->inb_sa_base = NULL;
-	return 0;
+exit:
+	mbox_put(mbox);
+	return rc;
 }
 
 struct roc_cpt_lf *
-- 
2.34.1