[PATCH 00/46] Support AMD Solarflare X45xx adaptors

[PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Ivan Malov]

New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
supports multiple network engine types. This series provides support
only for the Medford2-alike, 'full-feature' (FF) network engine. This
shall not be confused with the concept of 'datapath FW variants': the
FF network engine supports both 'full-feature' and 'ultra-low-latency'
datapath FW variants, with corresponding Medford2-alike feature sets.

The first part of the series provides general support for the adaptors,
whilst the second one adds support for the new management controller
interface for configuration of network port features (netport MCDI).

For now, only support for physical functions (PFs) is concerned. There
is a small number of TODO and FIXME markings in the code. Those are
normal at this development stage and will be removed by future patches
when VF support has fleshed out.


Andy Moreton (3):
  common/sfc_efx/base: update X4 BAR layout and PCI IDs
  net/sfc: add Medford4 with only full feature datapath engine
  common/sfc_efx/base: add port mode for 8 port hardware

Denis Pryazhennikov (15):
  common/sfc_efx/base: add Medford4 PCI IDs to common code
  common/sfc_efx/base: add efsys option for Medford4
  common/sfc_efx/base: add Medford4 support to NIC module
  common/sfc_efx/base: add Medford4 support to EV module
  common/sfc_efx/base: add Medford4 support to FILTER module
  common/sfc_efx/base: add Medford4 support to INTR module
  common/sfc_efx/base: add Medford4 support to MAC module
  common/sfc_efx/base: add Medford4 support to PHY module
  common/sfc_efx/base: add Medford4 support to TUNNEL module
  common/sfc_efx/base: add Medford4 support to MCDI module
  common/sfc_efx/base: add Medford4 support to Rx module
  common/sfc_efx/base: add Medford4 support to Tx module
  drivers: enable support for AMD Solarflare X4 adapter family
  common/sfc_efx/base: add new X4 port mode
  common/sfc_efx/base: extend list of supported X4 port modes

Ivan Malov (28):
  common/sfc_efx/base: update MCDI headers
  common/sfc_efx/base: provide a stub for basic netport attach
  common/sfc_efx/base: provide defaults on netport attach path
  common/sfc_efx/base: obtain assigned netport handle from NIC
  common/sfc_efx/base: allow for const in MCDI struct accessor
  common/sfc_efx/base: get netport fixed capabilities on probe
  common/sfc_efx/base: decode netport link state on probe path
  common/sfc_efx/base: fill in loopback modes on netport probe
  common/sfc_efx/base: introduce Medford4 stub for PHY methods
  common/sfc_efx/base: refactor EF10 link mode decoding helper
  common/sfc_efx/base: provide PHY link get method on Medford4
  common/sfc_efx/base: implement PHY link control for Medford4
  common/sfc_efx/base: introduce Medford4 stub for MAC methods
  common/sfc_efx/base: add MAC reconfigure method for Medford4
  common/sfc_efx/base: fill in software LUT for MAC statistics
  common/sfc_efx/base: fill in MAC statistics mask on Medford4
  common/sfc_efx/base: support MAC statistics on Medford4 NICs
  common/sfc_efx/base: implement MAC PDU controls for Medford4
  common/sfc_efx/base: correct MAC PDU calculation on Medford4
  net/sfc: make use of generic EFX MAC PDU calculation helpers
  common/sfc_efx/base: ignore legacy link events on new boards
  common/sfc_efx/base: add link event processing on new boards
  net/sfc: query link status on link change events on new NICs
  common/sfc_efx/base: subscribe to netport link change events
  net/sfc: offer support for 200G link ability on new adaptors
  common/sfc_efx/base: support controls for netport lane count
  net/sfc: add support for control of physical port lane count
  doc: advertise support for AMD Solarflare X45xx adapters

 .mailmap                                      |    3 +-
 doc/guides/nics/sfc_efx.rst                   |    9 +-
 doc/guides/rel_notes/release_25_07.rst        |    4 +
 drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
 drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
 drivers/common/sfc_efx/base/ef10_nic.c        |   98 +-
 drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
 drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
 drivers/common/sfc_efx/base/efx.h             |   98 +-
 drivers/common/sfc_efx/base/efx_check.h       |   24 +-
 drivers/common/sfc_efx/base/efx_ev.c          |    6 +
 drivers/common/sfc_efx/base/efx_filter.c      |    6 +
 drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
 drivers/common/sfc_efx/base/efx_intr.c        |    6 +
 drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
 drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
 drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
 drivers/common/sfc_efx/base/efx_nic.c         |   60 +
 drivers/common/sfc_efx/base/efx_np.c          | 1625 +++++
 drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
 drivers/common/sfc_efx/base/efx_port.c        |    1 +
 drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
 drivers/common/sfc_efx/base/efx_rx.c          |    6 +
 drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
 drivers/common/sfc_efx/base/efx_tx.c          |   33 +
 drivers/common/sfc_efx/base/medford4_impl.h   |  110 +
 drivers/common/sfc_efx/base/medford4_mac.c    |  299 +
 drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
 drivers/common/sfc_efx/base/meson.build       |    3 +
 drivers/common/sfc_efx/efsys.h                |    2 +
 drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
 drivers/net/sfc/sfc.c                         |    5 +-
 drivers/net/sfc/sfc.h                         |    4 +
 drivers/net/sfc/sfc_dp_tx.h                   |    3 +
 drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
 drivers/net/sfc/sfc_ethdev.c                  |  186 +-
 drivers/net/sfc/sfc_ev.c                      |   51 +-
 drivers/net/sfc/sfc_port.c                    |   27 +-
 drivers/net/sfc/sfc_repr.c                    |    7 +-
 drivers/net/sfc/sfc_repr.h                    |    1 +
 drivers/net/sfc/sfc_tx.c                      |    2 +
 41 files changed, 9000 insertions(+), 125 deletions(-)
 create mode 100644 drivers/common/sfc_efx/base/efx_np.c
 create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
 create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
 create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c

-- 
2.39.5

[PATCH 01/46] common/sfc_efx/base: add Medford4 PCI IDs to common code

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Later patches will use this to implement support for Medford4.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 5773cb00b3..dabf2e0e0b 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -64,6 +64,7 @@ typedef enum efx_family_e {
 	EFX_FAMILY_MEDFORD,
 	EFX_FAMILY_MEDFORD2,
 	EFX_FAMILY_RIVERHEAD,
+	EFX_FAMILY_MEDFORD4,
 	EFX_FAMILY_NTYPES
 } efx_family_t;
 
@@ -172,6 +173,10 @@ efx_family_probe_bar(
 #define	EFX_PCI_DEVID_RIVERHEAD			0x0100
 #define	EFX_PCI_DEVID_RIVERHEAD_VF		0x1100
 
+#define	EFX_PCI_DEVID_MEDFORD4_PF_UNINIT	0x0C13
+#define	EFX_PCI_DEVID_MEDFORD4			0x0C03
+#define	EFX_PCI_DEVID_MEDFORD4_VF		0x1C03
+
 #define	EFX_MEM_BAR_SIENA			2
 
 #define	EFX_MEM_BAR_HUNTINGTON_PF		2
-- 
2.39.5

[PATCH 02/46] common/sfc_efx/base: add efsys option for Medford4

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Later patches will use this to implement support for Medford4.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_check.h | 24 ++++++++++++++----------
 drivers/common/sfc_efx/efsys.h          |  2 ++
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_check.h b/drivers/common/sfc_efx/base/efx_check.h
index 66b38eeae0..0b9f4fb516 100644
--- a/drivers/common/sfc_efx/base/efx_check.h
+++ b/drivers/common/sfc_efx/base/efx_check.h
@@ -32,7 +32,8 @@
 
 /* Check family options for EF10 architecture controllers. */
 #define	EFX_OPTS_EF10()	\
-	(EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
+	(EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
+	EFSYS_OPT_MEDFORD4)
 
 #ifdef EFSYS_OPT_FALCON
 # error "FALCON is obsolete and is not supported."
@@ -197,7 +198,7 @@
 
 #if EFSYS_OPT_IMAGE_LAYOUT
 /* Support signed image layout handling */
-# if !(EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
+# if !(EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
 #  error "IMAGE_LAYOUT requires MEDFORD or MEDFORD2"
 # endif
 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
@@ -338,8 +339,10 @@
 
 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
 /* Support adapters with missing static config (for factory use only) */
-# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
-#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2"
+# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
+	EFSYS_OPT_MEDFORD4)
+#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2 " \
+	"or MEDFORD4"
 # endif
 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
 
@@ -352,22 +355,23 @@
 
 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 /* Support equal stride super-buffer mode */
-# if !(EFSYS_OPT_MEDFORD2)
-#  error "ES_SUPER_BUFFER requires MEDFORD2"
+# if !(EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
+#  error "ES_SUPER_BUFFER requires MEDFORD2 or MEDFORD4"
 # endif
 #endif
 
 /* Support hardware assistance for tunnels */
 #if EFSYS_OPT_TUNNEL
-# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
-#  error "TUNNEL requires RIVERHEAD or MEDFORD or MEDFORD2"
+# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
+	EFSYS_OPT_MEDFORD4)
+#  error "TUNNEL requires RIVERHEAD or MEDFORD or MEDFORD2 or MEDFORD4"
 # endif
 #endif /* EFSYS_OPT_TUNNEL */
 
 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
 /* Advertise that the driver is firmware subvariant aware */
-# if !(EFSYS_OPT_MEDFORD2)
-#  error "FW_SUBVARIANT_AWARE requires MEDFORD2"
+# if !(EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
+#  error "FW_SUBVARIANT_AWARE requires MEDFORD2 or MEDFORD4"
 # endif
 #endif
 
diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h
index 41fa3da762..e63cbdbe8f 100644
--- a/drivers/common/sfc_efx/efsys.h
+++ b/drivers/common/sfc_efx/efsys.h
@@ -125,6 +125,8 @@ prefetch_read_once(const volatile void *addr)
 #define EFSYS_OPT_MEDFORD2 1
 /* Enable Riverhead support */
 #define EFSYS_OPT_RIVERHEAD 1
+/* Disable Medford4 support (not supported yet) */
+#define EFSYS_OPT_MEDFORD4 0
 
 #ifdef RTE_DEBUG_COMMON_SFC_EFX
 #define EFSYS_OPT_CHECK_REG 1
-- 
2.39.5

Re: [PATCH 02/46] common/sfc_efx/base: add efsys option for Medford4

[Andrew Rybchenko]

On 4/16/25 16:59, Ivan Malov wrote:
> From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
> 
> Later patches will use this to implement support for Medford4.
> 
> Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>
> ---
>   drivers/common/sfc_efx/base/efx_check.h | 24 ++++++++++++++----------
>   drivers/common/sfc_efx/efsys.h          |  2 ++
>   2 files changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/common/sfc_efx/base/efx_check.h b/drivers/common/sfc_efx/base/efx_check.h
> index 66b38eeae0..0b9f4fb516 100644
> --- a/drivers/common/sfc_efx/base/efx_check.h
> +++ b/drivers/common/sfc_efx/base/efx_check.h

[snip]

> @@ -197,7 +198,7 @@
>   
>   #if EFSYS_OPT_IMAGE_LAYOUT
>   /* Support signed image layout handling */
> -# if !(EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
> +# if !(EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
>   #  error "IMAGE_LAYOUT requires MEDFORD or MEDFORD2"

MEDRORD4 is lost here in error message

>   # endif
>   #endif /* EFSYS_OPT_IMAGE_LAYOUT */
> @@ -338,8 +339,10 @@
>   
>   #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
>   /* Support adapters with missing static config (for factory use only) */
> -# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
> -#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2"
> +# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
> +	EFSYS_OPT_MEDFORD4)
> +#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2 " \
> +	"or MEDFORD4"

Typically it is a bad idea to split error message since it complicates grep.
Please, double-check that base driver code style requires.
As far as I remember - no.

>   # endif
>   #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
>   

[snip]

Re: [PATCH 02/46] common/sfc_efx/base: add efsys option for Medford4

[Stephen Hemminger]

On Thu, 17 Apr 2025 10:08:20 +0300
Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru> wrote:

> >   #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
> >   /* Support adapters with missing static config (for factory use only) */
> > -# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
> > -#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2"
> > +# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
> > +	EFSYS_OPT_MEDFORD4)
> > +#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2 " \
> > +	"or MEDFORD4"  
> 
> Typically it is a bad idea to split error message since it complicates grep.
> Please, double-check that base driver code style requires.
> As far as I remember - no.

Would a static_assert() logic be less complex here?

Re: [PATCH 02/46] common/sfc_efx/base: add efsys option for Medford4

[Andrew Rybchenko]

On 4/17/25 18:07, Stephen Hemminger wrote:
> On Thu, 17 Apr 2025 10:08:20 +0300
> Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru> wrote:
> 
>>>    #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
>>>    /* Support adapters with missing static config (for factory use only) */
>>> -# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
>>> -#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2"
>>> +# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
>>> +	EFSYS_OPT_MEDFORD4)
>>> +#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2 " \
>>> +	"or MEDFORD4"
>>
>> Typically it is a bad idea to split error message since it complicates grep.
>> Please, double-check that base driver code style requires.
>> As far as I remember - no.
> 
> Would a static_assert() logic be less complex here?

It is a base driver with its own rules and the same code was used in
many places (platforms, drivers) before. I don't know what is today.
So, I guess static_assert() is not an option here.

[PATCH 03/46] common/sfc_efx/base: add Medford4 support to NIC module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Implement NIC family discovery and minimum probe support.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/ef10_nic.c | 33 ++++++++++++++++-
 drivers/common/sfc_efx/base/efx.h      |  1 +
 drivers/common/sfc_efx/base/efx_impl.h |  7 +++-
 drivers/common/sfc_efx/base/efx_nic.c  | 50 ++++++++++++++++++++++++++
 4 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 79d596b5ef..77c97217ee 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1422,7 +1422,7 @@ ef10_get_datapath_caps(
 
 	/*
 	 * Check if firmware reports the VI window mode.
-	 * Medford2 has a variable VI window size (8K, 16K or 64K).
+	 * Medford2 and Medford4 have a variable VI window size (8K, 16K or 64K).
 	 * Medford and Huntington have a fixed 8K VI window size.
 	 */
 	if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
@@ -1479,6 +1479,7 @@ ef10_get_datapath_caps(
 
 		switch (enp->en_family) {
 		case EFX_FAMILY_MEDFORD2:
+		case EFX_FAMILY_MEDFORD4:
 			encp->enc_rx_scale_hash_alg_mask =
 			    (1U << EFX_RX_HASHALG_TOEPLITZ);
 			break;
@@ -1922,6 +1923,36 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_1x1_1x1),			/* mode 2 */
 		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Medford4 allocate 2 adjacent port numbers to cage 1
+	 * and the rest to cage 2.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 1
+	 *	port 2 -> cage 2
+	 *	port 3 -> cage 2
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_2x1_2x1) |			/* mode 5 */
+		(1U << TLV_PORT_MODE_2x1_1x4) |			/* mode 7 */
+		(1U << TLV_PORT_MODE_2x2_NA) |			/* mode 13 */
+		(1U << TLV_PORT_MODE_2x1_1x2),			/* mode 18 */
+		{ 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
+	/*
+	 * Modes that on Medford4 allocate up to 4 adjacent port numbers
+	 * to cage 1.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 1
+	 *	port 2 -> cage 1
+	 *	port 3 -> cage 1
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_4x1_NA),			/* mode 4 */
+		{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
+	/* FIXME: review Medford4 port modes */
 };
 
 static	__checkReturn	efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index dabf2e0e0b..442dfa0830 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -190,6 +190,7 @@ efx_family_probe_bar(
 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
 #define	EFX_MEM_BAR_RIVERHEAD			2
 
+#define	EFX_MEM_BAR_MEDFORD4			0
 
 /* Error codes */
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 662a21e90c..9d1f361c5d 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -972,7 +972,8 @@ struct efx_nic_s {
 };
 
 #define	EFX_FAMILY_IS_EF10(_enp) \
-	((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
+	((_enp)->en_family == EFX_FAMILY_MEDFORD4 || \
+	 (_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 	 (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 	 (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 
@@ -1128,6 +1129,10 @@ struct efx_txq_s {
 			rev = 'G';					\
 			break;						\
 									\
+		case EFX_FAMILY_MEDFORD4:				\
+			rev = 'H';					\
+			break;						\
+									\
 		default:						\
 			rev = '?';					\
 			break;						\
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 172488e083..5bcc0a04ff 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -79,6 +79,19 @@ efx_family(
 			return (0);
 #endif /* EFSYS_OPT_MEDFORD2 */
 
+#if EFSYS_OPT_MEDFORD4
+		case EFX_PCI_DEVID_MEDFORD4_PF_UNINIT:
+			/*
+			 * Hardware default for PF0 of uninitialised Medford4.
+			 * manftest must be able to cope with this device id.
+			 */
+		case EFX_PCI_DEVID_MEDFORD4:
+		case EFX_PCI_DEVID_MEDFORD4_VF:
+			*efp = EFX_FAMILY_MEDFORD4;
+			*membarp = EFX_MEM_BAR_MEDFORD4;
+			return (0);
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 		case EFX_PCI_DEVID_FALCON:	/* Obsolete, not supported */
 		default:
 			break;
@@ -251,6 +264,27 @@ static const efx_nic_ops_t	__efx_nic_riverhead_ops = {
 
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+
+static const efx_nic_ops_t	__efx_nic_medford4_ops = {
+	ef10_nic_probe,			/* eno_probe */
+	medford2_board_cfg,		/* eno_board_cfg */
+	ef10_nic_set_drv_limits,	/* eno_set_drv_limits */
+	ef10_nic_reset,			/* eno_reset */
+	ef10_nic_init,			/* eno_init */
+	ef10_nic_get_vi_pool,		/* eno_get_vi_pool */
+	ef10_nic_get_bar_region,	/* eno_get_bar_region */
+	ef10_nic_hw_unavailable,	/* eno_hw_unavailable */
+	ef10_nic_set_hw_unavailable,	/* eno_set_hw_unavailable */
+#if EFSYS_OPT_DIAG
+	ef10_nic_register_test,		/* eno_register_test */
+#endif	/* EFSYS_OPT_DIAG */
+	ef10_nic_fini,			/* eno_fini */
+	ef10_nic_unprobe,		/* eno_unprobe */
+};
+
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 
 	__checkReturn	efx_rc_t
 efx_nic_create(
@@ -363,6 +397,22 @@ efx_nic_create(
 		break;
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		enp->en_enop = &__efx_nic_medford4_ops;
+		enp->en_features =
+		    EFX_FEATURE_IPV6 |
+		    EFX_FEATURE_LINK_EVENTS |
+		    EFX_FEATURE_PERIODIC_MAC_STATS |
+		    EFX_FEATURE_MCDI |
+		    EFX_FEATURE_MAC_HEADER_FILTERS |
+		    EFX_FEATURE_MCDI_DMA |
+		    EFX_FEATURE_FW_ASSISTED_TSO_V2 |
+		    EFX_FEATURE_PACKED_STREAM |
+		    EFX_FEATURE_TXQ_CKSUM_OP_DESC;
+		break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		rc = ENOTSUP;
 		goto fail2;
-- 
2.39.5

Re: [PATCH 03/46] common/sfc_efx/base: add Medford4 support to NIC module

[Andrew Rybchenko]

On 4/16/25 16:59, Ivan Malov wrote:
> From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
> 
> Implement NIC family discovery and minimum probe support.
> 
> Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>

[snip]

> @@ -1922,6 +1923,36 @@ static struct ef10_external_port_map_s {
>   		(1U << TLV_PORT_MODE_1x1_1x1),			/* mode 2 */
>   		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
>   	},
> +	/*
> +	 * Modes that on Medford4 allocate 2 adjacent port numbers to cage 1
> +	 * and the rest to cage 2.
> +	 *	port 0 -> cage 1
> +	 *	port 1 -> cage 1
> +	 *	port 2 -> cage 2
> +	 *	port 3 -> cage 2
> +	 */
> +	{
> +		EFX_FAMILY_MEDFORD4,
> +		(1U << TLV_PORT_MODE_2x1_2x1) |			/* mode 5 */
> +		(1U << TLV_PORT_MODE_2x1_1x4) |			/* mode 7 */
> +		(1U << TLV_PORT_MODE_2x2_NA) |			/* mode 13 */
> +		(1U << TLV_PORT_MODE_2x1_1x2),			/* mode 18 */
> +		{ 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
> +	},
> +	/*
> +	 * Modes that on Medford4 allocate up to 4 adjacent port numbers
> +	 * to cage 1.
> +	 *	port 0 -> cage 1
> +	 *	port 1 -> cage 1
> +	 *	port 2 -> cage 1
> +	 *	port 3 -> cage 1
> +	 */
> +	{
> +		EFX_FAMILY_MEDFORD4,
> +		(1U << TLV_PORT_MODE_4x1_NA),			/* mode 4 */
> +		{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
> +	},
> +	/* FIXME: review Medford4 port modes */

Is it still true at the moment of submission?

>   };
>   
>   static	__checkReturn	efx_rc_t
> diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
> index dabf2e0e0b..442dfa0830 100644
> --- a/drivers/common/sfc_efx/base/efx.h
> +++ b/drivers/common/sfc_efx/base/efx.h
> @@ -190,6 +190,7 @@ efx_family_probe_bar(
>   /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
>   #define	EFX_MEM_BAR_RIVERHEAD			2
>   
> +#define	EFX_MEM_BAR_MEDFORD4			0

IMHO it is wrong that you add it here and fix in later patches.
It just adds noise to mailing list and git blame.
IMHO fix should be squashed and correct BAR should be specified
from the very beginning.

>   
>   /* Error codes */
>   

[snip]

> diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
> index 172488e083..5bcc0a04ff 100644
> --- a/drivers/common/sfc_efx/base/efx_nic.c
> +++ b/drivers/common/sfc_efx/base/efx_nic.c
> @@ -79,6 +79,19 @@ efx_family(
>   			return (0);
>   #endif /* EFSYS_OPT_MEDFORD2 */
>   
> +#if EFSYS_OPT_MEDFORD4
> +		case EFX_PCI_DEVID_MEDFORD4_PF_UNINIT:
> +			/*
> +			 * Hardware default for PF0 of uninitialised Medford4.
> +			 * manftest must be able to cope with this device id.
> +			 */
> +		case EFX_PCI_DEVID_MEDFORD4:
> +		case EFX_PCI_DEVID_MEDFORD4_VF:
> +			*efp = EFX_FAMILY_MEDFORD4;
> +			*membarp = EFX_MEM_BAR_MEDFORD4;
> +			return (0);
> +#endif /* EFSYS_OPT_MEDFORD4 */
> +

It is a dead code from build point of view if I stop on the patch since
EFSYS_OPT_MEDFORD4 is 0. May be it is OK, but I'd like to ensure that
you have checked it if EFSYS_OPT_MEDFORD4==1 before the patch to avoid
build fixes noise later.

Same for all similar blocks below and subsequent patches.

>   		case EFX_PCI_DEVID_FALCON:	/* Obsolete, not supported */
>   		default:
>   			break;

[snip]

[PATCH 04/46] common/sfc_efx/base: add Medford4 support to EV module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_ev.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_ev.c b/drivers/common/sfc_efx/base/efx_ev.c
index 4808f8ddfc..13159a10f4 100644
--- a/drivers/common/sfc_efx/base/efx_ev.c
+++ b/drivers/common/sfc_efx/base/efx_ev.c
@@ -173,6 +173,12 @@ efx_ev_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		eevop = &__efx_ev_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH 05/46] common/sfc_efx/base: add Medford4 support to FILTER module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_filter.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_filter.c b/drivers/common/sfc_efx/base/efx_filter.c
index 2c8c7bdc33..551db58fdd 100644
--- a/drivers/common/sfc_efx/base/efx_filter.c
+++ b/drivers/common/sfc_efx/base/efx_filter.c
@@ -201,6 +201,12 @@ efx_filter_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		efop = &__efx_filter_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH 06/46] common/sfc_efx/base: add Medford4 support to INTR module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_intr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_intr.c b/drivers/common/sfc_efx/base/efx_intr.c
index 792302f540..8fdef839db 100644
--- a/drivers/common/sfc_efx/base/efx_intr.c
+++ b/drivers/common/sfc_efx/base/efx_intr.c
@@ -158,6 +158,12 @@ efx_intr_init(
 		break;
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		eiop = &__efx_intr_ef10_ops;
+		break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(B_FALSE);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH 07/46] common/sfc_efx/base: add Medford4 support to MAC module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h | 1 +
 drivers/common/sfc_efx/base/efx_mac.c  | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 9d1f361c5d..89b7e0292e 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -79,6 +79,7 @@ typedef enum efx_mac_type_e {
 	EFX_MAC_MEDFORD,
 	EFX_MAC_MEDFORD2,
 	EFX_MAC_RIVERHEAD,
+	EFX_MAC_MEDFORD4,
 	EFX_MAC_NTYPES
 } efx_mac_type_t;
 
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 13cac5a751..a2cbf02b46 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -953,6 +953,13 @@ efx_mac_select(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		emop = &__efx_mac_ef10_ops;
+		type = EFX_MAC_MEDFORD4;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		rc = EINVAL;
 		goto fail1;
-- 
2.39.5

[PATCH 08/46] common/sfc_efx/base: add Medford4 support to PHY module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_phy.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index d55becae18..3d792f20b8 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -114,6 +114,12 @@ efx_phy_probe(
 		break;
 #endif	/* EFSYS_OPT_MEDFORD2 */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		epop = &__efx_phy_ef10_ops;
+	break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		rc = ENOTSUP;
 		goto fail1;
-- 
2.39.5

[PATCH 09/46] common/sfc_efx/base: add Medford4 support to TUNNEL module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_tunnel.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_tunnel.c b/drivers/common/sfc_efx/base/efx_tunnel.c
index d63f9176e4..75968a0b4f 100644
--- a/drivers/common/sfc_efx/base/efx_tunnel.c
+++ b/drivers/common/sfc_efx/base/efx_tunnel.c
@@ -47,7 +47,7 @@
 
 #if EFSYS_OPT_TUNNEL
 
-#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4
 static	__checkReturn	boolean_t
 ef10_udp_encap_supported(
 	__in		efx_nic_t *enp);
@@ -59,7 +59,7 @@ ef10_tunnel_reconfigure(
 static			void
 ef10_tunnel_fini(
 	__in		efx_nic_t *enp);
-#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4 */
 
 #if EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON
 static const efx_tunnel_ops_t	__efx_tunnel_dummy_ops = {
@@ -68,12 +68,12 @@ static const efx_tunnel_ops_t	__efx_tunnel_dummy_ops = {
 };
 #endif /* EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON */
 
-#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4
 static const efx_tunnel_ops_t	__efx_tunnel_ef10_ops = {
 	ef10_tunnel_reconfigure,	/* eto_reconfigure */
 	ef10_tunnel_fini,		/* eto_fini */
 };
-#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4 */
 
 #if EFSYS_OPT_RIVERHEAD
 static const efx_tunnel_ops_t	__efx_tunnel_rhead_ops = {
@@ -254,6 +254,12 @@ efx_tunnel_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		etop = &__efx_tunnel_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
@@ -637,7 +643,7 @@ efx_tunnel_reconfigure(
 	return (rc);
 }
 
-#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4
 static	__checkReturn		boolean_t
 ef10_udp_encap_supported(
 	__in		efx_nic_t *enp)
@@ -724,6 +730,6 @@ ef10_tunnel_fini(
 		    &resetting);
 	}
 }
-#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4 */
 
 #endif /* EFSYS_OPT_TUNNEL */
-- 
2.39.5

[PATCH 10/46] common/sfc_efx/base: add Medford4 support to MCDI module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_mcdi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c
index acf7f02246..0bd56dd84d 100644
--- a/drivers/common/sfc_efx/base/efx_mcdi.c
+++ b/drivers/common/sfc_efx/base/efx_mcdi.c
@@ -119,6 +119,12 @@ efx_mcdi_init(
 		break;
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		emcop = &__efx_mcdi_ef10_ops;
+		break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH 11/46] common/sfc_efx/base: add Medford4 support to Rx module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_rx.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c
index dce9ada55d..86dfc89ba4 100644
--- a/drivers/common/sfc_efx/base/efx_rx.c
+++ b/drivers/common/sfc_efx/base/efx_rx.c
@@ -261,6 +261,12 @@ efx_rx_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		erxop = &__efx_rx_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH 12/46] common/sfc_efx/base: add Medford4 support to Tx module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Define and use Medford4 specific method table.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_tx.c | 33 ++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_tx.c b/drivers/common/sfc_efx/base/efx_tx.c
index 6f61f937a1..d1021dea82 100644
--- a/drivers/common/sfc_efx/base/efx_tx.c
+++ b/drivers/common/sfc_efx/base/efx_tx.c
@@ -233,6 +233,33 @@ static const efx_tx_ops_t	__efx_tx_rhead_ops = {
 #endif /* EFSYS_OPT_RIVERHEAD */
 
 
+#if EFSYS_OPT_MEDFORD4
+static const efx_tx_ops_t	__efx_tx_medford4_ops = {
+	ef10_tx_init,				/* etxo_init */
+	ef10_tx_fini,				/* etxo_fini */
+	ef10_tx_qcreate,			/* etxo_qcreate */
+	ef10_tx_qdestroy,			/* etxo_qdestroy */
+	ef10_tx_qpost,				/* etxo_qpost */
+	ef10_tx_qpush,				/* etxo_qpush */
+	ef10_tx_qpace,				/* etxo_qpace */
+	ef10_tx_qflush,				/* etxo_qflush */
+	ef10_tx_qenable,			/* etxo_qenable */
+	NULL,					/* etxo_qpio_enable */
+	NULL,					/* etxo_qpio_disable */
+	NULL,					/* etxo_qpio_write */
+	NULL,					/* etxo_qpio_post */
+	ef10_tx_qdesc_post,			/* etxo_qdesc_post */
+	ef10_tx_qdesc_dma_create,		/* etxo_qdesc_dma_create */
+	NULL,					/* etxo_qdesc_tso_create */
+	ef10_tx_qdesc_tso2_create,		/* etxo_qdesc_tso2_create */
+	ef10_tx_qdesc_vlantci_create,		/* etxo_qdesc_vlantci_create */
+	ef10_tx_qdesc_checksum_create,		/* etxo_qdesc_checksum_create */
+#if EFSYS_OPT_QSTATS
+	ef10_tx_qstats_update,			/* etxo_qstats_update */
+#endif
+};
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	__checkReturn	efx_rc_t
 efx_tx_init(
 	__in		efx_nic_t *enp)
@@ -284,6 +311,12 @@ efx_tx_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		etxop = &__efx_tx_medford4_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH 13/46] drivers: enable support for AMD Solarflare X4 adapter family

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Enable support for Medford4 (X4) adapters X4522 and X4542.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/efsys.h | 4 ++--
 drivers/net/sfc/sfc_ethdev.c   | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h
index e63cbdbe8f..ea68d3bd1a 100644
--- a/drivers/common/sfc_efx/efsys.h
+++ b/drivers/common/sfc_efx/efsys.h
@@ -125,8 +125,8 @@ prefetch_read_once(const volatile void *addr)
 #define EFSYS_OPT_MEDFORD2 1
 /* Enable Riverhead support */
 #define EFSYS_OPT_RIVERHEAD 1
-/* Disable Medford4 support (not supported yet) */
-#define EFSYS_OPT_MEDFORD4 0
+/* Enable Medford4 support */
+#define EFSYS_OPT_MEDFORD4 1
 
 #ifdef RTE_DEBUG_COMMON_SFC_EFX
 #define EFSYS_OPT_CHECK_REG 1
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 82fbdbae9c..3e57c902df 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -2829,6 +2829,7 @@ sfc_eth_dev_set_ops(struct rte_eth_dev *dev)
 	case EFX_FAMILY_HUNTINGTON:
 	case EFX_FAMILY_MEDFORD:
 	case EFX_FAMILY_MEDFORD2:
+	case EFX_FAMILY_MEDFORD4:
 		avail_caps |= SFC_DP_HW_FW_CAP_EF10;
 		avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX;
 		avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX;
@@ -3301,6 +3302,8 @@ static const struct rte_pci_id pci_id_sfc_efx_map[] = {
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) },
 	{ .vendor_id = 0 /* sentinel */ }
-- 
2.39.5

[PATCH 14/46] common/sfc_efx/base: update X4 BAR layout and PCI IDs

[Ivan Malov]

From: Andy Moreton <andy.moreton@amd.com>

The BAR layout on X4 has changed to put MSI-X (and CXL) in BAR0/1,
and moved the main memory BAR to be BAR2/3. Update definitions to
match the updated hardware and cmodel.

Also add PCI IDs used for functions which only have the full feature
(X2 style) datapath engines, and do not support the low latency
datapath engine.

Signed-off-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/common/sfc_efx/base/efx.h     | 12 +++++++++---
 drivers/common/sfc_efx/base/efx_nic.c |  2 ++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 442dfa0830..a9ed3f423f 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -173,9 +173,15 @@ efx_family_probe_bar(
 #define	EFX_PCI_DEVID_RIVERHEAD			0x0100
 #define	EFX_PCI_DEVID_RIVERHEAD_VF		0x1100
 
+/*
+ * Medford4 has low latency (LL) and full feature (FF) datapath engines.
+ * Some Medford4 functions have FF and LL datapath, others only have FF.
+ */
 #define	EFX_PCI_DEVID_MEDFORD4_PF_UNINIT	0x0C13
-#define	EFX_PCI_DEVID_MEDFORD4			0x0C03
-#define	EFX_PCI_DEVID_MEDFORD4_VF		0x1C03
+#define	EFX_PCI_DEVID_MEDFORD4			0x0C03	/* X4 PF, FF+LL */
+#define	EFX_PCI_DEVID_MEDFORD4_VF		0x1C03	/* X4 VF, FF+LL */
+#define	EFX_PCI_DEVID_MEDFORD4_NO_LL		0x2C03	/* X4 PF, FF only */
+#define	EFX_PCI_DEVID_MEDFORD4_NO_LL_VF		0x3C03	/* X4 VF, FF only */
 
 #define	EFX_MEM_BAR_SIENA			2
 
@@ -190,7 +196,7 @@ efx_family_probe_bar(
 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
 #define	EFX_MEM_BAR_RIVERHEAD			2
 
-#define	EFX_MEM_BAR_MEDFORD4			0
+#define	EFX_MEM_BAR_MEDFORD4			2
 
 /* Error codes */
 
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 5bcc0a04ff..1ec684da40 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -87,6 +87,8 @@ efx_family(
 			 */
 		case EFX_PCI_DEVID_MEDFORD4:
 		case EFX_PCI_DEVID_MEDFORD4_VF:
+		case EFX_PCI_DEVID_MEDFORD4_NO_LL:
+		case EFX_PCI_DEVID_MEDFORD4_NO_LL_VF:
 			*efp = EFX_FAMILY_MEDFORD4;
 			*membarp = EFX_MEM_BAR_MEDFORD4;
 			return (0);
-- 
2.39.5

[PATCH 15/46] net/sfc: add Medford4 with only full feature datapath engine

[Ivan Malov]

From: Andy Moreton <andy.moreton@amd.com>

Add PCI IDs for Medford4 functions that only have the full feature
datapath engine (no support for low latency datapath engine).

Signed-off-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/net/sfc/sfc_ethdev.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 3e57c902df..05194918f9 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -3304,6 +3304,8 @@ static const struct rte_pci_id pci_id_sfc_efx_map[] = {
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_VF) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_NO_LL) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_NO_LL_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) },
 	{ .vendor_id = 0 /* sentinel */ }
-- 
2.39.5

[PATCH 16/46] common/sfc_efx/base: add port mode for 8 port hardware

[Ivan Malov]

From: Andy Moreton <andy.moreton@amd.com>

Add support for 8 port mode and adjust the bus bandwidth
computation and external port mapping table.

Signed-off-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/common/sfc_efx/base/ef10_nic.c        | 20 +++++++++++++++++++
 drivers/common/sfc_efx/base/ef10_tlv_layout.h |  9 ++++++---
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 77c97217ee..0e00ff64d4 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -176,6 +176,9 @@ ef10_nic_get_port_mode_bandwidth(
 	case TLV_PORT_MODE_2x1_2x1:			/* mode 5 */
 		bandwidth = (2 * single_lane) + (2 * single_lane);
 		break;
+	case TLV_PORT_MODE_4x1_4x1:			/* mode 26 */
+		bandwidth = (4 * single_lane) + (4 * single_lane);
+		break;
 	case TLV_PORT_MODE_1x2_1x2:			/* mode 12 */
 		bandwidth = dual_lane + dual_lane;
 		break;
@@ -1952,6 +1955,23 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_4x1_NA),			/* mode 4 */
 		{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Medford4 allocate up to 4 adjacent port numbers
+	 * to cage 1 and 4 port numbers to cage 2.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 1
+	 *	port 2 -> cage 1
+	 *	port 3 -> cage 1
+	 *	port 4 -> cage 2
+	 *	port 5 -> cage 2
+	 *	port 6 -> cage 2
+	 *	port 7 -> cage 2
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_4x1_4x1),			/* mode 26 */
+		{ 0, 4, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
 	/* FIXME: review Medford4 port modes */
 };
 
diff --git a/drivers/common/sfc_efx/base/ef10_tlv_layout.h b/drivers/common/sfc_efx/base/ef10_tlv_layout.h
index 9ac50f1df6..712a1c7d26 100644
--- a/drivers/common/sfc_efx/base/ef10_tlv_layout.h
+++ b/drivers/common/sfc_efx/base/ef10_tlv_layout.h
@@ -7,7 +7,7 @@
 /*
  * This is NOT the original source file. Do NOT edit it.
  * To update the tlv layout, please edit the copy in
- * the sfregistry repo and then, in that repo,
+ * the smartnic_registry repo and then, in that repo,
  * "make tlv_headers" or "make export" to
  * regenerate and export all types of headers.
  */
@@ -635,7 +635,10 @@ struct tlv_global_port_mode {
 #define TLV_PORT_MODE_1x1_NA_LL                  (23) /* Single 10G/25G on mdi0, low-latency PCS */
 #define TLV_PORT_MODE_1x1_1x1_LL                 (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE        (9) /* bug63720: Do not use */
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
+
+/* X4 */
+
+#define TLV_PORT_MODE_4x1_4x1                    (25) /* Quad 10G/25G on mdi0, quad 10G/25G on mdi1 */
 
 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
 #define TLV_PORT_MODE_10G_10G_10G_10G_Q          (5)
@@ -643,7 +646,7 @@ struct tlv_global_port_mode {
 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2         (8)
 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2      (9)
 
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_4x1_4x1
 };
 
 /* Type of the v-switch created implicitly by the firmware */
-- 
2.39.5

[PATCH 17/46] common/sfc_efx/base: add new X4 port mode

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Add handling for the port mode in the Medford4 driver logic,
enabling support for two single network ports.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Richard Houldsworth <richard.houldsworth@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 .mailmap                               |  2 +-
 drivers/common/sfc_efx/base/ef10_nic.c | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index afebbb32e6..1fbad1e1ae 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1295,7 +1295,7 @@ Ricardo Salveti <ricardo.salveti@linaro.org>
 Richael Zhuang <richael.zhuang@arm.com>
 Richard Donkin <richard.donkin@corigine.com>
 Richard Eklycke <richard.eklycke@ericsson.com>
-Richard Houldsworth <rhouldsw@xilinx.com> <rhouldsworth@solarflare.com>
+Richard Houldsworth <richard.houldsworth@amd.com> <rhouldsw@xilinx.com> <rhouldsworth@solarflare.com>
 Richard Walsh <richard.walsh@intel.com>
 Rich Lane <rich.lane@bigswitch.com>
 Ricky Li <ricky.li@intel.com>
diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 0e00ff64d4..e28978e4cc 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1972,6 +1972,16 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_4x1_4x1),			/* mode 26 */
 		{ 0, 4, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Medford4 allocate each port number to a separate cage.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 2
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_1x4_1x4),			/* mode 3 */
+		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
 	/* FIXME: review Medford4 port modes */
 };
 
-- 
2.39.5

[PATCH 18/46] common/sfc_efx/base: extend list of supported X4 port modes

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Add X4 port mode that allocates two 10G/25G/50G ports
to separate cages.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Richard Houldsworth <richard.houldsworth@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/common/sfc_efx/base/ef10_nic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index e28978e4cc..e1e8de5396 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1979,6 +1979,7 @@ static struct ef10_external_port_map_s {
 	 */
 	{
 		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_1x1_1x1) |			/* mode 2 */
 		(1U << TLV_PORT_MODE_1x4_1x4),			/* mode 3 */
 		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
-- 
2.39.5

[PATCH 19/46] common/sfc_efx/base: update MCDI headers

[Ivan Malov]

Pick up new X4 network port MCDI defines.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 .mailmap                                    |    1 +
 drivers/common/sfc_efx/base/efx_regs_mcdi.h | 5868 ++++++++++++++++++-
 2 files changed, 5816 insertions(+), 53 deletions(-)

diff --git a/.mailmap b/.mailmap
index 1fbad1e1ae..f46390b2d0 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1208,6 +1208,7 @@ Phil Yang <phil.yang@arm.com>
 Philip Prindeville <philipp@redfish-solutions.com>
 Pier Damouny <pdamouny@nvidia.com>
 Pierre Pfister <ppfister@cisco.com>
+Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
 Piotr Azarewicz <piotr.azarewicz@intel.com> <piotrx.t.azarewicz@intel.com>
 Piotr Bartosiewicz <piotr.bartosiewicz@atendesoftware.pl>
 Piotr Bronowski <piotrx.bronowski@intel.com>
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
index 41751344b4..a981d0be5e 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
@@ -408,6 +408,12 @@
  */
 #define	MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
 
+/* PORT_DIRECTION enum: Traffic direction for the port configuration APIs. */
+/* enum: Receive */
+#define	PORT_DIRECTION_RX 0x0
+/* enum: Transmit */
+#define	PORT_DIRECTION_TX 0x1
+
 /* MC_CMD_RESOURCE_SPECIFIER enum */
 /* enum: Any */
 #define	MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
@@ -445,6 +451,14 @@
  * an on-NIC ARM module is expected to be connected.
  */
 #define	PCIE_INTERFACE_NIC_EMBEDDED 0x1
+/* enum: The PCIe logical interface 0. It is an alias for HOST_PRIMARY. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_0 0x0
+/* enum: The PCIe logical interface 1. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_1 0x2
+/* enum: The PCIe logical interface 2. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_2 0x3
+/* enum: The PCIe logical interface 3. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_3 0x4
 /* enum: For MCDI commands issued over a PCIe interface, this value is
  * translated into the interface over which the command was issued. Not
  * meaningful for other MCDI transports.
@@ -682,6 +696,53 @@
  */
 #define	MAE_COUNTER_ID_NULL 0xffffffff
 
+/* PR_METADATA_ITEM_CATEGORY enum: Meta-data item category */
+/* enum: A XCLBIN meta-data section */
+#define	PR_METADATA_ITEM_CATEGORY_SECTION 0x0
+/* enum: The active XCLBIN's UUID (axlf_header::uuid) */
+#define	PR_METADATA_ITEM_CATEGORY_UUID 0x1
+/* enum: The active XCLBIN's timestamp (axlf_header::m_timeStamp) */
+#define	PR_METADATA_ITEM_CATEGORY_TIMESTAMP 0x2
+/* enum: The active XCLBIN's signature (the last axlf::m_signature_length bytes
+ * of the XCLBIN data)
+ */
+#define	PR_METADATA_ITEM_CATEGORY_SIGNATURE 0x3
+
+/* PR_METADATA_ITEM_SUBCATEGORY enum: Meta-data item sub-category. For the
+ * SECTION category the subcategory matches AXLF section type identifiers (enum
+ * axlf_section_kind) and each subcategory contains an array of items as the
+ * AXLF container format supports multiple sections of the same type. Other
+ * categories (UUID, TIMESTAMP and SIGNATURE) do not currently use
+ * subcategories and must be 0 (NONE).
+ */
+#define	PR_METADATA_ITEM_SUBCATEGORY_NONE 0x0 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BITSTREAM 0x0 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_CLEARING_BITSTREAM 0x1 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_EMBEDDED_METADATA 0x2 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_FIRMWARE 0x3 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DEBUG_DATA 0x4 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_SCHED_FIRMWARE 0x5 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_MEM_TOPOLOGY 0x6 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_CONNECTIVITY 0x7 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_IP_LAYOUT 0x8 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DEBUG_IP_LAYOUT 0x9 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DESIGN_CHECK_POINT 0xa /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_CLOCK_FREQ_TOPOLOGY 0xb /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_MCS 0xc /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BMC 0xd /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BUILD_METADATA 0xe /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_KEYVALUE_METADATA 0xf /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_USER_METADATA 0x10 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DNA_CERTIFICATE 0x11 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_PDI 0x12 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BITSTREAM_PARTIAL_PDI 0x13 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_PARTITION_METADATA 0x14 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_EMULATION_DATA 0x15 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_SYSTEM_METADATA 0x16 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_SOFT_KERNEL 0x17 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_ASK_FLASH 0x18 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_AIE_METADATA 0x19 /* enum */
+
 /* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
  * structured with bits [31:24] reserved (0), [23:16] indicating which major
  * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
@@ -1241,10 +1302,7 @@
 #define	TABLE_FIELD_ID_CRC_REFOUT 0x3f4
 /* enum: If set, invert every bit of the output value. */
 #define	TABLE_FIELD_ID_CRC_INVOUT 0x3f5
-/* enum: The CRC polynomial to use for checksumming, in normal form. See
- * https://en.wikipedia.org/wiki/Cyclic_redundancy_check#Specification for a
- * description of normal form.
- */
+/* enum: The CRC polynomial to use for checksumming, in normal form. */
 #define	TABLE_FIELD_ID_CRC_POLY 0x3f6
 /* enum: Operation for the checksum engine to perform - see DPU_CSUM_OP enum.
  */
@@ -1335,6 +1393,24 @@
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
+#define	MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_LBN 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_WIDTH 24
+#define	MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_LBN 24
+#define	MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_WIDTH 7
+#define	MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_LBN 31
+#define	MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_WIDTH 1
+#define	MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_LBN 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_WIDTH 24
+#define	MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_LBN 24
+#define	MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_WIDTH 7
+#define	MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_LBN 31
+#define	MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_WIDTH 1
 #define	MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
 #define	MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
 #define	MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
@@ -1709,6 +1785,25 @@
  * VI ID.
  */
 #define	MCDI_EVENT_CODE_DESC_PROXY_FUNC_QUEUE_START 0x28
+/* enum: Notification of a change in link state and/or link speed of a network
+ * port link. This event applies to a network port identified by a handle,
+ * PORT_HANDLE, which is discovered by the driver using the MC_CMD_ENUM_PORTS
+ * command.
+ */
+#define	MCDI_EVENT_CODE_PORT_LINKCHANGE 0x29
+/* enum: Notification of a change in the state of an MDI (external connector)
+ * of a network port. This typically corresponds to module plug/unplug for
+ * modular interfaces (e.g., SFP/QSFP and similar) or cable connect/disconnect.
+ * This event applies to a network port identified by a handle, PORT_HANDLE,
+ * which is discovered by the driver using the MC_CMD_ENUM_PORTS command.
+ */
+#define	MCDI_EVENT_CODE_PORT_MODULECHANGE 0x2a
+/* enum: Notification that the port enumeration journal has changed since it
+ * was last read and updates can be read using the MC_CMD_ENUM_PORTS command.
+ * The firmware may moderate the events so that an event is not sent for every
+ * change to the journal.
+ */
+#define	MCDI_EVENT_CODE_ENUM_PORTS_CHANGE 0x2b
 /* enum: Artificial event generated by host and posted via MC for test
  * purposes.
  */
@@ -1721,6 +1816,14 @@
 #define	MCDI_EVENT_LINKCHANGE_DATA_LEN 4
 #define	MCDI_EVENT_LINKCHANGE_DATA_LBN 0
 #define	MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_LEN 4
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_LBN 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_WIDTH 32
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_LEN 4
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_LBN 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_WIDTH 32
 #define	MCDI_EVENT_SENSOREVT_DATA_OFST 0
 #define	MCDI_EVENT_SENSOREVT_DATA_LEN 4
 #define	MCDI_EVENT_SENSOREVT_DATA_LBN 0
@@ -3302,8 +3405,11 @@
  * subscribers.
  */
 #define	MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
-/* enum: Above this for future use. */
-#define	MC_CMD_PTP_OP_MAX 0x1c
+/* enum: X4 and later adapters should use this instead of
+ * PTP_OP_TIME_EVENT_SUBSCRIBE. Subscribe to receive periodic time events
+ * indicating the current NIC time
+ */
+#define	MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE_V2 0x1c
 
 /* MC_CMD_PTP_IN_ENABLE msgrequest */
 #define	MC_CMD_PTP_IN_ENABLE_LEN 16
@@ -3744,6 +3850,22 @@
 #define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
 #define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
 
+/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2 msgrequest */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_LEN 16
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_CMD_LEN 4 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
+/* Event queue ID */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_OFST 8
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_LEN 4
+/* Space for flags. */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_OFST 12
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_LEN 4
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_OFST 12
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_LBN 31
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_WIDTH 1
+
 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
 #define	MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
@@ -6262,13 +6384,837 @@
 #define	FEC_TYPE_TYPE_LEN 4
 /* enum: No FEC */
 #define	MC_CMD_FEC_NONE 0x0
-/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
+/* enum: IEEE 802.3, Clause 74 BASE-R FEC (a.k.a Firecode) */
 #define	MC_CMD_FEC_BASER 0x1
-/* enum: Clause 91/Clause 108 Reed-Solomon FEC */
+/* enum: IEEE 802.3, Clause 91/Clause 108 Reed-Solomon FEC */
 #define	MC_CMD_FEC_RS 0x2
+/* enum: IEEE 802.3, Clause 161, interleaved RS-FEC sublayer for 100GBASE-R
+ * PHYs
+ */
+#define	MC_CMD_FEC_IEEE_RS_INT 0x3
+/* enum: Ethernet Consortium, Low Latency RS-FEC. RS(272, 258). Replaces FEC
+ * specified in Clause 119 for 100/200G PHY. Replaces FEC specified in Clause
+ * 134 for 50G PHY.
+ */
+#define	MC_CMD_FEC_ETCS_RS_LL 0x4
+/* enum: FEC mode selected automatically */
+#define	MC_CMD_FEC_AUTO 0x5
 #define	FEC_TYPE_TYPE_LBN 0
 #define	FEC_TYPE_TYPE_WIDTH 32
 
+/* MC_CMD_ETH_TECH structuredef: Ethernet technology as defined by IEEE802.3,
+ * Ethernet Technology Consortium, proprietary technologies. The driver must
+ * not use technologies labelled NONE and AUTO.
+ */
+#define	MC_CMD_ETH_TECH_LEN 16
+/* The enums in this field can be used either as bitwise indices into a tech
+ * mask (e.g. see MC_CMD_ETH_AN_FIELDS/TECH_MASK for example) or as regular
+ * enums (e.g. see MC_CMD_LINK_CTRL_IN/ADVERTISED_TECH_ABILITIES_MASK). This
+ * structure must be updated to add new technologies when projects that need
+ * them arise. An incomplete list of possible expansion in the future include:
+ * 100GBASE_KP4, 800GBASE_CR8, 800GBASE_KR8, 800GBASE_DR8, 800GBASE_SR8
+ * 800GBASE_VR8
+ */
+#define	MC_CMD_ETH_TECH_TECH_OFST 0
+#define	MC_CMD_ETH_TECH_TECH_LEN 16
+/* enum: 1000BASE-KX - 1000BASE-X PCS/PMA over an electrical backplane PMD. See
+ * IEEE 802.3 Clause 70
+ */
+#define	MC_CMD_ETH_TECH_1000BASEKX 0x0
+/* enum: 10GBASE-R - PCS/PMA over an electrical backplane PMD. Refer to IEEE
+ * 802.3 Clause 72
+ */
+#define	MC_CMD_ETH_TECH_10GBASE_KR 0x1
+/* enum: 40GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 84.
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_KR4 0x2
+/* enum: 40GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
+ * IEEE 802.3 Clause 85
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_CR4 0x3
+/* enum: 40GBASE-R PCS/PMA over 4 lane multimode fiber PMD as specified in
+ * Clause 86
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_SR4 0x4
+/* enum: 40GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD with long
+ * reach. See IEEE 802.3 Clause 87
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_LR4 0x5
+/* enum: 25GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
+ * 802.3 Clause 110
+ */
+#define	MC_CMD_ETH_TECH_25GBASE_CR 0x6
+/* enum: 25GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 111
+ */
+#define	MC_CMD_ETH_TECH_25GBASE_KR 0x7
+/* enum: 25GBASE-R PCS/PMA over multimode fiber PMD. Refer to IEEE 802.3 Clause
+ * 112
+ */
+#define	MC_CMD_ETH_TECH_25GBASE_SR 0x8
+/* enum: An Ethernet Physical layer operating at 50 Gb/s on twin-axial copper
+ * cable. Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_CR2 0x9
+/* enum: An Ethernet Physical layer operating at 50 Gb/s on copper backplane.
+ * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_KR2 0xa
+/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 93
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_KR4 0xb
+/* enum: 100GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
+ * Clause 95
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_SR4 0xc
+/* enum: 100GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
+ * IEEE 802.3 Clause 92
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR4 0xd
+/* enum: 100GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD, with
+ * long/extended reach,. See IEEE 802.3 Clause 88
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_LR4_ER4 0xe
+/* enum: An Ethernet Physical layer operating at 50 Gb/s on short reach fiber.
+ * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_SR2 0xf
+/* enum: 1000BASEX PCS/PMA. See IEEE 802.3 Clause 36 over undefined PMD, duplex
+ * mode unknown
+ */
+#define	MC_CMD_ETH_TECH_1000BASEX 0x10
+/* enum: Non-standardised. 10G direct attach */
+#define	MC_CMD_ETH_TECH_10GBASE_CR 0x11
+/* enum: 10GBASE-SR fiber over 850nm optics. See IEEE 802.3 Clause 52 */
+#define	MC_CMD_ETH_TECH_10GBASE_SR 0x12
+/* enum: 10GBASE-LR fiber over 1310nm optics. See IEEE 802.3 Clause 52 */
+#define	MC_CMD_ETH_TECH_10GBASE_LR 0x13
+/* enum: 10GBASE-LRM fiber over 1310 nm optics. See IEEE 802.3 Clause 68 */
+#define	MC_CMD_ETH_TECH_10GBASE_LRM 0x14
+/* enum: 10GBASE-ER fiber over 1550nm optics. See IEEE 802.3 Clause 52 */
+#define	MC_CMD_ETH_TECH_10GBASE_ER 0x15
+/* enum: 50GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 137
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_KR 0x16
+/* enum: 50GBASE-SR PCS/PMA over multimode fiber PMD as specified in Clause 138
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_SR 0x17
+/* enum: 50GBASE-CR PCS/PMA over shielded copper balanced cable PMD. See IEEE
+ * 802.3 Clause 136
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_CR 0x18
+/* enum: 50GBASE-R PCS/PMA over single mode fiber PMD as specified in Clause
+ * 139.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_LR_ER_FR 0x19
+/* enum: 100 Gb/s PHY using 100GBASE-R encoding over single-mode fiber with
+ * reach up to at least 500 m (see IEEE 802.3 Clause 140)
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_DR 0x1a
+/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 137
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_KR2 0x1b
+/* enum: 100GBASE-R PCS/PMA over 2 lane multimode fiber PMD. See IEEE 802.3
+ * Clause 138
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_SR2 0x1c
+/* enum: 100GBASE-R PCS/PMA over 2 lane shielded copper balanced cable PMD. See
+ * IEEE 802.3 Clause 136
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR2 0x1d
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2 0x1e
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_100GBASE_DR2 0x1f
+/* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 137
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_KR4 0x20
+/* enum: 200GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
+ * Clause 138
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_SR4 0x21
+/* enum: 200GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD as specified
+ * in Clause 122
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4 0x22
+/* enum: 200GBASE-R PCS/PMA over 4-lane single-mode fiber PMD. See IEEE 802.3
+ * Clause 121
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_DR4 0x23
+/* enum: 200GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD as
+ * specified in Clause 136
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_CR4 0x24
+/* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-KR8 PMD uses
+ * 802.3 Clause 137, but the number PMD lanes is 8.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_KR8 0x25
+/* enum: 400GBASE-R PCS/PMA over 8-lane multimode fiber PMD. See IEEE 802.3
+ * Clause 138
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_SR8 0x26
+/* enum: 400GBASE-R PCS/PMA over 8 WDM lane single-mode fiber PMD. See IEEE
+ * 802.3 Clause 122
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_LR8_ER8_FR8 0x27
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_400GBASE_DR8 0x28
+/* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-CR8 PMD uses
+ * IEEE 802.3 Clause 136, but the number PMD lanes is 8.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_CR8 0x29
+/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3ck
+ * Clause 163.
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_KR 0x2a
+/* enum: IEEE 802.3ck. 100G PHY with PMD as specified in Clause 167 over short
+ * reach fiber
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_SR 0x2b
+/* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
+ * 140
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_LR_ER_FR 0x2c
+/* enum: 100GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
+ * 802.3 in Clause 162 IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR 0x2d
+/* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
+ * 140
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_DR 0x2e
+/* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD as specified in
+ * Clause 163 IEEE 802.3ck
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_KR2 0x2f
+/* enum: 200G PHY with PMD as specified in Clause 167 over short reach fiber
+ * IEEE 802.3ck
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_SR2 0x30
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2 0x31
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_200GBASE_DR2 0x32
+/* enum: 200GBASE-R PCS/PMA over 2 lane shielded balanced copper cable PMD as
+ * specified in Clause 162 IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_CR2 0x33
+/* enum: 400GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 163 IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_KR4 0x34
+/* enum: 400G PHY with PMD over short reach fiber. See Clause 167 of IEEE
+ * 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_SR4 0x35
+/* enum: 400GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD. See IEEE
+ * 802.3 Clause 151
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_LR4_ER4_FR4 0x36
+/* enum: 400GBASE-R PCS/PMA over 4-lane single-mode fiber PMD as specified in
+ * Clause 124
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_DR4 0x37
+/* enum: 400GBASE-R PCS/PMA over 4 lane shielded balanced copper cable PMD as
+ * specified in Clause 162 of IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_CR4 0x38
+/* enum: Automatic tech mode. The driver must not use this. */
+#define	MC_CMD_ETH_TECH_AUTO 0x39
+/* enum: See IEEE 802.3cc-2017 Clause 114 */
+#define	MC_CMD_ETH_TECH_25GBASE_LR_ER 0x3a
+/* enum: Up to 7 m over twinaxial copper cable assembly (10 lanes, 10 Gbit/s
+ * each) See IEEE 802.3ba-2010 Clause 85
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR10 0x3b
+/* enum: Invalid tech mode. The driver must not use this. */
+#define	MC_CMD_ETH_TECH_NONE 0x7f
+#define	MC_CMD_ETH_TECH_TECH_LBN 0
+#define	MC_CMD_ETH_TECH_TECH_WIDTH 128
+
+/* MC_CMD_LINK_STATUS_FLAGS structuredef */
+#define	MC_CMD_LINK_STATUS_FLAGS_LEN 8
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: bitshift */
+/* enum: Whether we have overall link up */
+#define	MC_CMD_LINK_STATUS_FLAGS_LINK_UP 0x0
+/* enum: If set, the PHY has no external RX link synchronisation */
+#define	MC_CMD_LINK_STATUS_FLAGS_NO_PHY_LINK 0x1
+/* enum: If set, PMD/MDI is not connected (e.g. cable disconnected, module cage
+ * empty)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_MDI_DISCONNECTED 0x2
+/* enum: Set on error while decoding module data (e.g. module EEPROM does not
+ * contain valid values, has checksum errors, etc.)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_BAD 0x3
+/* enum: Set when module unsupported (e.g. unsupported link rate or link
+ * technology)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_UNSUPPORTED 0x4
+/* enum: Set on error while communicating with the module (e.g. I2C errors
+ * while reading EEPROM)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_COMMS_FAULT 0x5
+/* enum: Set on module overcurrent/overvoltage condition */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_POWER_FAULT 0x6
+/* enum: Set on module overtemperature condition */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_THERMAL_FAULT 0x7
+/* enum: If set, the module is indicating Loss of Signal */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_LOS 0x8
+/* enum: If set, PMA is indicating loss of CDR lock (clock sync) */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMA_NO_CDR_LOCK 0x9
+/* enum: If set, PMA is indicating loss of analog signal */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMA_LOS 0xa
+/* enum: If set, PCS is indicating loss of block lock */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_NO_BLOCK_LOCK 0xb
+/* enum: If set, PCS is indicating loss of alignment marker lock on one or more
+ * lanes
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_NO_AM_LOCK 0xc
+/* enum: If set, PCS is indicating loss of overall alignment lock */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_NO_ALIGN_LOCK 0xd
+/* enum: If set, PCS is indicating high bit error rate condition. */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_HI_BER 0xe
+/* enum: If set, FEC is indicating loss of FEC lock */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_NO_LOCK 0xf
+/* enum: If set, indicates that the number of symbol errors in a 8192-codeword
+ * window has exceeded the threshold K (417).
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_HI_SER 0x10
+/* enum: If set, the receiver has detected the local FEC has degraded. */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_LOCAL_DEGRADED 0x11
+/* enum: If set, the receiver has detected the remote FEC has degraded. */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_RM_DEGRADED 0x12
+/* enum: If set, the number of symbol errors is over an internal threshold. */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_DEGRADED_SER 0x13
+/* enum: If set, autonegotiation has detected an auto-negotiation capable link
+ * partner
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_ABLE 0x14
+/* enum: If set, autonegotiation base page exchange has failed */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_BP_FAILED 0x15
+/* enum: If set, autonegotiation next page exchange has failed */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_NP_FAILED 0x16
+/* enum: If set, autonegotiation has failed to negotiate a common set of
+ * capabilities
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_NO_HCD 0x17
+/* enum: If set, local end link training has failed to establish link training
+ * frame lock on one or more lanes
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_LT_NO_LOCAL_FRAME_LOCK 0x18
+/* enum: If set, remote end link training has failed to establish link training
+ * frame lock on one or more lanes
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_LT_NO_RM_FRAME_LOCK 0x19
+/* enum: If set, remote end has failed to assert Receiver Ready (link training
+ * success) within the designated timeout
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_LT_NO_RX_READY 0x1a
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LBN 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_WIDTH 64
+
+/* MC_CMD_PAUSE_MODE structuredef */
+#define	MC_CMD_PAUSE_MODE_LEN 1
+#define	MC_CMD_PAUSE_MODE_TYPE_OFST 0
+#define	MC_CMD_PAUSE_MODE_TYPE_LEN 1
+/* enum: See IEEE 802.3 Clause 73.6.6 */
+#define	MC_CMD_PAUSE_MODE_AN_PAUSE 0x0
+/* enum: See IEEE 802.3 Clause 73.6.6 */
+#define	MC_CMD_PAUSE_MODE_AN_ASYM_DIR 0x1
+#define	MC_CMD_PAUSE_MODE_TYPE_LBN 0
+#define	MC_CMD_PAUSE_MODE_TYPE_WIDTH 8
+
+/* MC_CMD_ETH_AN_FIELDS structuredef: Fields used for IEEE 802.3 Clause 73
+ * Auto-Negotiation. Warning - This is fixed size and cannot be extended. This
+ * structure is used to define autonegotiable abilities (advertised, link
+ * partner and supported abilities).
+ */
+#define	MC_CMD_ETH_AN_FIELDS_LEN 25
+/* Mask of Ethernet technologies. The bit indices in this mask are taken from
+ * the TECH field in the MC_CMD_ETH_TECH structure.
+ */
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_OFST 0
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_LEN 16
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_LBN 0
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_WIDTH 128
+/* Mask of supported FEC modes */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_OFST 16
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_LBN 128
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_WIDTH 32
+/* Mask of requested FEC modes */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_OFST 20
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_LBN 160
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_WIDTH 32
+/* Bitmask of negotiated pause modes */
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_OFST 24
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LBN 192
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_WIDTH 8
+
+/* MC_CMD_LOOPBACK_V2 structuredef: Loopback modes for use with the new
+ * MC_CMD_LINK_CTRL and MC_CMD_LINK_STATE. These loopback modes are not
+ * supported in other getlink/setlink commands.
+ */
+#define	MC_CMD_LOOPBACK_V2_LEN 4
+#define	MC_CMD_LOOPBACK_V2_MODE_OFST 0
+#define	MC_CMD_LOOPBACK_V2_MODE_LEN 4
+/* enum: No loopback */
+#define	MC_CMD_LOOPBACK_V2_NONE 0x0
+/* enum: Let firmware choose a supported loopback mode */
+#define	MC_CMD_LOOPBACK_V2_AUTO 0x1
+/* enum: Loopback after the MAC */
+#define	MC_CMD_LOOPBACK_V2_POST_MAC 0x2
+/* enum: Loopback after the PCS */
+#define	MC_CMD_LOOPBACK_V2_POST_PCS 0x3
+/* enum: Loopback after the PMA */
+#define	MC_CMD_LOOPBACK_V2_POST_PMA 0x4
+/* enum: Loopback after the MDI Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_MDI_WS 0x5
+/* enum: Loopback after the PMA Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_PMA_WS 0x6
+/* enum: Loopback after the PCS Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_PCS_WS 0x7
+/* enum: Loopback after the MAC Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_MAC_WS 0x8
+/* enum: Loopback after the MAC FIFOs (before the MAC) */
+#define	MC_CMD_LOOPBACK_V2_PRE_MAC 0x9
+#define	MC_CMD_LOOPBACK_V2_MODE_LBN 0
+#define	MC_CMD_LOOPBACK_V2_MODE_WIDTH 32
+
+/* MC_CMD_FCNTL structuredef */
+#define	MC_CMD_FCNTL_LEN 4
+#define	MC_CMD_FCNTL_MASK_OFST 0
+#define	MC_CMD_FCNTL_MASK_LEN 4
+/* enum: Flow control is off. */
+#define	MC_CMD_FCNTL_OFF 0x0
+/* enum: Respond to flow control. */
+#define	MC_CMD_FCNTL_RESPOND 0x1
+/* enum: Respond to and Issue flow control. */
+#define	MC_CMD_FCNTL_BIDIR 0x2
+/* enum: Auto negotiate flow control. */
+#define	MC_CMD_FCNTL_AUTO 0x3
+/* enum: Priority flow control. This is only supported on KSB. */
+#define	MC_CMD_FCNTL_QBB 0x4
+/* enum: Issue flow control. */
+#define	MC_CMD_FCNTL_GENERATE 0x5
+#define	MC_CMD_FCNTL_MASK_LBN 0
+#define	MC_CMD_FCNTL_MASK_WIDTH 32
+
+/* MC_CMD_LINK_FLAGS structuredef */
+#define	MC_CMD_LINK_FLAGS_LEN 4
+/* The enums defined in this field are used as indices into the
+ * MC_CMD_LINK_FLAGS bitmask.
+ */
+#define	MC_CMD_LINK_FLAGS_MASK_OFST 0
+#define	MC_CMD_LINK_FLAGS_MASK_LEN 4
+/* enum property: bitshift */
+/* enum: Enable auto-negotiation. If AN is enabled, link technology and FEC
+ * mode are determined by advertised capabilities and requested FEC modes,
+ * combined with link partner capabilities. If AN is disabled, link technology
+ * is forced to LINK_TECHNOLOGY and FEC mode is forced to FEC_MODE. Not valid
+ * if loopback is enabled
+ */
+#define	MC_CMD_LINK_FLAGS_AUTONEG_EN 0x0
+/* enum: Enable parallel detect. In addition to AN, try to sense partner forced
+ * speed/FEC mode (when partner AN disabled). Only valid if AN is enabled.
+ */
+#define	MC_CMD_LINK_FLAGS_PARALLEL_DETECT_EN 0x1
+/* enum: Force link down, in electrical idle. */
+#define	MC_CMD_LINK_FLAGS_LINK_DISABLE 0x2
+/* enum: Ignore the sequence number and always apply. */
+#define	MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ 0x3
+#define	MC_CMD_LINK_FLAGS_MASK_LBN 0
+#define	MC_CMD_LINK_FLAGS_MASK_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_LINK_CTRL
+ * Write the unified MAC/PHY link configuration. Locks required: None. Return
+ * code: 0, EINVAL, ETIME, EAGAIN
+ */
+#define	MC_CMD_LINK_CTRL 0x6b
+#define	MC_CMD_LINK_CTRL_MSGSET 0x6b
+#undef	MC_CMD_0x6b_PRIVILEGE_CTG
+
+#define	MC_CMD_0x6b_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_LINK_CTRL_IN msgrequest */
+#define	MC_CMD_LINK_CTRL_IN_LEN 40
+/* Handle to the port to set link state for. */
+#define	MC_CMD_LINK_CTRL_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_LINK_CTRL_IN_PORT_HANDLE_LEN 4
+/* Control flags */
+#define	MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_OFST 4
+#define	MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Reserved for future expansion, and included to provide padding for alignment
+ * purposes.
+ */
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_OFST 8
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LEN 8
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_OFST 8
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_LEN 4
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_LBN 64
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_WIDTH 32
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_OFST 12
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_LEN 4
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_LBN 96
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_WIDTH 32
+/* Technology abilities to advertise during auto-negotiation */
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_OFST 16
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_LEN 16
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Pause abilities to advertise during auto-negotiation. Valid when auto-
+ * negotation is enabled and MC_CMD_SET_MAC_IN/FCTL is set to
+ * MC_CMD_FCNTL_AUTO. If auto-negotiation is disabled the driver must
+ * explicitly configure pause mode with MC_CMD_SET_MAC.
+ */
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_OFST 32
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* When auto-negotiation is enabled, this is the FEC mode to request. Note that
+ * a weaker FEC mode may get negotiated, depending on what the link partner
+ * supports. The driver should subsequently use MC_CMD_GET_LINK to check the
+ * actual negotiated FEC mode. When auto-negotiation is disabled, this is the
+ * forced FEC mode.
+ */
+#define	MC_CMD_LINK_CTRL_IN_FEC_MODE_OFST 33
+#define	MC_CMD_LINK_CTRL_IN_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* This is only to be used when auto-negotiation is disabled (forced speed or
+ * loopback mode). If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_OFST 36
+#define	MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* The sequence number of the last MODULECHANGE event. If this doesn't match,
+ * fail with EAGAIN.
+ */
+#define	MC_CMD_LINK_CTRL_IN_MODULE_SEQ_OFST 38
+#define	MC_CMD_LINK_CTRL_IN_MODULE_SEQ_LEN 1
+/* Loopback Mode. Only valid when auto-negotiation is disabled. */
+#define	MC_CMD_LINK_CTRL_IN_LOOPBACK_OFST 39
+#define	MC_CMD_LINK_CTRL_IN_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+
+/* MC_CMD_LINK_CTRL_OUT msgresponse */
+#define	MC_CMD_LINK_CTRL_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_LINK_STATE
+ */
+#define	MC_CMD_LINK_STATE 0x6c
+#define	MC_CMD_LINK_STATE_MSGSET 0x6c
+#undef	MC_CMD_0x6c_PRIVILEGE_CTG
+
+#define	MC_CMD_0x6c_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_LINK_STATE_IN msgrequest */
+#define	MC_CMD_LINK_STATE_IN_LEN 4
+/* Handle to the port to get link state for. */
+#define	MC_CMD_LINK_STATE_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_LINK_STATE_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_LINK_STATE_OUT msgresponse */
+#define	MC_CMD_LINK_STATE_OUT_LEN 114
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+/* Configured technology. If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_OFST 8
+#define	MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Configured FEC mode */
+#define	MC_CMD_LINK_STATE_OUT_FEC_MODE_OFST 10
+#define	MC_CMD_LINK_STATE_OUT_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* Bitmask of auto-negotiated pause modes */
+#define	MC_CMD_LINK_STATE_OUT_PAUSE_MASK_OFST 11
+#define	MC_CMD_LINK_STATE_OUT_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* Configured loopback mode */
+#define	MC_CMD_LINK_STATE_OUT_LOOPBACK_OFST 12
+#define	MC_CMD_LINK_STATE_OUT_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* Abilities requested by the driver to advertise during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_LEN 32
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_OFST 32
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_OFST 36
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_OFST 40
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_LEN 1
+/* Abilities advertised by the link partner during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_LEN 32
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_OFST 64
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_OFST 68
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_OFST 72
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_LEN 1
+/* Abilities supported by the local device (including cable abilities) For
+ * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
+ */
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_LEN 28
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_OFST 96
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_OFST 100
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_OFST 104
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_LEN 1
+/* Control flags */
+#define	MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_OFST 108
+#define	MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Sequence number to synchronize link change events */
+#define	MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_OFST 112
+#define	MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_LEN 1
+/* Sequence number to synchronize module change events */
+#define	MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 113
+#define	MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+
+/* MC_CMD_LINK_STATE_OUT_V2 msgresponse: Updated LINK_STATE_OUT with
+ * LOCAL_AN_SUPPORT
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_LEN 120
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+/* Configured technology. If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_OFST 8
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Configured FEC mode */
+#define	MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_OFST 10
+#define	MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* Bitmask of auto-negotiated pause modes */
+#define	MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_OFST 11
+#define	MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* Configured loopback mode */
+#define	MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_OFST 12
+#define	MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* Abilities requested by the driver to advertise during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_LEN 32
+/* Abilities advertised by the link partner during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_LEN 32
+/* Abilities supported by the local device (including cable abilities) For
+ * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_LEN 28
+/* Control flags */
+#define	MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_OFST 108
+#define	MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Sequence number to synchronize link change events */
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_OFST 112
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_LEN 1
+/* Sequence number to synchronize module change events */
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_OFST 113
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+/* Reports the auto-negotiation supported by the local device. This depends on
+ * the port and module properties.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_OFST 116
+#define	MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_LEN 4
+/*            Enum values, see field(s): */
+/*               AN_TYPE/TYPE */
+
+/* MC_CMD_LINK_STATE_OUT_V3 msgresponse: Updated LINK_STATE_OUT_V2 for explicit
+ * reporting of the link speed and duplex mode.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LEN 128
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+/* Configured technology. If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_OFST 8
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Configured FEC mode */
+#define	MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_OFST 10
+#define	MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* Bitmask of auto-negotiated pause modes */
+#define	MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_OFST 11
+#define	MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* Configured loopback mode */
+#define	MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_OFST 12
+#define	MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* Abilities requested by the driver to advertise during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_LEN 32
+/* Abilities advertised by the link partner during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_LEN 32
+/* Abilities supported by the local device (including cable abilities) For
+ * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_LEN 28
+/* Control flags */
+#define	MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_OFST 108
+#define	MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Sequence number to synchronize link change events */
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_OFST 112
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_LEN 1
+/* Sequence number to synchronize module change events */
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_OFST 113
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+/* Reports the auto-negotiation supported by the local device. This depends on
+ * the port and module properties.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_OFST 116
+#define	MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_LEN 4
+/*            Enum values, see field(s): */
+/*               AN_TYPE/TYPE */
+/* Autonegotiated speed in mbit/s. The link may still be down even if this
+ * reads non-zero. LINK_SPEED field is intended to be used by drivers without
+ * the most up-to-date MCDI definitions, unable to deduce the link speed from
+ * the reported LINK_TECHNOLOGY field.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_OFST 120
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_FLAGS_OFST 124
+#define	MC_CMD_LINK_STATE_OUT_V3_FLAGS_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_OFST 124
+#define	MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_WIDTH 1
+
 
 /***********************************/
 /* MC_CMD_GET_LINK
@@ -6383,6 +7329,7 @@
 /* This returns the negotiated flow control value. */
 #define	MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
 #define	MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
+/* enum property: value */
 /*            Enum values, see field(s): */
 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
 #define	MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
@@ -6451,6 +7398,7 @@
 /* This returns the negotiated flow control value. */
 #define	MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
 #define	MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
+/* enum property: value */
 /*            Enum values, see field(s): */
 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
 #define	MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
@@ -6764,17 +7712,17 @@
 #define	MC_CMD_SET_MAC_IN_FCNTL_OFST 20
 #define	MC_CMD_SET_MAC_IN_FCNTL_LEN 4
 /* enum: Flow control is off. */
-#define	MC_CMD_FCNTL_OFF 0x0
+/*               MC_CMD_FCNTL_OFF 0x0 */
 /* enum: Respond to flow control. */
-#define	MC_CMD_FCNTL_RESPOND 0x1
+/*               MC_CMD_FCNTL_RESPOND 0x1 */
 /* enum: Respond to and Issue flow control. */
-#define	MC_CMD_FCNTL_BIDIR 0x2
-/* enum: Auto neg flow control. */
-#define	MC_CMD_FCNTL_AUTO 0x3
-/* enum: Priority flow control (eftest builds only). */
-#define	MC_CMD_FCNTL_QBB 0x4
+/*               MC_CMD_FCNTL_BIDIR 0x2 */
+/* enum: Auto negotiate flow control. */
+/*               MC_CMD_FCNTL_AUTO 0x3 */
+/* enum: Priority flow control. This is only supported on KSB. */
+/*               MC_CMD_FCNTL_QBB 0x4 */
 /* enum: Issue flow control. */
-#define	MC_CMD_FCNTL_GENERATE 0x5
+/*               MC_CMD_FCNTL_GENERATE 0x5 */
 #define	MC_CMD_SET_MAC_IN_FLAGS_OFST 24
 #define	MC_CMD_SET_MAC_IN_FLAGS_LEN 4
 #define	MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
@@ -6816,9 +7764,9 @@
 /*               MC_CMD_FCNTL_RESPOND 0x1 */
 /* enum: Respond to and Issue flow control. */
 /*               MC_CMD_FCNTL_BIDIR 0x2 */
-/* enum: Auto neg flow control. */
+/* enum: Auto negotiate flow control. */
 /*               MC_CMD_FCNTL_AUTO 0x3 */
-/* enum: Priority flow control (eftest builds only). */
+/* enum: Priority flow control. This is only supported on KSB. */
 /*               MC_CMD_FCNTL_QBB 0x4 */
 /* enum: Issue flow control. */
 /*               MC_CMD_FCNTL_GENERATE 0x5 */
@@ -6885,9 +7833,9 @@
 /*               MC_CMD_FCNTL_RESPOND 0x1 */
 /* enum: Respond to and Issue flow control. */
 /*               MC_CMD_FCNTL_BIDIR 0x2 */
-/* enum: Auto neg flow control. */
+/* enum: Auto negotiate flow control. */
 /*               MC_CMD_FCNTL_AUTO 0x3 */
-/* enum: Priority flow control (eftest builds only). */
+/* enum: Priority flow control. This is only supported on KSB. */
 /*               MC_CMD_FCNTL_QBB 0x4 */
 /* enum: Issue flow control. */
 /*               MC_CMD_FCNTL_GENERATE 0x5 */
@@ -7542,6 +8490,36 @@
 /*            Other enum values, see field(s): */
 /*               MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
 
+/* MC_CMD_MAC_STATS_V5_OUT_DMA msgresponse */
+#define	MC_CMD_MAC_STATS_V5_OUT_DMA_LEN 0
+
+/* MC_CMD_MAC_STATS_V5_OUT_NO_DMA msgresponse */
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V5*64))>>3)
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_OFST 0
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LEN 8
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V5
+/* enum property: index */
+/* enum: Start of V5 stats buffer space */
+#define	MC_CMD_MAC_V5_DMABUF_START 0x7c
+/* enum: Link toggle counter: Number of times the link has toggled between
+ * up/down and down/up
+ */
+#define	MC_CMD_MAC_LINK_TOGGLES 0x7c
+/* enum: This includes the space at offset 125 which is the final
+ * GENERATION_END in a MAC_STATS_V5 response and otherwise unused.
+ */
+#define	MC_CMD_MAC_NSTATS_V5 0x7e
+/*            Other enum values, see field(s): */
+/*               MC_CMD_MAC_STATS_V4_OUT_NO_DMA/STATISTICS */
+
 
 /***********************************/
 /* MC_CMD_SRIOV
@@ -9410,6 +10388,28 @@
 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
 #define	MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
 
+/* MC_CMD_GET_RESOURCE_LIMITS_IN_V2 msgrequest */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_LEN 8
+/* What type of allocation to count. */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_REQUEST_TYPE_OFST 0
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_REQUEST_TYPE_LEN 4
+/* enum: Command returns the number of each resource that the function has
+ * currently allocated.
+ */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_ALLOCATED 0x0
+/* enum: Command returns the maximum number of each resource that it could be
+ * possible for the function to allocate (ie assuming that other functions have
+ * nothing allocated beyond their minimum reservations (if any).
+ */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_MAX_POSSIBLE 0x1
+/* What type of resource to count. */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_RESOURCE_TYPE_OFST 4
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_RESOURCE_TYPE_LEN 4
+/* enum: Count full-featured (X2-style) queues */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_FULL_FEATURED_QUEUE 0x0
+/* enum: Count low-latency (X3-style) queues */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_LOW_LATENCY_QUEUE 0x1
+
 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
@@ -10515,7 +11515,7 @@
 /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
  * Get descriptions for a set of sensors, specified as an array of sensor
  * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. Any handles which do not
- * correspond to a sensor currently managed by the MC will be dropped from
+ * correspond to a sensor currently managed by the MC will be dropped from from
  * the response. This may happen when a sensor table update is in progress, and
  * effectively means the set of usable sensors is the intersection between the
  * sets of sensors known to the driver and the MC. On Riverhead this command is
@@ -10562,7 +11562,7 @@
  * broken sensor, then the state of the response's MC_CMD_DYNAMIC_SENSORS_VALUE
  * entry will be set to BROKEN, and any value provided should be treated as
  * erroneous. Any handles which do not correspond to a sensor currently managed
- * by the MC will be dropped from the response. This may happen when a
+ * by the MC will be dropped from from the response. This may happen when a
  * sensor table update is in progress, and effectively means the set of usable
  * sensors is the intersection between the sets of sensors known to the driver
  * and the MC. On Riverhead this command is implemented as a wrapper for
@@ -10641,6 +11641,2644 @@
 /* MC_CMD_EVENT_CTRL_OUT msgrequest */
 #define	MC_CMD_EVENT_CTRL_OUT_LEN 0
 
+/* HNIC_FIFO_SIZE_PARAMS structuredef: HNIC FIFO size parameters */
+#define	HNIC_FIFO_SIZE_PARAMS_LEN 12
+/* FIFO handle */
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_WIDTH 32
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_OFST 4
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_LEN 4
+#define	HNIC_FIFO_SIZE_PARAMS_ENABLED_OFST 4
+#define	HNIC_FIFO_SIZE_PARAMS_ENABLED_LBN 0
+#define	HNIC_FIFO_SIZE_PARAMS_ENABLED_WIDTH 1
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_LBN 32
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_WIDTH 32
+/* Bytes allocated to this FIFO */
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_OFST 8
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_LEN 4
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_LBN 64
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_WIDTH 32
+
+/* HNIC_FIFO_DELAY_PARAMS structuredef: HNIC FIFO delay parameters */
+#define	HNIC_FIFO_DELAY_PARAMS_LEN 16
+/* FIFO handle */
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_WIDTH 32
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_OFST 4
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_OVERRIDE_OFST 4
+#define	HNIC_FIFO_DELAY_PARAMS_OVERRIDE_LBN 0
+#define	HNIC_FIFO_DELAY_PARAMS_OVERRIDE_WIDTH 1
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_LBN 32
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_WIDTH 32
+/* XOFF threshold Only applies if the OVERRIDE flag is set. Represented in
+ * bytes
+ */
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_OFST 8
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_LBN 64
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_WIDTH 32
+/* XON threshold Only applies if the OVERRIDE flag is set. Represented in bytes
+ */
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_OFST 12
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_LBN 96
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_CONFIG
+ * Query the static HNIC port configuration for a physical port. Returns ENODEV
+ * if the target does not correspond to a physical port, or EPERM if the caller
+ * does not have permission to administer it. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_CONFIG instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG 0x1d6
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_MSGSET 0x1d6
+#undef	MC_CMD_0x1d6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_CONFIG_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_CONFIG_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LENMIN 12
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LENMAX 252
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LEN(num) (12+4*(num))
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_NUM(len) (((len)-12)/4)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_REGION_SIZE_LEN 4
+/* Allocation granularity, in bytes. All partitioning of the buffer region must
+ * be in multiples of this value.
+ */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_LEN 4
+/* Array of FIFO handles, NUM_FIFOS items long. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_OFST 12
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MINNUM 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM 60
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM_MCDI2 252
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_FIFO_SIZING
+ * Returns the current state of the FIFO sizing configuration for all of the
+ * FIFOs assigned to a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING 0x1d7
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_MSGSET 0x1d7
+#undef	MC_CMD_0x1d7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LENMIN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LENMAX 248
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LEN(num) (8+12*(num))
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_NUM(len) (((len)-8)/12)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM 20
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 84
+
+
+/***********************************/
+/* MC_CMD_SET_HNIC_PORT_FIFO_SIZING
+ * Sets the FIFO sizing configuration for a physical port. This is disruptive
+ * to port operation and will cause the link to drop while the port is
+ * reconfigured. Returns ENODEV if the target does not correspond to a physical
+ * port, or EPERM if the caller does not have permission to administer it, or
+ * EINVAL if the sizing parameters are invalid. This command is deprecated. Use
+ * MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING instead.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING 0x1d8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_MSGSET 0x1d8
+#undef	MC_CMD_0x1d8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LENMIN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LENMAX 244
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LENMAX_MCDI2 1012
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LEN(num) (16+12*(num))
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_NUM(len) (((len)-16)/12)
+/* Target port to configure. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies
+ * the port by MAE port and link end, but this must correspond to a physical
+ * port to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current size configuration.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_OFST 12
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_OFST 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM 19
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 83
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_PRIO_MAPPING
+ * Returns the current state of the 802.1Q priority to FIFO mapping
+ * configuration for a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING 0x1d9
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1d9
+#undef	MC_CMD_0x1d9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_LEN 32
+/* FIFO handle for each Priority Code Point(PCP), in order from 0 to 7. */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_NUM 8
+
+
+/***********************************/
+/* MC_CMD_SET_HNIC_PORT_PRIO_MAPPING
+ * Sets the PCP priority to FIFO mapping configuration for a physical port.
+ * Returns ENODEV if the target does not correspond to a physical port, or
+ * EPERM if the caller does not have permission to administer it, or EINVAL if
+ * any of the FIFO handles are invalid in some way. This command is deprecated.
+ * Use MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING instead.
+ */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING 0x1da
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1da
+#undef	MC_CMD_0x1da_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1da_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_LEN 44
+/* Target port to configure. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies
+ * the port by MAE port and link end, but this must correspond to a physical
+ * port to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 8
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* FIFO handle for each PCP value, in order from 0 to 7. */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_OFST 12
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_NUM 8
+
+/* MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Returns the current state of the FIFO delay parameters configuration for all
+ * of the FIFOs assigned to a physical port. Returns ENODEV if the target does
+ * not correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS 0x1db
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1db
+#undef	MC_CMD_0x1db_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1db_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMIN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX 244
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX_MCDI2 1012
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN(num) (4+16*(num))
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_NUM(len) (((len)-4)/16)
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM 15
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 63
+
+
+/***********************************/
+/* MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Sets the FIFO delay parameters configuration for a physical port. This is
+ * not disruptive to port operation. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it, or EINVAL if the sizing parameters are invalid.
+ * This command is deprecated. Use MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS
+ * instead
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS 0x1dc
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1dc
+#undef	MC_CMD_0x1dc_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1dc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMIN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX 240
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX_MCDI2 1008
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN(num) (16+16*(num))
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_NUM(len) (((len)-16)/16)
+/* Target port to configure. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies
+ * the port by MAE port and link end, but this must correspond to a physical
+ * port to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current delay
+ * configuration.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_OFST 12
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_OFST 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM 14
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 62
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN 0
+
+/* MC_CMD_MAC_FLAGS structuredef */
+#define	MC_CMD_MAC_FLAGS_LEN 4
+/* The enums defined in this field are used as indices into the
+ * MC_CMD_MAC_FLAGS bitmask.
+ */
+#define	MC_CMD_MAC_FLAGS_MASK_OFST 0
+#define	MC_CMD_MAC_FLAGS_MASK_LEN 4
+/* enum property: bitshift */
+/* enum: Include the FCS in the packet data delivered to the host. Ignored if
+ * RX_INCLUDE_FCS not set in capabilities.
+ */
+#define	MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS 0x0
+#define	MC_CMD_MAC_FLAGS_MASK_LBN 0
+#define	MC_CMD_MAC_FLAGS_MASK_WIDTH 32
+
+/* MC_CMD_TRANSMISSION_MODE structuredef */
+#define	MC_CMD_TRANSMISSION_MODE_LEN 4
+#define	MC_CMD_TRANSMISSION_MODE_MASK_OFST 0
+#define	MC_CMD_TRANSMISSION_MODE_MASK_LEN 4
+/* enum property: value */
+#define	MC_CMD_TRANSMISSION_MODE_PROMSC_MODE 0x0 /* enum */
+#define	MC_CMD_TRANSMISSION_MODE_UNCST_MODE 0x1 /* enum */
+#define	MC_CMD_TRANSMISSION_MODE_BRDCST_MODE 0x2 /* enum */
+#define	MC_CMD_TRANSMISSION_MODE_MASK_LBN 0
+#define	MC_CMD_TRANSMISSION_MODE_MASK_WIDTH 32
+
+/* MC_CMD_MAC_CONFIG_OPTIONS structuredef */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_LEN 4
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_OFST 0
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_LEN 4
+/* enum property: bitmask */
+/* enum: Configure the MAC address. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_ADDR 0x0
+/* enum: Configure the maximum frame length. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN 0x1
+/* enum: Configure flow control. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL 0x2
+/* enum: Configure the transmission mode. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_TRANSMISSION_MODE 0x3
+/* enum: Configure FCS. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS 0x4
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_LBN 0
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_MAC_CTRL
+ * Set MAC configuration. Return code: 0, EINVAL, ENOTSUP
+ */
+#define	MC_CMD_MAC_CTRL 0x1df
+#define	MC_CMD_MAC_CTRL_MSGSET 0x1df
+#undef	MC_CMD_0x1df_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1df_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_MAC_CTRL_IN msgrequest */
+#define	MC_CMD_MAC_CTRL_IN_LEN 32
+/* Handle for selected network port. */
+#define	MC_CMD_MAC_CTRL_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_CTRL_IN_PORT_HANDLE_LEN 4
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set.
+ */
+#define	MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_OFST 4
+#define	MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_CONFIG_OPTIONS/MASK */
+/* MAC address of the device. */
+#define	MC_CMD_MAC_CTRL_IN_ADDR_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LEN 8
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_WIDTH 32
+/* Includes the ethernet header, optional VLAN tags, payload and FCS. */
+#define	MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_OFST 16
+#define	MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_LEN 4
+/* Settings for flow control. */
+#define	MC_CMD_MAC_CTRL_IN_FCNTL_OFST 20
+#define	MC_CMD_MAC_CTRL_IN_FCNTL_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_FCNTL/MASK */
+/* Configure the MAC to transmit in one of promiscuous, unicast or broadcast
+ * mode.
+ */
+#define	MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_OFST 24
+#define	MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_TRANSMISSION_MODE/MASK */
+/* Flags to control and expand the configuration of the MAC. */
+#define	MC_CMD_MAC_CTRL_IN_FLAGS_OFST 28
+#define	MC_CMD_MAC_CTRL_IN_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_FLAGS/MASK */
+
+/* MC_CMD_MAC_CTRL_IN_V2 msgrequest: Updated MAC_CTRL with QBB mask */
+#define	MC_CMD_MAC_CTRL_IN_V2_LEN 33
+/* Handle for selected network port. */
+#define	MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_LEN 4
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set.
+ */
+#define	MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_OFST 4
+#define	MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_CONFIG_OPTIONS/MASK */
+/* MAC address of the device. */
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LEN 8
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_WIDTH 32
+/* Includes the ethernet header, optional VLAN tags, payload and FCS. */
+#define	MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_OFST 16
+#define	MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_LEN 4
+/* Settings for flow control. */
+#define	MC_CMD_MAC_CTRL_IN_V2_FCNTL_OFST 20
+#define	MC_CMD_MAC_CTRL_IN_V2_FCNTL_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_FCNTL/MASK */
+/* Configure the MAC to transmit in one of promiscuous, unicast or broadcast
+ * mode.
+ */
+#define	MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_OFST 24
+#define	MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_TRANSMISSION_MODE/MASK */
+/* Flags to control and expand the configuration of the MAC. */
+#define	MC_CMD_MAC_CTRL_IN_V2_FLAGS_OFST 28
+#define	MC_CMD_MAC_CTRL_IN_V2_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_FLAGS/MASK */
+/* Priority-based flow control mask (QBB). PRIO7 corresponds to the highest
+ * priority, and PRIO0 to the lowest. This field is only used when CFG_FCNTL is
+ * set and FCNTL is QBB
+ */
+#define	MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_OFST 32
+#define	MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_LEN 1
+/* enum property: bitmask */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO0 0x0 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO1 0x1 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO2 0x2 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO3 0x3 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO4 0x4 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO5 0x5 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO6 0x6 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO7 0x7 /* enum */
+
+/* MC_CMD_MAC_CTRL_OUT msgresponse */
+#define	MC_CMD_MAC_CTRL_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_MAC_STATE
+ * Read the MAC state. Return code: 0, ETIME.
+ */
+#define	MC_CMD_MAC_STATE 0x1e0
+#define	MC_CMD_MAC_STATE_MSGSET 0x1e0
+#undef	MC_CMD_0x1e0_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e0_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_MAC_STATE_IN msgrequest */
+#define	MC_CMD_MAC_STATE_IN_LEN 4
+/* Handle for selected network port. */
+#define	MC_CMD_MAC_STATE_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_STATE_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_MAC_STATE_OUT msgresponse */
+#define	MC_CMD_MAC_STATE_OUT_LEN 32
+/* The configured maximum frame length of the MAC. */
+#define	MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_OFST 0
+#define	MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_LEN 4
+/* This returns the negotiated flow control value. */
+#define	MC_CMD_MAC_STATE_OUT_FCNTL_OFST 4
+#define	MC_CMD_MAC_STATE_OUT_FCNTL_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_FCNTL/MASK */
+/* MAC address of the device. */
+#define	MC_CMD_MAC_STATE_OUT_ADDR_OFST 8
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LEN 8
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_WIDTH 32
+/* Flags indicating MAC faults. */
+#define	MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_OFST 16
+#define	MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_LEN 4
+/* enum property: bitshift */
+/* enum: Indicates a local MAC fault. */
+#define	MC_CMD_MAC_STATE_OUT_LOCAL 0x0
+/* enum: Indicates a remote MAC fault. */
+#define	MC_CMD_MAC_STATE_OUT_REMOTE 0x1
+/* enum: Indicates a pending reconfiguration of the MAC. */
+#define	MC_CMD_MAC_STATE_OUT_PENDING_RECONFIG 0x2
+/* The flags that were used to configure the MAC. This is a copy of the FLAGS
+ * field in the MC_CMD_MAC_CTRL_IN command.
+ */
+#define	MC_CMD_MAC_STATE_OUT_FLAGS_OFST 20
+#define	MC_CMD_MAC_STATE_OUT_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_FLAGS/MASK */
+/* The transmission mode that was used to configure the MAC. This is a copy of
+ * the TRANSMISSION_MODE field in the MC_CMD_MAC_CTRL_IN command.
+ */
+#define	MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_OFST 24
+#define	MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_TRANSMISSION_MODE/MASK */
+/* The control flags that were used to configure the MAC. This is a copy of the
+ * CONTROL field in the MC_CMD_MAC_CTRL_IN command.
+ */
+#define	MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_OFST 28
+#define	MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_CONFIG_OPTIONS/MASK */
+
+
+/***********************************/
+/* MC_CMD_GET_MPORT_HANDLE
+ * Obtain a handle to an mport identified by the provided target. Return code:
+ * 0, ENOENT
+ */
+#define	MC_CMD_GET_MPORT_HANDLE 0x1e1
+#define	MC_CMD_GET_MPORT_HANDLE_MSGSET 0x1e1
+#undef	MC_CMD_0x1e1_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e1_PRIVILEGE_CTG SRIOV_CTG_MAE
+
+/* MC_CMD_GET_MPORT_HANDLE_IN msgrequest */
+#define	MC_CMD_GET_MPORT_HANDLE_IN_LEN 4
+/* Virtual port to get handle for. This uses the MAE_LINK_ENDPOINT_SELECTOR
+ * which identifies a real or virtual network port by MAE port and link end.
+ */
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_LEN 4
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_WIDTH 32
+
+/* MC_CMD_GET_MPORT_HANDLE_OUT msgresponse */
+#define	MC_CMD_GET_MPORT_HANDLE_OUT_LEN 4
+/* Handle for selected mport. */
+#define	MC_CMD_GET_MPORT_HANDLE_OUT_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_OUT_PORT_HANDLE_LEN 4
+
+
+/***********************************/
+/* MC_CMD_GET_ASSIGNED_PORT_HANDLE
+ * Obtain a handle that can be operated on to configure and query the status of
+ * the link. ENOENT is returned when no port is assigned to the client. Return
+ * code: 0, ENOENT
+ */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE 0x1e2
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_MSGSET 0x1e2
+#undef	MC_CMD_0x1e2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN msgrequest */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN 0
+
+/* MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT msgresponse */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN 4
+/* Handle for assigned port. */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_LEN 4
+
+/* MC_CMD_STAT_ID structuredef */
+#define	MC_CMD_STAT_ID_LEN 4
+#define	MC_CMD_STAT_ID_SOURCE_ID_OFST 0
+#define	MC_CMD_STAT_ID_SOURCE_ID_LEN 2
+/* enum property: index */
+/* enum: Internal markers (generation start and end markers) */
+#define	MC_CMD_STAT_ID_MARKER 0x1
+/* enum: Network port MAC statistics. */
+#define	MC_CMD_STAT_ID_MAC 0x2
+/* enum: Network port PHY statistics. */
+#define	MC_CMD_STAT_ID_PHY 0x3
+#define	MC_CMD_STAT_ID_SOURCE_ID_LBN 0
+#define	MC_CMD_STAT_ID_SOURCE_ID_WIDTH 16
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_OFST 2
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_LEN 2
+/* enum property: index */
+/* enum: This value is used to mark the start of a generation of statistics for
+ * DMA synchronization. It is incremented whenever a new set of statistics is
+ * transferred. Always the first entry in the DMA buffer.
+ */
+#define	MC_CMD_STAT_ID_GENERATION_START 0x1
+/* enum: This value is used to mark the end of a generation of statistics for
+ * DMA synchronizaion. Always the last entry in the DMA buffer and set to the
+ * same value as GENERATION_START. The host driver must compare the
+ * GENERATION_START and GENERATION_END values to verify that the DMA buffer is
+ * consistent upon copying the the DMA buffer. If they do not match, it means
+ * that new DMA transfer has started while the host driver was copying the DMA
+ * buffer. In this case, the host driver must repeat the copy operation.
+ */
+#define	MC_CMD_STAT_ID_GENERATION_END 0x2
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_LBN 16
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_WIDTH 16
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_OFST 2
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_LEN 2
+/* enum property: index */
+/* enum: Total number of packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_PKTS 0x1
+/* enum: Pause frames transmitted. */
+#define	MC_CMD_STAT_ID_TX_PAUSE_PKTS 0x2
+/* enum: Control frames transmitted. */
+#define	MC_CMD_STAT_ID_TX_CONTROL_PKTS 0x3
+/* enum: Unicast packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_UNICAST_PKTS 0x4
+/* enum: Multicast packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_MULTICAST_PKTS 0x5
+/* enum: Broadcast packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_BROADCAST_PKTS 0x6
+/* enum: Bytes transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_BYTES 0x7
+/* enum: Bytes transmitted with bad CRC. */
+#define	MC_CMD_STAT_ID_TX_BAD_BYTES 0x8
+/* enum: Bytes transmitted with good CRC. */
+#define	MC_CMD_STAT_ID_TX_GOOD_BYTES 0x9
+/* enum: Packets transmitted with length less than 64 bytes. */
+#define	MC_CMD_STAT_ID_TX_LT64_PKTS 0xa
+/* enum: Packets transmitted with length equal to 64 bytes. */
+#define	MC_CMD_STAT_ID_TX_64_PKTS 0xb
+/* enum: Packets transmitted with length between 65 and 127 bytes. */
+#define	MC_CMD_STAT_ID_TX_65_TO_127_PKTS 0xc
+/* enum: Packets transmitted with length between 128 and 255 bytes. */
+#define	MC_CMD_STAT_ID_TX_128_TO_255_PKTS 0xd
+/* enum: Packets transmitted with length between 256 and 511 bytes. */
+#define	MC_CMD_STAT_ID_TX_256_TO_511_PKTS 0xe
+/* enum: Packets transmitted with length between 512 and 1023 bytes. */
+#define	MC_CMD_STAT_ID_TX_512_TO_1023_PKTS 0xf
+/* enum: Packets transmitted with length between 1024 and 1518 bytes. */
+#define	MC_CMD_STAT_ID_TX_1024_TO_15XX_PKTS 0x10
+/* enum: Packets transmitted with length between 1519 and 9216 bytes. */
+#define	MC_CMD_STAT_ID_TX_15XX_TO_JUMBO_PKTS 0x11
+/* enum: Packets transmitted with length greater than 9216 bytes. */
+#define	MC_CMD_STAT_ID_TX_GTJUMBO_PKTS 0x12
+/* enum: Packets transmitted with bad FCS. */
+#define	MC_CMD_STAT_ID_TX_BAD_FCS_PKTS 0x13
+/* enum: Packets transmitted with good FCS. */
+#define	MC_CMD_STAT_ID_TX_GOOD_FCS_PKTS 0x14
+/* enum: Packets received. */
+#define	MC_CMD_STAT_ID_RX_PKTS 0x15
+/* enum: Pause frames received. */
+#define	MC_CMD_STAT_ID_RX_PAUSE_PKTS 0x16
+/* enum: Total number of good packets received. */
+#define	MC_CMD_STAT_ID_RX_GOOD_PKTS 0x17
+/* enum: Total number of BAD packets received. */
+#define	MC_CMD_STAT_ID_RX_BAD_PKTS 0x18
+/* enum: Total number of control frames received. */
+#define	MC_CMD_STAT_ID_RX_CONTROL_PKTS 0x19
+/* enum: Total number of unicast packets received. */
+#define	MC_CMD_STAT_ID_RX_UNICAST_PKTS 0x1a
+/* enum: Total number of multicast packets received. */
+#define	MC_CMD_STAT_ID_RX_MULTICAST_PKTS 0x1b
+/* enum: Total number of broadcast packets received. */
+#define	MC_CMD_STAT_ID_RX_BROADCAST_PKTS 0x1c
+/* enum: Total number of bytes received. */
+#define	MC_CMD_STAT_ID_RX_BYTES 0x1d
+/* enum: Total number of bytes received with bad CRC. */
+#define	MC_CMD_STAT_ID_RX_BAD_BYTES 0x1e
+/* enum: Total number of bytes received with GOOD CRC. */
+#define	MC_CMD_STAT_ID_RX_GOOD_BYTES 0x1f
+/* enum: Packets received with length equal to 64 bytes. */
+#define	MC_CMD_STAT_ID_RX_64_PKTS 0x20
+/* enum: Packets received with length between 65 and 127 bytes. */
+#define	MC_CMD_STAT_ID_RX_65_TO_127_PKTS 0x21
+/* enum: Packets received with length between 128 and 255 bytes. */
+#define	MC_CMD_STAT_ID_RX_128_TO_255_PKTS 0x22
+/* enum: Packets received with length between 256 and 511 bytes. */
+#define	MC_CMD_STAT_ID_RX_256_TO_511_PKTS 0x23
+/* enum: Packets received with length between 512 and 1023 bytes. */
+#define	MC_CMD_STAT_ID_RX_512_TO_1023_PKTS 0x24
+/* enum: Packets received with length between 1024 and 1518 bytes. */
+#define	MC_CMD_STAT_ID_RX_1024_TO_15XX_PKTS 0x25
+/* enum: Packets received with length between 1519 and 9216 bytes. */
+#define	MC_CMD_STAT_ID_RX_15XX_TO_JUMBO_PKTS 0x26
+/* enum: Packets received with length greater than 9216 bytes. */
+#define	MC_CMD_STAT_ID_RX_GTJUMBO_PKTS 0x27
+/* enum: Packets received with length less than 64 bytes. */
+#define	MC_CMD_STAT_ID_RX_UNDERSIZE_PKTS 0x28
+/* enum: Packets received with bad FCS. */
+#define	MC_CMD_STAT_ID_RX_BAD_FCS_PKTS 0x29
+/* enum: Packets received with GOOD FCS. */
+#define	MC_CMD_STAT_ID_RX_GOOD_FCS_PKTS 0x2a
+/* enum: Packets received with overflow. */
+#define	MC_CMD_STAT_ID_RX_OVERFLOW_PKTS 0x2b
+/* enum: Packets received with symbol error. */
+#define	MC_CMD_STAT_ID_RX_SYMBOL_ERROR_PKTS 0x2c
+/* enum: Packets received with alignment error. */
+#define	MC_CMD_STAT_ID_RX_ALIGN_ERROR_PKTS 0x2d
+/* enum: Packets received with length error. */
+#define	MC_CMD_STAT_ID_RX_LENGTH_ERROR_PKTS 0x2e
+/* enum: Packets received with internal error. */
+#define	MC_CMD_STAT_ID_RX_INTERNAL_ERROR_PKTS 0x2f
+/* enum: Packets received with jabber. These packets are larger than the
+ * allowed maximum receive unit (MRU). This indicates that a packet either has
+ * a bad CRC or has an RX error.
+ */
+#define	MC_CMD_STAT_ID_RX_JABBER_PKTS 0x30
+/* enum: Packets dropped due to having no descriptor. This is a datapath stat
+ */
+#define	MC_CMD_STAT_ID_RX_NODESC_DROPS 0x31
+/* enum: Packets received with lanes 0 and 1 character error. */
+#define	MC_CMD_STAT_ID_RX_LANES01_CHAR_ERR 0x32
+/* enum: Packets received with lanes 2 and 3 character error. */
+#define	MC_CMD_STAT_ID_RX_LANES23_CHAR_ERR 0x33
+/* enum: Packets received with lanes 0 and 1 disparity error. */
+#define	MC_CMD_STAT_ID_RX_LANES01_DISP_ERR 0x34
+/* enum: Packets received with lanes 2 and 3 disparity error. */
+#define	MC_CMD_STAT_ID_RX_LANES23_DISP_ERR 0x35
+/* enum: Packets received with match fault. */
+#define	MC_CMD_STAT_ID_RX_MATCH_FAULT 0x36
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_LBN 16
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_WIDTH 16
+/* Include FEC stats. */
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_OFST 2
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_LEN 2
+/* enum property: index */
+/* enum: Number of uncorrected FEC codewords on link (RS-FEC only from Medford2
+ * onwards)
+ */
+#define	MC_CMD_STAT_ID_FEC_UNCORRECTED_ERRORS 0x1
+/* enum: Number of corrected FEC codewords on link (RS-FEC only from Medford2
+ * onwards)
+ */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_ERRORS 0x2
+/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE0 0x3
+/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE1 0x4
+/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE2 0x5
+/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE3 0x6
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_LBN 16
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_WIDTH 16
+
+/* MC_CMD_STAT_DESC structuredef: Structure describing the layout and size of
+ * the stats DMA buffer descriptor.
+ */
+#define	MC_CMD_STAT_DESC_LEN 8
+/* Unique identifier of the statistic. Formatted as MC_CMD_STAT_ID */
+#define	MC_CMD_STAT_DESC_STAT_ID_OFST 0
+#define	MC_CMD_STAT_DESC_STAT_ID_LEN 4
+#define	MC_CMD_STAT_DESC_STAT_ID_LBN 0
+#define	MC_CMD_STAT_DESC_STAT_ID_WIDTH 32
+/* See structuredef: MC_CMD_STAT_ID */
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_OFST 0
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LBN 0
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_WIDTH 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_OFST 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LBN 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_WIDTH 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_OFST 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LBN 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_WIDTH 16
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_OFST 2
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LBN 16
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_WIDTH 16
+/* Index of the statistic in the DMA buffer. */
+#define	MC_CMD_STAT_DESC_STAT_INDEX_OFST 4
+#define	MC_CMD_STAT_DESC_STAT_INDEX_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_INDEX_LBN 32
+#define	MC_CMD_STAT_DESC_STAT_INDEX_WIDTH 16
+/* Reserved for future extension (e.g. flags field) - currently always 0. */
+#define	MC_CMD_STAT_DESC_RESERVED_OFST 6
+#define	MC_CMD_STAT_DESC_RESERVED_LEN 2
+#define	MC_CMD_STAT_DESC_RESERVED_LBN 48
+#define	MC_CMD_STAT_DESC_RESERVED_WIDTH 16
+
+
+/***********************************/
+/* MC_CMD_MAC_STATISTICS_DESCRIPTOR
+ * Get a list of descriptors that describe the layout and size of the stats
+ * buffer required for retrieving statistics for a given port. Each entry in
+ * the list is formatted as MC_CMD_STAT_DESC and provides the ID of each stat
+ * and its location and size in the buffer. It also gives the overall minimum
+ * size of the DMA buffer required when DMA mode is used. Note that the first
+ * and last entries in the list are reserved for the generation start
+ * (MC_CMD_MARKER_STAT_GENERATION_START) and end
+ * (MC_CMD_MARKER_STAT_GENERATION_END) markers respectively, to be used for DMA
+ * synchronisation as described in the documentation for the relevant enum
+ * entries. The entries are present in the buffer even if DMA mode is not used.
+ * Provisions are made (but currently unused) for extending the size of the
+ * descriptors, extending the size of the list beyond the maximum MCDI response
+ * size, as well as the dynamic runtime updates of the list. Returns: 0 on
+ * success, ENOENT on non-existent port handle
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR 0x1e3
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_MSGSET 0x1e3
+#undef	MC_CMD_0x1e3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN msgrequest */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN 8
+/* Handle of port to get MAC statitstics descriptors for. */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_LEN 4
+/* Offset of the first entry to return, for cases where not all entries fit in
+ * the MCDI response. Should be set to 0 on initial request, and on subsequent
+ * requests updated by the number of entries already returned, as long as the
+ * MORE_ENTRIES flag is set.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_OFST 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_LEN 4
+
+/* MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT msgresponse */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMIN 28
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX 252
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LEN(num) (20+8*(num))
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(len) (((len)-20)/8)
+/* Generation number of the stats buffer. This is incremented each time the
+ * buffer is updated, and is used to verify the consistency of the buffer
+ * contents. Reserved for future extension (dynamic list updates). Currently
+ * always set to 0.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_OFST 0
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_LEN 4
+/* Minimum size of the DMA buffer required to retrieve all statistics for the
+ * port. This is the sum of the sizes of all the statistics, plus the size of
+ * the generation markers. Minimum buffer size in bytes required to fit all
+ * statistics. Drivers will typically round up this value to the granularity of
+ * the host DMA allocation units.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_OFST 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_OFST 8
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_OFST 8
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_LBN 0
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_WIDTH 1
+/* Size of the individual descriptor entry in the list. Determines the entry
+ * stride in the list. Currently always set to size of MC_CMD_STAT_DESC, larger
+ * values can be used in the future for extending the descriptor, by appending
+ * new data to the end of the existing structure.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_OFST 12
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_LEN 4
+/* Number of entries returned in the descriptor list. */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_OFST 16
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_LEN 4
+/* List of descriptors. Each entry is formatted as MC_CMD_STAT_DESC and
+ * provides the ID of each stat and its location and size in the buffer. The
+ * first and last entries are reserved for the generation start and end markers
+ * respectively.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_OFST 20
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LEN 8
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_OFST 20
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LBN 160
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_WIDTH 32
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_OFST 24
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LBN 192
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_WIDTH 32
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MINNUM 1
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM 29
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM_MCDI2 125
+
+
+/***********************************/
+/* MC_CMD_MAC_STATISTICS
+ * Get generic MAC statistics. This call retrieves unified statistics managed
+ * by the MC. The MC will populate and provide all supported statistics in the
+ * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the
+ * aforementioned command for the format and contents of the stats DMA buffer.
+ * To ensure consistent and accurate results, it is essential for the driver to
+ * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
+ * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
+ * handle, and EINVAL on invalid parameters (DMA buffer too small)
+ */
+#define	MC_CMD_MAC_STATISTICS 0x1e4
+#define	MC_CMD_MAC_STATISTICS_MSGSET 0x1e4
+#undef	MC_CMD_0x1e4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_MAC_STATISTICS_IN msgrequest */
+#define	MC_CMD_MAC_STATISTICS_IN_LEN 20
+/* Handle of port to get MAC statistics for. */
+#define	MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_LEN 4
+/* Contains options for querying the MAC statistics. */
+#define	MC_CMD_MAC_STATISTICS_IN_CMD_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_CMD_LEN 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_LBN 0
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_CLEAR_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_CLEAR_LBN 1
+#define	MC_CMD_MAC_STATISTICS_IN_CLEAR_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_LBN 2
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_LBN 3
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_LBN 16
+#define	MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_WIDTH 16
+/* This is the address of the DMA buffer to use for transfer of the statistics.
+ * Only valid if the DMA flag is set to 1.
+ */
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_OFST 8
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LEN 8
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32
+/* This is the length of the DMA buffer to use for the transfer of the
+ * statistics. The buffer should be at least DMA_BUFFER_SIZE long, as returned
+ * by MC_CMD_MAC_STATISTICS_DESCRIPTOR. If the supplied buffer is too small,
+ * the command will fail with EINVAL. Only valid if the DMA flag is set to 1.
+ */
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_LEN_OFST 16
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_LEN_LEN 4
+
+/* MC_CMD_MAC_STATISTICS_OUT msgresponse */
+#define	MC_CMD_MAC_STATISTICS_OUT_LENMIN 5
+#define	MC_CMD_MAC_STATISTICS_OUT_LENMAX 252
+#define	MC_CMD_MAC_STATISTICS_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_MAC_STATISTICS_OUT_LEN(num) (4+1*(num))
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_NUM(len) (((len)-4)/1)
+/* length of the data in bytes */
+#define	MC_CMD_MAC_STATISTICS_OUT_DATALEN_OFST 0
+#define	MC_CMD_MAC_STATISTICS_OUT_DATALEN_LEN 4
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_OFST 4
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_LEN 1
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_MINNUM 1
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM 248
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM_MCDI2 1016
+
+/* NET_PORT_HANDLE_DESC structuredef: Network port descriptor containing a port
+ * handle and attributes used, for example, in MC_CMD_ENUM_PORTS.
+ */
+#define	NET_PORT_HANDLE_DESC_LEN 53
+/* The handle to identify the port */
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_OFST 0
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_LEN 4
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_LBN 0
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_WIDTH 32
+/* Includes the type of port e.g. physical, virtual or MAE MPORT and other
+ * properties relevant to the port.
+ */
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_OFST 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LEN 8
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_OFST 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LEN 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LBN 32
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_WIDTH 32
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_OFST 8
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LEN 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LBN 64
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_WIDTH 32
+#define	NET_PORT_HANDLE_DESC_PORT_TYPE_OFST 4
+#define	NET_PORT_HANDLE_DESC_PORT_TYPE_LBN 0
+#define	NET_PORT_HANDLE_DESC_PORT_TYPE_WIDTH 3
+#define	NET_PORT_HANDLE_DESC_PHYSICAL 0x0 /* enum */
+#define	NET_PORT_HANDLE_DESC_VIRTUAL 0x1 /* enum */
+#define	NET_PORT_HANDLE_DESC_MPORT 0x2 /* enum */
+#define	NET_PORT_HANDLE_DESC_IS_ZOMBIE_OFST 4
+#define	NET_PORT_HANDLE_DESC_IS_ZOMBIE_LBN 8
+#define	NET_PORT_HANDLE_DESC_IS_ZOMBIE_WIDTH 1
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LBN 32
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_WIDTH 64
+/* The dynamic change that led to the port enumeration */
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_OFST 12
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_LEN 1
+/* enum: Indicates that the ENTRY_SRC field has not been initialized. */
+#define	NET_PORT_HANDLE_DESC_UNKNOWN 0x0
+/* enum: The port was enumerated at start of day. */
+#define	NET_PORT_HANDLE_DESC_PRESENT 0x1
+/* enum: The port was dynamically added. */
+#define	NET_PORT_HANDLE_DESC_ADDED 0x2
+/* enum: The port was dynamically deleted. */
+#define	NET_PORT_HANDLE_DESC_DELETED 0x3
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_LBN 96
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_WIDTH 8
+/* This is an opaque 40 byte label exposed to users as a unique identifier of
+ * the port. It is represented as a zero-terminated ASCII string and assigned
+ * by the port administrator which is typically either the firmware for a
+ * physical port or the host software responsible for creating the virtual
+ * port. The label is conveyed to the driver after assignment, which, unlike
+ * the port administrator, does not need to know how to interpret the label.
+ */
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_OFST 13
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_LEN 40
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_LBN 104
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_WIDTH 320
+
+
+/***********************************/
+/* MC_CMD_ENUM_PORTS
+ * This command returns handles for all ports present in the system. The PCIe
+ * function type of each port (either physical or virtual) is also reported.
+ * After a start-of-day port enumeration, firmware keeps track of all available
+ * ports upon creation or deletion and updates the ports if there is a change.
+ * This command is cleared after a control interface reset (e.g. FLR,
+ * ENTITY_RESET), in which case it must be called again to reenumerate the
+ * ports. The command is also clear-on-read and repeated calls will drain the
+ * buffer.
+ */
+#define	MC_CMD_ENUM_PORTS 0x1e5
+#define	MC_CMD_ENUM_PORTS_MSGSET 0x1e5
+#undef	MC_CMD_0x1e5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e5_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_ENUM_PORTS_IN msgrequest */
+#define	MC_CMD_ENUM_PORTS_IN_LEN 0
+
+/* MC_CMD_ENUM_PORTS_OUT msgresponse */
+#define	MC_CMD_ENUM_PORTS_OUT_LENMIN 12
+#define	MC_CMD_ENUM_PORTS_OUT_LENMAX 252
+#define	MC_CMD_ENUM_PORTS_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_ENUM_PORTS_OUT_LEN(num) (12+1*(num))
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_NUM(len) (((len)-12)/1)
+/* Any unused flags are reserved and must be ignored. */
+#define	MC_CMD_ENUM_PORTS_OUT_FLAGS_OFST 0
+#define	MC_CMD_ENUM_PORTS_OUT_FLAGS_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_MORE_OFST 0
+#define	MC_CMD_ENUM_PORTS_OUT_MORE_LBN 0
+#define	MC_CMD_ENUM_PORTS_OUT_MORE_WIDTH 1
+/* The number of NET_PORT_HANDLE_DESC structures in PORT_HANDLES. */
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_OFST 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_OFST 8
+#define	MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_LEN 4
+/* Array of NET_PORT_HANDLE_DESC structures. Callers must use must use the
+ * SIZEOF_NET_PORT_HANDLE_DESC field field as the array stride between entries.
+ * This may also allow for tail padding for alignment. Fields beyond
+ * SIZEOF_NET_PORT_HANDLE_DESC are not present.
+ */
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_OFST 12
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_LEN 1
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MINNUM 0
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM 240
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM_MCDI2 1008
+/* See structuredef: NET_PORT_HANDLE_DESC */
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_OFST 12
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_OFST 16
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LEN 8
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_OFST 16
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LBN 128
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_WIDTH 32
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_OFST 20
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LBN 160
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_WIDTH 32
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_LBN 128
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_WIDTH 3
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_LBN 136
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_WIDTH 1
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_OFST 24
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_LEN 1
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_OFST 25
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_LEN 40
+
+
+/***********************************/
+/* MC_CMD_GET_TRANSCEIVER_PROPERTIES
+ * Read properties of the transceiver associated with the port. Can be either
+ * for a fixed onboard transceiver or an inserted module. The returned data is
+ * interpreted from the transceiver hardware and may be fixed up by the
+ * firmware. Use MC_CMD_GET_MODULE_DATA to get raw undecoded data.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES 0x1e6
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_MSGSET 0x1e6
+#undef	MC_CMD_0x1e6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e6_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN msgrequest */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_LEN 4
+/* Handle to port to get transceiver properties from. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT msgresponse */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LEN 89
+/* Supported technology abilities. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_OFST 0
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_LEN 16
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Reserved for future expansion to accommodate future Ethernet technology
+ * expansion.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_OFST 16
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_LEN 16
+/* Preferred FEC modes. This is a function of the cable type and length. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_OFST 32
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* SFF-8042 code reported by the module. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_OFST 36
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_LEN 2
+/* Medium. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_OFST 38
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_LEN 1
+/* enum property: value */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 /* enum */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_COPPER 0x1 /* enum */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_OPTICAL 0x2 /* enum */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BACKPLANE 0x3 /* enum */
+/* Identifies the tech */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_OFST 39
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_LEN 1
+/* enum property: value */
+/*               MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 */
+/* enum: Ethernet over twisted-pair copper cables for distances up to 100
+ * meters.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASET 0x1
+/* enum: Ethernet over twin-axial, balanced copper cable. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CR 0x2
+/* enum: Ethernet over backplane for connections on the same board. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KX 0x3
+/* enum: Ethernet over a single backplane lane for connections between
+ * different boards.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KR 0x4
+/* enum: Ethernet over copper backplane. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KP 0x5
+/* enum: Ethernet over fiber optic. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASEX 0x6
+/* enum: Short range ethernet over multimode fiber optic (See IEEE 802.3 Clause
+ * 49 and 52).
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SR 0x7
+/* enum: Long range, extended range or far reach ethernet used with single mode
+ * fiber optics.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LR_ER_FR 0x8
+/* enum: Long reach multimode ethernet over multimode optical fiber. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LRM 0x9
+/* enum: Very short reach PAM4 ethernet over multimode optical fiber (see IEEE
+ * 802.3db).
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VR 0xa
+/* enum: BASE-R encoding and PAM4 over single-mode fiber with reach up to at
+ * least 500 meters (803.2 Clause 121 and 124)
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_DR 0xb
+/* String of the vendor name as intepreted by NMC firmware. NMC firmware
+ * applies workarounds for known buggy transceivers. The vendor name is
+ * presented as 16 bytes of ASCII characters padded with spaces. It can also be
+ * represented as 16 bytes of zeros if the field is unspecified for the
+ * connected module. See SFF-8472/CMIS specifications for details.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_OFST 40
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_LEN 1
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_NUM 16
+/* The vendor part number as intepreted by NMC firmware. The field is presented
+ * as 16 bytes of ASCII chars padded with spaces. It can also be 16 bytes of
+ * zeros if the field is unspecified for the connected module.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_OFST 56
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_LEN 1
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_NUM 16
+/* Serial number of the module presented as 16 bytes of ASCII characters padded
+ * with spaces. It can also be 16 bytes of zeros if the field is unspecified
+ * for the connected module. See SFF-8472/CMIS specifications for details.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_OFST 72
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_LEN 1
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_NUM 16
+/* This reports the number of module changes detected by the NMC firmware. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 88
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+
+
+/***********************************/
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES 0x1e7
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_MSGSET 0x1e7
+#undef	MC_CMD_0x1e7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e7_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES_IN msgrequest: In this context, the port
+ * consists of the MAC and the PHY, and excludes any modules inserted into the
+ * cage. This information is fixed for a given board but not for a given ASIC.
+ * This command reports properties for the port as it is currently configured,
+ * and not its hardware capabilities, which can be better than the current
+ * configuration.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN 4
+/* Handle to the port to from which to retreive properties */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT msgresponse */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LEN 36
+/* Supported capabilities of the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_LEN 25
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_OFST 16
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_OFST 20
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_OFST 24
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_LEN 1
+/* Number of lanes supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_OFST 25
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_LEN 1
+/* Bitmask of supported loopback modes. Where the response to this command
+ * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in
+ * preference to ensure that all available loopback modes are seen.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_OFST 26
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* This field serves as a cage index that uniquely identifies the cage to which
+ * the module is connected. This is useful when splitter cables that have
+ * multiple ports on a single cage are used.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_OFST 27
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_LEN 1
+/* This bitmask is used to specify the lanes within the cage identified by
+ * MDI_INDEX that are allocated to the port.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_OFST 28
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_LEN 1
+/* Maximum frame length supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_OFST 32
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_LEN 4
+
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2 msgresponse */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN 48
+/* Supported capabilities of the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_LEN 25
+/* Number of lanes supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_OFST 25
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_LEN 1
+/* Bitmask of supported loopback modes. Where the response to this command
+ * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in
+ * preference to ensure that all available loopback modes are seen.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_OFST 26
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* This field serves as a cage index that uniquely identifies the cage to which
+ * the module is connected. This is useful when splitter cables that have
+ * multiple ports on a single cage are used.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_OFST 27
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_LEN 1
+/* This bitmask is used to specify the lanes within the cage identified by
+ * MDI_INDEX that are allocated to the port.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_OFST 28
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_LEN 1
+/* Maximum frame length supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_OFST 32
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_LEN 4
+/* Bitmask of supported loopback modes. This field replaces the
+ * LOOPBACK_MODES_MASK field which is defined under version 1 of this command.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_OFST 40
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LEN 8
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_OFST 40
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LBN 320
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_WIDTH 32
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_OFST 44
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LBN 352
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_WIDTH 32
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+
+
+/***********************************/
+/* MC_CMD_GET_MODULE_DATA
+ * Read media-specific data from the PHY (e.g. SFP/SFP+ module ID information
+ * for SFP+ PHYs). This command returns raw data from the module's EEPROM and
+ * it is not interpreted by the MC. Use MC_CMD_GET_TRANSCEIVER_PROPERTIES to
+ * get interpreted data. Return code: 0, ENOENT
+ */
+#define	MC_CMD_GET_MODULE_DATA 0x1e8
+#define	MC_CMD_GET_MODULE_DATA_MSGSET 0x1e8
+#undef	MC_CMD_0x1e8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e8_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_MODULE_DATA_IN msgrequest */
+#define	MC_CMD_GET_MODULE_DATA_IN_LEN 16
+/* Handle to identify the port from which to request module properties. */
+#define	MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_LEN 4
+/* 7 bit I2C address of the device. DEPRECATED: This field is replaced by
+ * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier
+ * access.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_DEVADDR_LBN 32
+#define	MC_CMD_GET_MODULE_DATA_IN_DEVADDR_WIDTH 7
+/* 0 if the page does not support banked access, non-zero otherwise. Non-zero
+ * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
+ * region.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_BANK_OFST 6
+#define	MC_CMD_GET_MODULE_DATA_IN_BANK_LEN 2
+/* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
+ * valid if OFFSET is in the range 80h - ffh.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_PAGE_OFST 8
+#define	MC_CMD_GET_MODULE_DATA_IN_PAGE_LEN 2
+/* Offset in the range 00h - 7fh to access lower memory. Offset in the range
+ * 80h - ffh to access upper memory
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_OFFSET_OFST 10
+#define	MC_CMD_GET_MODULE_DATA_IN_OFFSET_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_IN_LENGTH_OFST 12
+#define	MC_CMD_GET_MODULE_DATA_IN_LENGTH_LEN 4
+
+/* MC_CMD_GET_MODULE_DATA_IN_V2 msgrequest: Updated MC_CMD_GET_MODULE_DATA with
+ * 8-bit wide ADDRESSING field. This new field provides a correctly aligned
+ * container for the 7-bit DEVADDR field from V1, now renamed MODULE_ADDR, to
+ * ensure proper alignment.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_LEN 16
+/* Handle to identify the port from which to request module properties. */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_LEN 4
+/* 7 bit I2C address of the device. DEPRECATED: This field is replaced by
+ * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier
+ * access.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_LBN 32
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_WIDTH 7
+/* 0 if the page does not support banked access, non-zero otherwise. Non-zero
+ * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
+ * region.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_BANK_OFST 6
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_BANK_LEN 2
+/* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
+ * valid if OFFSET is in the range 80h - ffh.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_OFST 8
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_LEN 2
+/* Offset in the range 00h - 7fh to access lower memory. Offset in the range
+ * 80h - ffh to access upper memory
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_OFST 10
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_OFST 12
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_LEN 4
+/* Container for 7 bit I2C addresses. */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_OFST 4
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_OFST 4
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_LBN 0
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_WIDTH 7
+
+/* MC_CMD_GET_MODULE_DATA_OUT msgresponse */
+#define	MC_CMD_GET_MODULE_DATA_OUT_LENMIN 5
+#define	MC_CMD_GET_MODULE_DATA_OUT_LENMAX 252
+#define	MC_CMD_GET_MODULE_DATA_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_GET_MODULE_DATA_OUT_LEN(num) (4+1*(num))
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_NUM(len) (((len)-4)/1)
+/* length of the data in bytes */
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATALEN_OFST 0
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATALEN_LEN 4
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_OFST 4
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_MINNUM 1
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM 248
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM_MCDI2 1016
+
+/* EVENT_MASK structuredef */
+#define	EVENT_MASK_LEN 4
+#define	EVENT_MASK_TYPE_OFST 0
+#define	EVENT_MASK_TYPE_LEN 4
+/* enum: PORT_LINKCHANGE event is enabled */
+#define	EVENT_MASK_PORT_LINKCHANGE 0x0
+/* enum: PORT_MODULECHANGE event is enabled */
+#define	EVENT_MASK_PORT_MODULECHANGE 0x1
+#define	EVENT_MASK_TYPE_LBN 0
+#define	EVENT_MASK_TYPE_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_SET_NETPORT_EVENTS_MASK
+ */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK 0x1e9
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_MSGSET 0x1e9
+#undef	MC_CMD_0x1e9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e9_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_SET_NETPORT_EVENTS_MASK_IN msgrequest: Enable or disable delivery of
+ * specified network port events for a given port identified by PORT_HANDLE. At
+ * start of day, or after any control interface reset (FLR, ENTITY_RESET,
+ * etc.), all event delivery is disabled for all ports associated with the
+ * control interface.
+ */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN 8
+/* Handle to port to set event delivery mask. */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
+/* Bitmask of events to enable. Event delivery is enabled when corresponding
+ * bit is 1, disabled when 0.
+ */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_OFST 4
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               EVENT_MASK/TYPE */
+
+/* MC_CMD_SET_NETPORT_EVENTS_MASK_OUT msgresponse */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_NETPORT_EVENTS_MASK
+ */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK 0x1ea
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_MSGSET 0x1ea
+#undef	MC_CMD_0x1ea_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ea_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_NETPORT_EVENTS_MASK_IN msgrequest: Get event delivery mask a
+ * given port identified by PORT_HANDLE.
+ */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_IN_LEN 4
+/* Handle to port to get event deliver mask for. */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_GET_NETPORT_EVENTS_MASK_OUT msgresponse */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_LEN 4
+/* Bitmask of events enabled. Event delivery is enabled when corresponding bit
+ * is 1, disabled when 0.
+ */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_OFST 0
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               EVENT_MASK/TYPE */
+
+
+/***********************************/
+/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS
+ */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS 0x1eb
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_MSGSET 0x1eb
+#undef	MC_CMD_0x1eb_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1eb_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN msgrequest: Get network port events
+ * supported by the platform. Information returned is fixed for a given NIC
+ * platform.
+ */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN_LEN 0
+
+/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT msgresponse */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_LEN 4
+/* Bitmask of events enabled. Event delivery is enabled when corresponding bit
+ * is 1, disabled when 0.
+ */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_OFST 0
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               EVENT_MASK/TYPE */
+
+/* LINK_CHANGE_LOG structuredef */
+#define	LINK_CHANGE_LOG_LEN 16
+/* Bitmask of flags that describe the state of the link. */
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_OFST 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LEN 8
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_OFST 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_LEN 4
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_LBN 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_WIDTH 32
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_OFST 4
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_LEN 4
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_LBN 32
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LBN 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_WIDTH 64
+/* This is the time elapsed in milliseconds since the last event occurred. */
+#define	LINK_CHANGE_LOG_TIME_STAMP_OFST 8
+#define	LINK_CHANGE_LOG_TIME_STAMP_LEN 4
+#define	LINK_CHANGE_LOG_TIME_STAMP_LBN 64
+#define	LINK_CHANGE_LOG_TIME_STAMP_WIDTH 32
+/* Speed of the link. 0 if the link is down. */
+#define	LINK_CHANGE_LOG_LINK_SPEED_OFST 12
+#define	LINK_CHANGE_LOG_LINK_SPEED_LEN 4
+#define	LINK_CHANGE_LOG_LINK_SPEED_LBN 96
+#define	LINK_CHANGE_LOG_LINK_SPEED_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_LINK_LOG
+ * This command retrieves the history log of link state changes and reports the
+ * timestamp, reason for link state change and new link state. This command is
+ * clear-on-read.
+ */
+#define	MC_CMD_LINK_LOG 0x1ec
+#define	MC_CMD_LINK_LOG_MSGSET 0x1ec
+#undef	MC_CMD_0x1ec_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_LINK_LOG_IN msgrequest */
+#define	MC_CMD_LINK_LOG_IN_LEN 4
+/* A handle to identify the port on which to query the link log. */
+#define	MC_CMD_LINK_LOG_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_LINK_LOG_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_LINK_LOG_OUT msgresponse */
+#define	MC_CMD_LINK_LOG_OUT_LENMIN 8
+#define	MC_CMD_LINK_LOG_OUT_LENMAX 248
+#define	MC_CMD_LINK_LOG_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_LINK_LOG_OUT_LEN(num) (8+16*(num))
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_NUM(len) (((len)-8)/16)
+/* Number of valid transitions of type LINK_CHANGE_LOG structures in the
+ * LINK_LOG_ARRAY
+ */
+#define	MC_CMD_LINK_LOG_OUT_NUM_LOG_ENTRIES_OFST 0
+#define	MC_CMD_LINK_LOG_OUT_NUM_LOG_ENTRIES_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_MORE_OFST 0
+#define	MC_CMD_LINK_LOG_OUT_MORE_LBN 0
+#define	MC_CMD_LINK_LOG_OUT_MORE_WIDTH 1
+/* Contains additional flags or control information related to the log
+ * response. The specific bits, e.g. MORE_ENTRIES, are described below.
+ */
+#define	MC_CMD_LINK_LOG_OUT_FLAGS_OFST 4
+#define	MC_CMD_LINK_LOG_OUT_FLAGS_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_MORE_ENTRIES_OFST 4
+#define	MC_CMD_LINK_LOG_OUT_MORE_ENTRIES_LBN 0
+#define	MC_CMD_LINK_LOG_OUT_MORE_ENTRIES_WIDTH 1
+/* Array of LINK_CHANGE_LOG structures */
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_OFST 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_LEN 16
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_MINNUM 0
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_MAXNUM 15
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_MAXNUM_MCDI2 63
+/* See structuredef: LINK_CHANGE_LOG */
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_OFST 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_OFST 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_LBN 64
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_OFST 12
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_LBN 96
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_WIDTH 32
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_TIME_STAMP_OFST 16
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_TIME_STAMP_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_LINK_SPEED_OFST 20
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_LINK_SPEED_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CSR_INST_READ32
+ * Read 32bit words from an MCPU indirect memory map specified by its
+ * MAP_INDEX.
+ */
+#define	MC_CMD_CSR_INST_READ32 0x1ee
+#define	MC_CMD_CSR_INST_READ32_MSGSET 0x1ee
+#undef	MC_CMD_0x1ee_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ee_PRIVILEGE_CTG SRIOV_CTG_INSECURE
+
+/* MC_CMD_CSR_INST_READ32_IN msgrequest */
+#define	MC_CMD_CSR_INST_READ32_IN_LEN 24
+/* Address */
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_OFST 0
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LEN 8
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_OFST 0
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_LEN 4
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_LBN 0
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_WIDTH 32
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_OFST 4
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_LEN 4
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_LBN 32
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_WIDTH 32
+/* Step value between register addresses */
+#define	MC_CMD_CSR_INST_READ32_IN_STEP_OFST 8
+#define	MC_CMD_CSR_INST_READ32_IN_STEP_LEN 4
+/* Map index of indirect memory map */
+#define	MC_CMD_CSR_INST_READ32_IN_MAP_INDEX_OFST 12
+#define	MC_CMD_CSR_INST_READ32_IN_MAP_INDEX_LEN 4
+/* Number of words to read */
+#define	MC_CMD_CSR_INST_READ32_IN_NUM_WORDS_OFST 20
+#define	MC_CMD_CSR_INST_READ32_IN_NUM_WORDS_LEN 4
+
+/* MC_CMD_CSR_INST_READ32_OUT msgresponse */
+#define	MC_CMD_CSR_INST_READ32_OUT_LENMIN 4
+#define	MC_CMD_CSR_INST_READ32_OUT_LENMAX 252
+#define	MC_CMD_CSR_INST_READ32_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_CSR_INST_READ32_OUT_LEN(num) (4+4*(num))
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_NUM(len) (((len)-4)/4)
+/* Status response from register reads by firmware */
+#define	MC_CMD_CSR_INST_READ32_OUT_STATUS_OFST 0
+#define	MC_CMD_CSR_INST_READ32_OUT_STATUS_LEN 4
+/* Read data */
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_OFST 4
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_LEN 4
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_MINNUM 0
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_MAXNUM 62
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_MAXNUM_MCDI2 254
+
+
+/***********************************/
+/* MC_CMD_CSR_INST_WRITE32
+ * Write 32bit dwords to an MCPU indirect memory map specified by its
+ * MAP_INDEX.
+ */
+#define	MC_CMD_CSR_INST_WRITE32 0x1ef
+#define	MC_CMD_CSR_INST_WRITE32_MSGSET 0x1ef
+#undef	MC_CMD_0x1ef_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ef_PRIVILEGE_CTG SRIOV_CTG_INSECURE
+
+/* MC_CMD_CSR_INST_WRITE32_IN msgrequest */
+#define	MC_CMD_CSR_INST_WRITE32_IN_LENMIN 24
+#define	MC_CMD_CSR_INST_WRITE32_IN_LENMAX 252
+#define	MC_CMD_CSR_INST_WRITE32_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_CSR_INST_WRITE32_IN_LEN(num) (20+4*(num))
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_NUM(len) (((len)-20)/4)
+/* Address */
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_OFST 0
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LEN 8
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_OFST 0
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_LEN 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_LBN 0
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_WIDTH 32
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_OFST 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_LEN 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_LBN 32
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_WIDTH 32
+/* Step value between register addresses */
+#define	MC_CMD_CSR_INST_WRITE32_IN_STEP_OFST 8
+#define	MC_CMD_CSR_INST_WRITE32_IN_STEP_LEN 4
+/* Map index of indirect memory map */
+#define	MC_CMD_CSR_INST_WRITE32_IN_MAP_INDEX_OFST 12
+#define	MC_CMD_CSR_INST_WRITE32_IN_MAP_INDEX_LEN 4
+/* Write data */
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_OFST 20
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_LEN 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_MINNUM 1
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_MAXNUM 58
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_MAXNUM_MCDI2 250
+
+/* MC_CMD_CSR_INST_WRITE32_OUT msgresponse */
+#define	MC_CMD_CSR_INST_WRITE32_OUT_LEN 4
+/* Status response from register writes by firmware */
+#define	MC_CMD_CSR_INST_WRITE32_OUT_STATUS_OFST 0
+#define	MC_CMD_CSR_INST_WRITE32_OUT_STATUS_LEN 4
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_CONFIG
+ * Query the static HNIC port configuration for a physical port. Returns ENODEV
+ * if the target does not correspond to a physical port, or EPERM if the caller
+ * does not have permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG 0x1f0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_MSGSET 0x1f0
+#undef	MC_CMD_0x1f0_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_CONFIG_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LENMIN 12
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LENMAX 252
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LEN(num) (12+4*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_NUM(len) (((len)-12)/4)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_REGION_SIZE_LEN 4
+/* Allocation granularity, in bytes. All partitioning of the buffer region must
+ * be in multiples of this value.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_LEN 4
+/* Array of FIFO handles, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_OFST 12
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MINNUM 0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM 60
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM_MCDI2 252
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING
+ * Returns the current state of the FIFO sizing configuration for all of the
+ * FIFOs assigned to a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING 0x1f1
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_MSGSET 0x1f1
+#undef	MC_CMD_0x1f1_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LENMIN 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LENMAX 248
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LEN(num) (8+12*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_NUM(len) (((len)-8)/12)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM 20
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 84
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING
+ * Sets the FIFO sizing configuration for a physical port. This is disruptive
+ * to port operation and will cause the link to drop while the port is
+ * reconfigured. Returns ENODEV if the target does not correspond to a physical
+ * port, or EPERM if the caller does not have permission to administer it, or
+ * EINVAL if the sizing parameters are invalid.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING 0x1f2
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_MSGSET 0x1f2
+#undef	MC_CMD_0x1f2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LENMIN 12
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LENMAX 252
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LEN(num) (12+12*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_NUM(len) (((len)-12)/12)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current size configuration.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_OFST 12
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM 20
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 84
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING
+ * Returns the current state of the 802.1Q priority to FIFO mapping
+ * configuration for a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING 0x1f3
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1f3
+#undef	MC_CMD_0x1f3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_LEN 32
+/* FIFO handle for each Priority Code Point(PCP), in order from 0 to 7. */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_NUM 8
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING
+ * Sets the PCP priority to FIFO mapping configuration for a physical port.
+ * Returns ENODEV if the target does not correspond to a physical port, or
+ * EPERM if the caller does not have permission to administer it, or EINVAL if
+ * any of the FIFO handles are invalid in some way.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING 0x1f4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1f4
+#undef	MC_CMD_0x1f4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_LEN 40
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* FIFO handle for each PCP value, in order from 0 to 7. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_LEN 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_NUM 8
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Returns the current state of the FIFO delay parameters configuration for all
+ * of the FIFOs assigned to a physical port. Returns ENODEV if the target does
+ * not correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS 0x1f5
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1f5
+#undef	MC_CMD_0x1f5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMIN 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX 244
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX_MCDI2 1012
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN(num) (4+16*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_NUM(len) (((len)-4)/16)
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM 15
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 63
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Sets the FIFO delay parameters configuration for a physical port. This is
+ * not disruptive to port operation. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it, or EINVAL if the sizing parameters are invalid.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS 0x1f6
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1f6
+#undef	MC_CMD_0x1f6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMIN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX 240
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX_MCDI2 1008
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN(num) (16+16*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_NUM(len) (((len)-16)/16)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current delay
+ * configuration.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM 14
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 62
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN 0
+
+/* HNIC_FIFO_DRAIN structuredef: HNIC FIFO drain parameters */
+#define	HNIC_FIFO_DRAIN_LEN 8
+/* Handle to identify the fifo to be drained. The FIFO_HANDLE should be treated
+ * as an opaque value.
+ */
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_WIDTH 32
+#define	HNIC_FIFO_DRAIN_FLAGS_OFST 4
+#define	HNIC_FIFO_DRAIN_FLAGS_LEN 4
+#define	HNIC_FIFO_DRAIN_DRAIN_EN_OFST 4
+#define	HNIC_FIFO_DRAIN_DRAIN_EN_LBN 0
+#define	HNIC_FIFO_DRAIN_DRAIN_EN_WIDTH 1
+#define	HNIC_FIFO_DRAIN_FLAGS_LBN 32
+#define	HNIC_FIFO_DRAIN_FLAGS_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN
+ * This command configures an HNIC TX FIFO to be flushed for a physical port.
+ * This is not disruptive to port operation. Returns ENODEV if the target does
+ * not correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it. or ENOTSUP if the requested direction is RX.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN 0x1f7
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_MSGSET 0x1f7
+#undef	MC_CMD_0x1f7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LENMIN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LENMAX 240
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LENMAX_MCDI2 1008
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LEN(num) (16+16*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_NUM(len) (((len)-16)/16)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. Flushing fifos is only allowed in the TX
+ * direction.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured for flushing. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DRAIN structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_LEN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_MINNUM 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_MAXNUM 14
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_MAXNUM_MCDI2 62
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_OUT_LEN 0
+
+/* HNIC_FIFO_WEIGHT structuredef: HNIC FIFO weights used in the scheduler's
+ * round robin algorithm.
+ */
+#define	HNIC_FIFO_WEIGHT_LEN 8
+/* FIFO handle */
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_WIDTH 32
+/* Weight value expressed in units of 0.001 (i.e. value 1000 corresponds to a
+ * weight=1). Allowed values for this field are [1000-4000]
+ */
+#define	HNIC_FIFO_WEIGHT_WEIGHT_OFST 4
+#define	HNIC_FIFO_WEIGHT_WEIGHT_LEN 4
+#define	HNIC_FIFO_WEIGHT_WEIGHT_LBN 32
+#define	HNIC_FIFO_WEIGHT_WEIGHT_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS
+ * Retrieves the FIFO weights for the scheduler's round robin algorithm.
+ * Returns ENODEV if the target does not correspond to a physical port, or
+ * EPERM if the caller does not have permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS 0x1f8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_MSGSET 0x1f8
+#undef	MC_CMD_0x1f8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to operate on. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LENMIN 16
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LENMAX 248
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LEN(num) (8+8*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_NUM(len) (((len)-8)/8)
+/* Total number of configured FIFOs. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_NUM_FIFOS_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_WEIGHT structures, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LEN 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_LBN 64
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_WIDTH 32
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_OFST 12
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_LBN 96
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_WIDTH 32
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_MINNUM 1
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_MAXNUM 30
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_MAXNUM_MCDI2 126
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS
+ * Configures the FIFO weights for the scheduler's round robin algorithm. This
+ * is not disruptive to port operation. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it or EINVAL if provided argument are not valid.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS 0x1f9
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_MSGSET 0x1f9
+#undef	MC_CMD_0x1f9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LENMIN 24
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LENMAX 248
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LENMAX_MCDI2 1016
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LEN(num) (16+8*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_NUM(len) (((len)-16)/8)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to operate on. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. At least one FIFO needs to be
+ * specified.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_WEIGHT structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LEN 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_LEN 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_LBN 128
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_WIDTH 32
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_OFST 20
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_LEN 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_LBN 160
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_WIDTH 32
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_MINNUM 1
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_MAXNUM 29
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_MAXNUM_MCDI2 125
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_NETPORT_STATISTICS
+ * Get generic MAC statistics. This call retrieves unified statistics managed
+ * by the MC. The MC will populate and provide all supported statistics in the
+ * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the
+ * aforementioned command for the format and contents of the stats DMA buffer.
+ * To ensure consistent and accurate results, it is essential for the driver to
+ * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
+ * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
+ * handle, and EINVAL on invalid parameters (DMA buffer too small)
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS 0x1fa
+#define	MC_CMD_GET_NETPORT_STATISTICS_MSGSET 0x1fa
+#undef	MC_CMD_0x1fa_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1fa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_NETPORT_STATISTICS_IN msgrequest */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_LEN 20
+/* Handle of port to get MAC statistics for. */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_LEN 4
+/* Contains options for querying the MAC statistics. */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LBN 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_LBN 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_LBN 2
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_LBN 3
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_LBN 15
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_WIDTH 17
+/* Specifies the physical address of the DMA buffer to use for statistics
+ * transfer. This field must contain a valid address under either of these
+ * conditions: 1. DMA flag is set (immediate DMA requested) 2. Both
+ * PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured)
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_OFST 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LEN 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_OFST 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LBN 64
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_OFST 12
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LBN 96
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32
+/* Specifies the length of the DMA buffer in bytes for statistics transfer. The
+ * buffer size must be at least DMA_BUFFER_SIZE bytes (as returned by
+ * MC_CMD_MAC_STATISTICS_DESCRIPTOR). Providing an insufficient buffer size
+ * will result in an EINVAL error. This field must contain a valid length under
+ * either of these conditions: 1. DMA flag is set (immediate DMA requested) 2.
+ * Both PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured)
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_OFST 16
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_LEN 4
+
+/* MC_CMD_GET_NETPORT_STATISTICS_OUT msgresponse */
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX 248
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LEN(num) (0+8*(num))
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_NUM(len) (((len)-0)/8)
+/* Statistics buffer. Zero-length if DMA mode is used. The statistics buffer is
+ * an array of 8-byte counter values, containing the generation start marker,
+ * stats counters, and generation end marker. The index of each counter in the
+ * array is reported by the MAC_STATISTICS_DESCRIPTOR command. The same layout
+ * is used for the DMA buffer for DMA mode stats.
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_OFST 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LEN 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_OFST 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LBN 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_WIDTH 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LBN 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_WIDTH 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MINNUM 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM 31
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM_MCDI2 127
+
 /* EVB_PORT_ID structuredef */
 #define	EVB_PORT_ID_LEN 4
 #define	EVB_PORT_ID_PORT_ID_OFST 0
@@ -11820,6 +15458,9 @@
 #define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
@@ -11926,6 +15567,9 @@
 #define	MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
@@ -12061,6 +15705,9 @@
 #define	MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
@@ -12209,6 +15856,9 @@
 #define	MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
@@ -13828,6 +17478,10 @@
 #define	MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
 /* enum: read the supported encapsulation types for the VNIC */
 #define	MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
+/* enum: read the supported RX filter matches for low-latency queues (as
+ * allocated by MC_CMD_ALLOC_LL_QUEUES)
+ */
+#define	MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_LL_RX_MATCHES 0x7
 
 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
 #define	MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
@@ -14554,7 +18208,7 @@
 
 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
-/* VI number to get information for. */
+/* Queue handle, encodes queue type and VI number to get information for. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
 #define	MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
 
@@ -14569,6 +18223,12 @@
 /* Use Relaxed ordering model for TLPs on this VI. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
+/* Use Relaxed ordering model for packet data transfer TLPs on this VI (alias
+ * of RELAXED_ORDERING for hardware that also understands the
+ * RELAXED_ORDERING_SYNC_DATA field and allows them to be used independently).
+ */
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_PACKET_DATA_LBN 16
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
 /* Use ID based ordering for TLPs on this VI. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
@@ -14578,15 +18238,56 @@
 /* Enable TPH for TLPs on this VI. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
+/* Use Relaxed ordering model for synchronization data transfer TLPs on this
+ * VI, used for relaxed ordering of metadata transfers on LL.
+ */
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_SYNC_DATA_LBN 20
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
 
+/* MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT msgresponse: This message has the same
+ * layout as GET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to
+ * simplify use in drivers
+ */
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_LEN 4
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_LEN 4
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_LBN 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_WIDTH 8
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_LBN 8
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_WIDTH 8
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_LBN 16
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_LBN 16
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_LBN 17
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_LBN 18
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_LBN 19
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_LBN 20
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
+
 
 /***********************************/
 /* MC_CMD_SET_VI_TLP_PROCESSING
  * Set TLP steering and ordering information for a VI. The caller must have the
  * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
- * an ancestor of the current user (see MC_CMD_SET_VI_USER).
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER). Note that LL
+ * queues require this to be called after allocation but before initialisation
+ * of the queue. TLP options of a queue are fixed after queue is initialised,
+ * with the values set to current global value or they can be overriden using
+ * this command. At LL queue allocation, all overrides are cleared.
  */
 #define	MC_CMD_SET_VI_TLP_PROCESSING 0xb1
 #define	MC_CMD_SET_VI_TLP_PROCESSING_MSGSET 0xb1
@@ -14596,7 +18297,7 @@
 
 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
-/* VI number to set information for. */
+/* Queue handle, encodes queue type and VI number to set information for. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
 /* Transaction processing steering hint 1 for use with the Rx Queue. */
@@ -14608,6 +18309,12 @@
 /* Use Relaxed ordering model for TLPs on this VI. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
+/* Use Relaxed ordering model for packet data transfer TLPs on this VI (alias
+ * of RELAXED_ORDERING for hardware that also understands the
+ * RELAXED_ORDERING_SYNC_DATA field and allows them to be used independently).
+ */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_PACKET_DATA_LBN 48
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
 /* Use ID based ordering for TLPs on this VI. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
@@ -14617,9 +18324,49 @@
 /* Enable TPH for TLPs on this VI. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
+/* Use Relaxed ordering model for synchronization data transfer TLPs on this
+ * VI, used for relaxed ordering of metadata transfers on LL.
+ */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_SYNC_DATA_LBN 52
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
 
+/* MC_CMD_SET_VI_TLP_PROCESSING_V2_IN msgrequest: This message has the same
+ * layout as SET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to
+ * simplify use in drivers.
+ */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_LEN 8
+/* Queue handle, encodes queue type and VI number to set information for. */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_OFST 0
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_LEN 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_LEN 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_LBN 0
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_WIDTH 8
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_LBN 8
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_WIDTH 8
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_LBN 16
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_LBN 16
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_LBN 17
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_LBN 18
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_LBN 19
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_LBN 20
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
+
 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
 
@@ -14640,12 +18387,16 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
 /* enum: MISC. */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
-/* enum: IDO. */
+/* enum: ID-based Ordering (IDO). */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
-/* enum: RO. */
+/* enum: Relaxed Ordering (RO), excluding LL queues. */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
-/* enum: TPH Type. */
+/* enum: TLP Processing Hint (TPH) Type (excluding LL queues). */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
+/* enum: Relaxed Ordering (RO) of LL queues. */
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LL_RO 0x4
+/* enum: TPH Type of LL queues. */
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LL_TPH_TYPE 0x5
 
 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
@@ -14659,9 +18410,6 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
@@ -14674,9 +18422,6 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
@@ -14686,9 +18431,6 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
@@ -14704,9 +18446,18 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_RXDMA_EN_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_RXDMA_EN_LBN 0
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_RXDMA_EN_WIDTH 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_PACKET_RXDMA_EN_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_PACKET_RXDMA_EN_LBN 0
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_PACKET_RXDMA_EN_WIDTH 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_META_RXDMA_EN_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_META_RXDMA_EN_LBN 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_META_RXDMA_EN_WIDTH 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_TPH_TYPE_RX_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_TPH_TYPE_RX_LBN 0
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_TPH_TYPE_RX_WIDTH 2
 
 
 /***********************************/
@@ -14767,9 +18518,18 @@
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
-#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
-#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
-#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_RXDMA_EN_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_RXDMA_EN_LBN 0
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_RXDMA_EN_WIDTH 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_PACKET_RXDMA_EN_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_PACKET_RXDMA_EN_LBN 0
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_PACKET_RXDMA_EN_WIDTH 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_META_RXDMA_EN_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_META_RXDMA_EN_LBN 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_META_RXDMA_EN_WIDTH 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_TPH_TYPE_RX_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_TPH_TYPE_RX_LBN 0
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_TPH_TYPE_RX_WIDTH 2
 
 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
@@ -15557,7 +19317,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -15967,7 +19730,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -16402,7 +20168,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -16845,7 +20614,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -17293,7 +21065,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -17752,7 +21527,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -17872,6 +21650,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 
 /* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
@@ -18262,7 +22046,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -18382,6 +22169,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 /* These bits are reserved for communicating test-specific capabilities to
  * host-side test software. All production drivers should treat this field as
  * opaque.
@@ -18786,7 +22579,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -18906,6 +22702,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 /* These bits are reserved for communicating test-specific capabilities to
  * host-side test software. All production drivers should treat this field as
  * opaque.
@@ -19345,7 +23147,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -19465,6 +23270,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 /* These bits are reserved for communicating test-specific capabilities to
  * host-side test software. All production drivers should treat this field as
  * opaque.
@@ -19529,6 +23340,1182 @@
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
 
+/* MC_CMD_GET_CAPABILITIES_V11_OUT msgresponse */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LEN 196
+/* First word of flags. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_WIDTH 1
+/* RxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_OFST 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_LEN 2
+/* enum: Standard RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP 0x0
+/* enum: Low latency RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_LOW_LATENCY 0x1
+/* enum: Packed stream RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_PACKED_STREAM 0x2
+/* enum: Rules engine RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_RULES_ENGINE 0x5
+/* enum: DPDK RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_DPDK 0x6
+/* enum: BIST RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_BIST 0x10a
+/* enum: RXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
+/* enum: RXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
+/* enum: RXDP Test firmware image 3 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
+/* enum: RXDP Test firmware image 4 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
+/* enum: RXDP Test firmware image 5 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_BACKPRESSURE 0x105
+/* enum: RXDP Test firmware image 6 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
+/* enum: RXDP Test firmware image 7 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
+/* enum: RXDP Test firmware image 8 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
+/* enum: RXDP Test firmware image 9 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
+/* enum: RXDP Test firmware image 10 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_SLOW 0x10c
+/* TxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_OFST 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_LEN 2
+/* enum: Standard TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP 0x0
+/* enum: Low latency TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_LOW_LATENCY 0x1
+/* enum: High packet rate TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_HIGH_PACKET_RATE 0x3
+/* enum: Rules engine TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_RULES_ENGINE 0x5
+/* enum: DPDK TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_DPDK 0x6
+/* enum: BIST TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_BIST 0x12d
+/* enum: TXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
+/* enum: TXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
+/* enum: TXDP CSR bus test firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_CSR 0x103
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+/* enum: Low latency RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
+/* enum: Packed stream RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
+ * encapsulations (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* Hardware capabilities of NIC */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_OFST 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_LEN 4
+/* Licensed capabilities */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_OFST 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_LEN 4
+/* Second word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
+/* One byte per PF containing the number of the external port assigned to this
+ * PF, indexed by PF number. Special values indicate that a PF is either not
+ * present or not assigned.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff
+/* enum: PF does not exist. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe
+/* enum: PF does exist but is not assigned to any external port. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_ASSIGNED 0xfd
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
+ * in this field. It is intended for a possible future situation where a more
+ * complex scheme of PFs to ports mapping is being used. The future driver
+ * should look for a new field supporting the new scheme. The current/old
+ * driver should treat this value as PF_NOT_ASSIGNED.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
+ * special value indicates that a PF is not present.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_OFST 42
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+/*               MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff */
+/* enum: PF does not exist. */
+/*               MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_OFST 58
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_NUM 4
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_OFST 66
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_LEN 1
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_OFST 67
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_LEN 1
+/* Total number of available PIO buffers */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_OFST 68
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_LEN 2
+/* Size of a single PIO buffer */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_OFST 70
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_LEN 2
+/* On chips later than Medford the amount of address space assigned to each VI
+ * is configurable. This is a global setting that the driver must query to
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
+ * with 8k VI windows.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_OFST 72
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_LEN 1
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
+ * CTPIO is not mapped.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_8K 0x0
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_16K 0x1
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_64K 0x2
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
+/* Entry count in the MAC stats array, including the final GENERATION_END
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
+ * hold at least this many 64-bit stats values, if they wish to receive all
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
+ * stats array returned will be truncated.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_OFST 76
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_LEN 2
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_OFST 80
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_LEN 4
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
+ * they create an RX queue. Due to hardware limitations, only a small number of
+ * different buffer sizes may be available concurrently. Nonzero entries in
+ * this array are the sizes of buffers which the system guarantees will be
+ * available for use. If the list is empty, there are no limitations on
+ * concurrent buffer sizes.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
+/* Third word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_WIDTH 1
+/* These bits are reserved for communicating test-specific capabilities to
+ * host-side test software. All production drivers should treat this field as
+ * opaque.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LEN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LBN 1216
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_WIDTH 32
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_OFST 156
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LBN 1248
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_WIDTH 32
+/* The minimum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum number of queues that can be used by an RSS context in exclusive
+ * mode. In exclusive mode the context has a configurable indirection table and
+ * a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
+/* The maximum number of queues that can be used by an RSS context in even-
+ * spreading mode. In even-spreading mode the context has no indirection table
+ * but it does have a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
+/* The total number of RSS contexts supported. Note that the number of
+ * available contexts using indirection tables is also limited by the
+ * availability of indirection table space allocated from a common pool.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_OFST 176
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_LEN 4
+/* The total amount of indirection table space that can be shared between RSS
+ * contexts.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_OFST 180
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_LEN 4
+/* A bitmap of the queue sizes the device can provide, where bit N being set
+ * indicates that 2**N is a valid size. The device may be limited in the number
+ * of different queue sizes that can exist simultaneously, so a bit being set
+ * here does not guarantee that an attempt to create a queue of that size will
+ * succeed.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
+/* A bitmap of queue sizes that are always available, in the same format as
+ * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
+ * will never fail due to unavailability of the requested size.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
+/* Number of available indirect memory maps. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
+
+/* MC_CMD_GET_CAPABILITIES_V12_OUT msgresponse */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LEN 204
+/* First word of flags. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_WIDTH 1
+/* RxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_OFST 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_LEN 2
+/* enum: Standard RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP 0x0
+/* enum: Low latency RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_LOW_LATENCY 0x1
+/* enum: Packed stream RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_PACKED_STREAM 0x2
+/* enum: Rules engine RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_RULES_ENGINE 0x5
+/* enum: DPDK RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_DPDK 0x6
+/* enum: BIST RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_BIST 0x10a
+/* enum: RXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
+/* enum: RXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
+/* enum: RXDP Test firmware image 3 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
+/* enum: RXDP Test firmware image 4 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
+/* enum: RXDP Test firmware image 5 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_BACKPRESSURE 0x105
+/* enum: RXDP Test firmware image 6 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
+/* enum: RXDP Test firmware image 7 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
+/* enum: RXDP Test firmware image 8 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
+/* enum: RXDP Test firmware image 9 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
+/* enum: RXDP Test firmware image 10 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_SLOW 0x10c
+/* TxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_OFST 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_LEN 2
+/* enum: Standard TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP 0x0
+/* enum: Low latency TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_LOW_LATENCY 0x1
+/* enum: High packet rate TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_HIGH_PACKET_RATE 0x3
+/* enum: Rules engine TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_RULES_ENGINE 0x5
+/* enum: DPDK TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_DPDK 0x6
+/* enum: BIST TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_BIST 0x12d
+/* enum: TXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
+/* enum: TXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
+/* enum: TXDP CSR bus test firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_CSR 0x103
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+/* enum: Low latency RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
+/* enum: Packed stream RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
+ * encapsulations (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* Hardware capabilities of NIC */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_OFST 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_LEN 4
+/* Licensed capabilities */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_OFST 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_LEN 4
+/* Second word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
+/* One byte per PF containing the number of the external port assigned to this
+ * PF, indexed by PF number. Special values indicate that a PF is either not
+ * present or not assigned.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff
+/* enum: PF does not exist. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe
+/* enum: PF does exist but is not assigned to any external port. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_ASSIGNED 0xfd
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
+ * in this field. It is intended for a possible future situation where a more
+ * complex scheme of PFs to ports mapping is being used. The future driver
+ * should look for a new field supporting the new scheme. The current/old
+ * driver should treat this value as PF_NOT_ASSIGNED.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
+ * special value indicates that a PF is not present.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_OFST 42
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+/*               MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff */
+/* enum: PF does not exist. */
+/*               MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_OFST 58
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_NUM 4
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_OFST 66
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_LEN 1
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_OFST 67
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_LEN 1
+/* Total number of available PIO buffers */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_OFST 68
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_LEN 2
+/* Size of a single PIO buffer */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_OFST 70
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_LEN 2
+/* On chips later than Medford the amount of address space assigned to each VI
+ * is configurable. This is a global setting that the driver must query to
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
+ * with 8k VI windows.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_OFST 72
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_LEN 1
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
+ * CTPIO is not mapped.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_8K 0x0
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_16K 0x1
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_64K 0x2
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
+/* Entry count in the MAC stats array, including the final GENERATION_END
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
+ * hold at least this many 64-bit stats values, if they wish to receive all
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
+ * stats array returned will be truncated.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_OFST 76
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_LEN 2
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_OFST 80
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_LEN 4
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
+ * they create an RX queue. Due to hardware limitations, only a small number of
+ * different buffer sizes may be available concurrently. Nonzero entries in
+ * this array are the sizes of buffers which the system guarantees will be
+ * available for use. If the list is empty, there are no limitations on
+ * concurrent buffer sizes.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
+/* Third word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_WIDTH 1
+/* These bits are reserved for communicating test-specific capabilities to
+ * host-side test software. All production drivers should treat this field as
+ * opaque.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LEN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LBN 1216
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_WIDTH 32
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_OFST 156
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LBN 1248
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_WIDTH 32
+/* The minimum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum number of queues that can be used by an RSS context in exclusive
+ * mode. In exclusive mode the context has a configurable indirection table and
+ * a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
+/* The maximum number of queues that can be used by an RSS context in even-
+ * spreading mode. In even-spreading mode the context has no indirection table
+ * but it does have a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
+/* The total number of RSS contexts supported. Note that the number of
+ * available contexts using indirection tables is also limited by the
+ * availability of indirection table space allocated from a common pool.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_OFST 176
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_LEN 4
+/* The total amount of indirection table space that can be shared between RSS
+ * contexts.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_OFST 180
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_LEN 4
+/* A bitmap of the queue sizes the device can provide, where bit N being set
+ * indicates that 2**N is a valid size. The device may be limited in the number
+ * of different queue sizes that can exist simultaneously, so a bit being set
+ * here does not guarantee that an attempt to create a queue of that size will
+ * succeed.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
+/* A bitmap of queue sizes that are always available, in the same format as
+ * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
+ * will never fail due to unavailability of the requested size.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
+/* Number of available indirect memory maps. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
+/* Number of VIs available for external ports 4-7. Information for ports 0-3 is
+ * in NUM_VIS_PER_PORT in GET_CAPABILITIES_V2_OUT.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_OFST 196
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_NUM 4
+
 
 /***********************************/
 /* MC_CMD_V2_EXTN
@@ -30722,7 +35709,8 @@
  * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
  * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
  * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
- * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
+ * VF on the calling interface - INTF=..., PF=PF_NULL, VF=VF_NULL to refer to
+ * the named interface itself - INTF=..., PF=..., VF=VF_NULL to refer to a PF
  * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
  * interface where ... refers to a small integer for the VF/PF fields, and to
  * values from the PCIE_INTERFACE enum for for the INTF field. It's only
@@ -33920,6 +38908,633 @@
 #define	MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
 #define	MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
 
+
+/***********************************/
+/* MC_CMD_PR_OPEN
+ * Open a session to manage a programmable region. Session handles can be
+ * explicitly closed with MC_CMD_PR_CLOSE, or implicitly via
+ * MC_CMD_ENTITY_RESET or a PCIe Function Level Reset. Although this command is
+ * available to all callers that are a member of the GENERAL privilege group,
+ * an additional privilege check may be performed against the target region.
+ * Returns ENODEV if the region doesn't exist; EPERM if the caller has
+ * insufficient privilege to open the region; EBUSY is the region is currently
+ * busy; ENOSPC if the caller has too many open programmable region sessions.
+ */
+#define	MC_CMD_PR_OPEN 0x1a2
+#define	MC_CMD_PR_OPEN_MSGSET 0x1a2
+#undef	MC_CMD_0x1a2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_OPEN_IN msgrequest */
+#define	MC_CMD_PR_OPEN_IN_LEN 4
+/* The programmable region to open. */
+#define	MC_CMD_PR_OPEN_IN_REGION_ID_OFST 0
+#define	MC_CMD_PR_OPEN_IN_REGION_ID_LEN 4
+
+/* MC_CMD_PR_OPEN_OUT msgresponse */
+#define	MC_CMD_PR_OPEN_OUT_LEN 4
+/* Session handle for operations on the contents of the programmable region.
+ * Handles should be considered opaque, although a value of 0xFFFFFFFF is
+ * guaranteed never to be a valid handle.
+ */
+#define	MC_CMD_PR_OPEN_OUT_HANDLE_OFST 0
+#define	MC_CMD_PR_OPEN_OUT_HANDLE_LEN 4
+/* enum: Invalid programmable region session handle */
+#define	MC_CMD_PR_OPEN_OUT_HANDLE_NULL 0xffffffff
+
+
+/***********************************/
+/* MC_CMD_PR_CLOSE
+ * Close a session created with MC_CMD_PR_OPEN. Returns ENOENT if the session
+ * handle doesn't exist.
+ */
+#define	MC_CMD_PR_CLOSE 0x1a3
+#define	MC_CMD_PR_CLOSE_MSGSET 0x1a3
+#undef	MC_CMD_0x1a3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_CLOSE_IN msgrequest */
+#define	MC_CMD_PR_CLOSE_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CLOSE_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_CLOSE_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CLOSE_OUT msgresponse */
+#define	MC_CMD_PR_CLOSE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_TRANSFER_BEGIN
+ * Starts transfer of a XCLBIN to the target region associated with a session,
+ * setting the target region's data transfer offset to 0. Although this command
+ * is available to all callers that are a member of the GENERAL privilege group
+ * an extra privilege check may be performed against the target region in
+ * addition to the check performed by MC_CMD_PR_OPEN. Returns ENOENT if the
+ * session handle doesn't exist; EPERM if the caller has insufficient privilege
+ * to update the target region; EBUSY if the target region is currently busy;
+ * ESTALE if the target region has been updated since the session was opened.
+ * The caller should close this handle and open a new session to retry its
+ * transfer; EINVAL if length is too small, e.g. smaller than the AXLF/XCLBIN2
+ * header; ENOMEM if length too large, e.g. larger than the resources available
+ * to buffer the transfer.
+ */
+#define	MC_CMD_PR_TRANSFER_BEGIN 0x1a4
+#define	MC_CMD_PR_TRANSFER_BEGIN_MSGSET 0x1a4
+#undef	MC_CMD_0x1a4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_TRANSFER_BEGIN_IN msgrequest */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LEN 16
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_HANDLE_LEN 4
+/* Reserved, must be zero. */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_RESERVED_OFST 4
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_RESERVED_LEN 4
+/* The length (in bytes) of the XCLBIN data to be transferred. */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_OFST 8
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LEN 8
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_OFST 8
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_LEN 4
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_LBN 64
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_WIDTH 32
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_OFST 12
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_LEN 4
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_LBN 96
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_WIDTH 32
+
+/* MC_CMD_PR_TRANSFER_BEGIN_OUT msgresponse */
+#define	MC_CMD_PR_TRANSFER_BEGIN_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_TRANSFER_WRITE
+ * Transfer a chunk of a XCLBIN data to the target region of a session,
+ * advancing the current data transfer offset. Chunks are transferred in a
+ * streaming like way and it is the responsibility of the caller to ensure all
+ * chunks are transferred in order and with no duplicates. Requires a transfer
+ * to have been started with MC_CMD_PR_TRANSFER_BEGIN. Returns ENOENT if the
+ * session handle doesn't exist; EACCESS if the session does not have an in-
+ * progress transfer; ESTALE if session's transfer has been cancelled, e.g.
+ * another session has started a transfer; ERANGE if the chunk exceeds the
+ * total transfer length specified in MC_CMD_PR_TRANSFER_BEGIN_IN.
+ */
+#define	MC_CMD_PR_TRANSFER_WRITE 0x1a5
+#define	MC_CMD_PR_TRANSFER_WRITE_MSGSET 0x1a5
+#undef	MC_CMD_0x1a5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_TRANSFER_WRITE_IN msgrequest */
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LENMIN 5
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LENMAX 252
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LEN(num) (4+1*(num))
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_NUM(len) (((len)-4)/1)
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_HANDLE_LEN 4
+/* Chunk of data to write */
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_OFST 4
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_LEN 1
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_MINNUM 1
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_MAXNUM 248
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_MAXNUM_MCDI2 1016
+
+/* MC_CMD_PR_TRANSFER_WRITE_OUT msgresponse */
+#define	MC_CMD_PR_TRANSFER_WRITE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_TRANSFER_END
+ * End the transfer of a XCLBIN to the target region of a session. A success
+ * result indicates the firmware started the update process. If the XCLBIN data
+ * is accepted, and programming has started, all other sessions for the same
+ * target region will be marked stale. The caller can use MC_CMD_PR_STATUS_GET
+ * to determine the overall result of the update. Requires a transfer to have
+ * been started with MC_CMD_PR_TRANSFER_BEGIN. Returns ENOENT if the session
+ * handle doesn't exist; EACCESS if the session does not have an in-progress
+ * transfer; ESTALE if session's transfer has been cancelled, e.g. another
+ * session has started a transfer.
+ */
+#define	MC_CMD_PR_TRANSFER_END 0x1a6
+#define	MC_CMD_PR_TRANSFER_END_MSGSET 0x1a6
+#undef	MC_CMD_0x1a6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_TRANSFER_END_IN msgrequest */
+#define	MC_CMD_PR_TRANSFER_END_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_TRANSFER_END_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_TRANSFER_END_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_TRANSFER_END_OUT msgresponse */
+#define	MC_CMD_PR_TRANSFER_END_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_STATUS_GET
+ * Query the current update status of the target region of a session. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened.
+ */
+#define	MC_CMD_PR_STATUS_GET 0x1a7
+#define	MC_CMD_PR_STATUS_GET_MSGSET 0x1a7
+#undef	MC_CMD_0x1a7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_STATUS_GET_IN msgrequest */
+#define	MC_CMD_PR_STATUS_GET_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_STATUS_GET_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_STATUS_GET_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_STATUS_GET_OUT msgresponse */
+#define	MC_CMD_PR_STATUS_GET_OUT_LENMIN 9
+#define	MC_CMD_PR_STATUS_GET_OUT_LENMAX 252
+#define	MC_CMD_PR_STATUS_GET_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_PR_STATUS_GET_OUT_LEN(num) (8+1*(num))
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_NUM(len) (((len)-8)/1)
+/* The state of the last update attempt triggered by MC_CMD_PR_TRANSFER_END or
+ * last action triggered by MC_CMD_PR_CONTROL.
+ */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_OFST 0
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_LEN 4
+/* enum: Update in progress */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_PENDING 0x0
+/* enum: Update successful, or no update attempted since device boot */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_SUCCESS 0x1
+/* enum: Update failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_ERROR 0x2
+/* Code providing more information about the state of the update process. */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_OFST 4
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_LEN 4
+/* enum: Operation successful */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_SUCCESS 0x0
+/* enum: xclbin package was not built for this platform */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_UUID_MISMATCH 0x1
+/* enum: Provided xclbin package contains no bitstream */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_NO_BITSTREAM 0x2
+/* enum: Provided xclbin package contains clock error */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_CLK_ERROR 0x3
+/* enum: Load attempt unexpectedly rejected - bitstream may be corrupt */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_BITSTREAM_ERROR 0x4
+/* enum: Clock programming failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_CLK_PROG_FAIL 0x5
+/* enum: Shell DDR failed to calibrate */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_DDR_CAL_FAIL 0x6
+/* enum: ICAP was unavailable before programming */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_ICAP_BUSY 0x7
+/* enum: ICAP failed to terminate programming */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_ICAP_FAIL 0x8
+/* enum: Clock scaling operation failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_CLK_SCALE_FAIL 0x9
+/* enum: Clock measurement operation failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_CLK_MON_FAIL 0xa
+/* enum: Firewall tripped */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_FIREWALL_TRIPPED 0xb
+/* enum: XCLBIN package parse error */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_PARSER_FAIL 0xc
+/* enum: Extension metadata load error */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_METADATA_LOAD_ERROR 0xd
+/* Result description (NUL-terminated ASCII string) */
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_OFST 8
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_LEN 1
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_MINNUM 1
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_MAXNUM 244
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_MAXNUM_MCDI2 1012
+
+
+/***********************************/
+/* MC_CMD_PR_CONTROL
+ * Control operations on programmable regions.
+ */
+#define	MC_CMD_PR_CONTROL 0x1ed
+#define	MC_CMD_PR_CONTROL_MSGSET 0x1ed
+#undef	MC_CMD_0x1ed_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ed_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_CONTROL_IN msgrequest */
+#define	MC_CMD_PR_CONTROL_IN_LEN 8
+/* Sub-command code */
+#define	MC_CMD_PR_CONTROL_IN_OP_OFST 0
+#define	MC_CMD_PR_CONTROL_IN_OP_LEN 4
+/* enum: Initiates the process of quiescing the logic within a programmable
+ * region in preparation for an update via an out-of-band mechanism. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened; EPERM if the
+ * caller has insufficient privilege to update the target region; EBUSY if the
+ * target region is currently busy and cannot be quieced (including if the
+ * region is being reinitialised); EALREADY if the target region is being
+ * quiesced or has already been quiesced. The progress of the quiesceing
+ * process can be checked with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET
+ * indicates that an error occurred during quiesceing them the programmable
+ * region is in an undefined state and the system must be reset. Once
+ * MC_CMD_PR_STATUS_GET indicates that the process has completed, a new image
+ * can be downloaded by the appropriate out-out-band mechanism.
+ */
+#define	MC_CMD_PR_CONTROL_IN_OP_QUIESCE 0x0
+/* enum: Reinitialise logic within a programmable region after an update via an
+ * out-of-band mechanism. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; EPERM if the caller has insufficient privilege to update
+ * the target region; EBUSY if the target region is currently being quiesced;
+ * EALREADY if the target region is currently being initialised or has already
+ * been initialised. The progress of the unquiesceing process can be checked
+ * with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET indicates that an error
+ * occurred during unquiesceing then the programmable region is still in a
+ * quiesced state. A new image can be downloaded via the appropriate out-of-
+ * band mechanism. Once MC_CMD_PR_STATUS_GET indicates that the process has
+ * completed, the logic within the programmable region is available for use.
+ */
+#define	MC_CMD_PR_CONTROL_IN_OP_UNQUIESCE 0x1
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CONTROL_IN_HANDLE_OFST 4
+#define	MC_CMD_PR_CONTROL_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CONTROL_OP_QUIESCE_IN msgrequest */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_LEN 8
+/* Sub-command code */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_OFST 0
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_LEN 4
+/* enum: Initiates the process of quiescing the logic within a programmable
+ * region in preparation for an update via an out-of-band mechanism. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened; EPERM if the
+ * caller has insufficient privilege to update the target region; EBUSY if the
+ * target region is currently busy and cannot be quieced (including if the
+ * region is being reinitialised); EALREADY if the target region is being
+ * quiesced or has already been quiesced. The progress of the quiesceing
+ * process can be checked with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET
+ * indicates that an error occurred during quiesceing them the programmable
+ * region is in an undefined state and the system must be reset. Once
+ * MC_CMD_PR_STATUS_GET indicates that the process has completed, a new image
+ * can be downloaded by the appropriate out-out-band mechanism.
+ */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_QUIESCE 0x0
+/* enum: Reinitialise logic within a programmable region after an update via an
+ * out-of-band mechanism. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; EPERM if the caller has insufficient privilege to update
+ * the target region; EBUSY if the target region is currently being quiesced;
+ * EALREADY if the target region is currently being initialised or has already
+ * been initialised. The progress of the unquiesceing process can be checked
+ * with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET indicates that an error
+ * occurred during unquiesceing then the programmable region is still in a
+ * quiesced state. A new image can be downloaded via the appropriate out-of-
+ * band mechanism. Once MC_CMD_PR_STATUS_GET indicates that the process has
+ * completed, the logic within the programmable region is available for use.
+ */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_UNQUIESCE 0x1
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_HANDLE_OFST 4
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CONTROL_OP_QUIESCE_OUT msgresponse */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_OUT_LEN 0
+
+/* MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN msgrequest */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_LEN 8
+/* Sub-command code */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_OFST 0
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_LEN 4
+/* enum: Initiates the process of quiescing the logic within a programmable
+ * region in preparation for an update via an out-of-band mechanism. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened; EPERM if the
+ * caller has insufficient privilege to update the target region; EBUSY if the
+ * target region is currently busy and cannot be quieced (including if the
+ * region is being reinitialised); EALREADY if the target region is being
+ * quiesced or has already been quiesced. The progress of the quiesceing
+ * process can be checked with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET
+ * indicates that an error occurred during quiesceing them the programmable
+ * region is in an undefined state and the system must be reset. Once
+ * MC_CMD_PR_STATUS_GET indicates that the process has completed, a new image
+ * can be downloaded by the appropriate out-out-band mechanism.
+ */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_QUIESCE 0x0
+/* enum: Reinitialise logic within a programmable region after an update via an
+ * out-of-band mechanism. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; EPERM if the caller has insufficient privilege to update
+ * the target region; EBUSY if the target region is currently being quiesced;
+ * EALREADY if the target region is currently being initialised or has already
+ * been initialised. The progress of the unquiesceing process can be checked
+ * with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET indicates that an error
+ * occurred during unquiesceing then the programmable region is still in a
+ * quiesced state. A new image can be downloaded via the appropriate out-of-
+ * band mechanism. Once MC_CMD_PR_STATUS_GET indicates that the process has
+ * completed, the logic within the programmable region is available for use.
+ */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_UNQUIESCE 0x1
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_HANDLE_OFST 4
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CONTROL_OP_UNQUIESCE_OUT msgresponse */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_METADATA_INFO
+ * Query information (length and name) about the meta-data describing the
+ * active contents of the target region of a session. Returns ENOENT if the
+ * session handle doesn't exist; ESTALE if the target region has been updated
+ * by another session since the session was opened; ENODEV if the meta-data
+ * item doesn't exist.
+ */
+#define	MC_CMD_PR_METADATA_INFO 0x1a8
+#define	MC_CMD_PR_METADATA_INFO_MSGSET 0x1a8
+#undef	MC_CMD_0x1a8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_METADATA_INFO_IN msgrequest */
+#define	MC_CMD_PR_METADATA_INFO_IN_LEN 16
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_METADATA_INFO_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_METADATA_INFO_IN_HANDLE_LEN 4
+/* Item category */
+#define	MC_CMD_PR_METADATA_INFO_IN_CATEGORY_OFST 4
+#define	MC_CMD_PR_METADATA_INFO_IN_CATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_CATEGORY */
+/* Item sub-category */
+#define	MC_CMD_PR_METADATA_INFO_IN_SUBCATEGORY_OFST 8
+#define	MC_CMD_PR_METADATA_INFO_IN_SUBCATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_SUBCATEGORY */
+/* Item index */
+#define	MC_CMD_PR_METADATA_INFO_IN_INDEX_OFST 12
+#define	MC_CMD_PR_METADATA_INFO_IN_INDEX_LEN 4
+
+/* MC_CMD_PR_METADATA_INFO_OUT msgresponse */
+#define	MC_CMD_PR_METADATA_INFO_OUT_LEN 136
+/* Length (in bytes) of the meta-data item */
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_OFST 0
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LEN 8
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_OFST 0
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_LEN 4
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_LBN 0
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_WIDTH 32
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_OFST 4
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_LEN 4
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_LBN 32
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_WIDTH 32
+/* Meta-data item name (NUL-terminated ASCII string). For the SECTION category
+ * the name is AXLF section name (axlf_section_header::m_sectionName). The
+ * items of the categories (UUID, TIMESTAMP and SIGNATURE) are unnamed items
+ * and return an empty string (NAME[0] == '\0').
+ */
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_NAME_OFST 8
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_NAME_LEN 1
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_NAME_NUM 128
+
+
+/***********************************/
+/* MC_CMD_PR_METADATA_READ
+ * Read a chunk of the meta-data describing the active contents of the target
+ * region of a session. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; ENODEV if the meta-data item doesn't exist; ERANGE if
+ * the offset is outside the valid range for the meta-data item, e.g. offset >=
+ * item_length.
+ */
+#define	MC_CMD_PR_METADATA_READ 0x1a9
+#define	MC_CMD_PR_METADATA_READ_MSGSET 0x1a9
+#undef	MC_CMD_0x1a9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_METADATA_READ_IN msgrequest */
+#define	MC_CMD_PR_METADATA_READ_IN_LEN 26
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_METADATA_READ_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_METADATA_READ_IN_HANDLE_LEN 4
+/* Item category */
+#define	MC_CMD_PR_METADATA_READ_IN_CATEGORY_OFST 4
+#define	MC_CMD_PR_METADATA_READ_IN_CATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_CATEGORY */
+/* Item sub-category */
+#define	MC_CMD_PR_METADATA_READ_IN_SUBCATEGORY_OFST 8
+#define	MC_CMD_PR_METADATA_READ_IN_SUBCATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_SUBCATEGORY */
+/* Item index */
+#define	MC_CMD_PR_METADATA_READ_IN_INDEX_OFST 12
+#define	MC_CMD_PR_METADATA_READ_IN_INDEX_LEN 4
+/* Byte offset within meta-data chunk */
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_OFST 16
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LEN 8
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_OFST 16
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_LEN 4
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_LBN 128
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_WIDTH 32
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_OFST 20
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_LEN 4
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_LBN 160
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_WIDTH 32
+/* Maximum length (in bytes) to read */
+#define	MC_CMD_PR_METADATA_READ_IN_MAX_LENGTH_OFST 24
+#define	MC_CMD_PR_METADATA_READ_IN_MAX_LENGTH_LEN 2
+
+/* MC_CMD_PR_METADATA_READ_OUT msgresponse */
+#define	MC_CMD_PR_METADATA_READ_OUT_LENMIN 1
+#define	MC_CMD_PR_METADATA_READ_OUT_LENMAX 252
+#define	MC_CMD_PR_METADATA_READ_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_PR_METADATA_READ_OUT_LEN(num) (0+1*(num))
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_NUM(len) (((len)-0)/1)
+/* Chunk of meta-data */
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_OFST 0
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_LEN 1
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_MINNUM 1
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_MAXNUM 252
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_MAXNUM_MCDI2 1020
+
+/* PR_FREQ_INFO structuredef: Information about a single programmable region
+ * clock
+ */
+#define	PR_FREQ_INFO_LEN 140
+/* Clock frequency (in Hz) */
+#define	PR_FREQ_INFO_FREQ_HZ_OFST 0
+#define	PR_FREQ_INFO_FREQ_HZ_LEN 8
+#define	PR_FREQ_INFO_FREQ_HZ_LO_OFST 0
+#define	PR_FREQ_INFO_FREQ_HZ_LO_LEN 4
+#define	PR_FREQ_INFO_FREQ_HZ_LO_LBN 0
+#define	PR_FREQ_INFO_FREQ_HZ_LO_WIDTH 32
+#define	PR_FREQ_INFO_FREQ_HZ_HI_OFST 4
+#define	PR_FREQ_INFO_FREQ_HZ_HI_LEN 4
+#define	PR_FREQ_INFO_FREQ_HZ_HI_LBN 32
+#define	PR_FREQ_INFO_FREQ_HZ_HI_WIDTH 32
+#define	PR_FREQ_INFO_FREQ_HZ_LBN 0
+#define	PR_FREQ_INFO_FREQ_HZ_WIDTH 64
+/* Clock type, a programmable region may have multiple clocks of the same type.
+ * (matches enum CLOCK_TYPE)
+ */
+#define	PR_FREQ_INFO_TYPE_OFST 8
+#define	PR_FREQ_INFO_TYPE_LEN 2
+/* enum: Unused/reserved. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_UNUSED 0x0
+/* enum: Data clock. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_DATA 0x1
+/* enum: Kernel clock. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_KERNEL 0x2
+/* enum: System clock. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_SYSTEM 0x3
+#define	PR_FREQ_INFO_TYPE_LBN 64
+#define	PR_FREQ_INFO_TYPE_WIDTH 16
+/* Assorted flags */
+#define	PR_FREQ_INFO_FLAGS_OFST 10
+#define	PR_FREQ_INFO_FLAGS_LEN 2
+#define	PR_FREQ_INFO_SETTABLE_OFST 10
+#define	PR_FREQ_INFO_SETTABLE_LBN 0
+#define	PR_FREQ_INFO_SETTABLE_WIDTH 1
+#define	PR_FREQ_INFO_FLAGS_LBN 80
+#define	PR_FREQ_INFO_FLAGS_WIDTH 16
+/* Clock name (NUL-terminated ASCII string) */
+#define	PR_FREQ_INFO_NAME_OFST 12
+#define	PR_FREQ_INFO_NAME_LEN 1
+#define	PR_FREQ_INFO_NAME_NUM 128
+#define	PR_FREQ_INFO_NAME_LBN 96
+#define	PR_FREQ_INFO_NAME_WIDTH 8
+
+
+/***********************************/
+/* MC_CMD_PR_FREQ_GET
+ * Query the current clock frequencies of the target region of a session. If
+ * the target region is 'empty' then an empty response should be returned.
+ * Returns ENOENT if the session handle doesn't exist; ESTALE if the target
+ * region has been updated by another session since the session was opened.
+ */
+#define	MC_CMD_PR_FREQ_GET 0x1aa
+#define	MC_CMD_PR_FREQ_GET_MSGSET 0x1aa
+#undef	MC_CMD_0x1aa_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1aa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_FREQ_GET_IN msgrequest */
+#define	MC_CMD_PR_FREQ_GET_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_FREQ_GET_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_FREQ_GET_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_FREQ_GET_OUT msgresponse */
+#define	MC_CMD_PR_FREQ_GET_OUT_LENMIN 0
+#define	MC_CMD_PR_FREQ_GET_OUT_LENMAX 140
+#define	MC_CMD_PR_FREQ_GET_OUT_LENMAX_MCDI2 980
+#define	MC_CMD_PR_FREQ_GET_OUT_LEN(num) (0+140*(num))
+#define	MC_CMD_PR_FREQ_GET_OUT_INFOS_NUM(len) (((len)-0)/140)
+/* An array of PR_FREQ_INFO structures. */
+#define	MC_CMD_PR_FREQ_GET_OUT_INFOS_OFST 0
+#define	MC_CMD_PR_FREQ_GET_OUT_INFOS_LEN 140
+
+
+/***********************************/
+/* MC_CMD_PR_FREQ_SET
+ * Set the desired clock frequencies of the target region of a session. The
+ * FREQ_HZ array must contain the same number of entries as the output to
+ * MC_CMD_PR_FREQ_GET. Callers should expect that the resulting frequencies may
+ * not precisely match the input and can use MC_CMD_PR_FREQ_GET to determine
+ * the actual frequencies selected. The algorithm for selecting the resulting
+ * clock settings is a firmware implementation detail based on the capabilities
+ * of the device and the target region. It is expected that the firmware will
+ * not exceed the desired frequency for any clock; will successfully apply a
+ * frequency value obtained from MC_CMD_PR_FREQ_GET without further adjustment;
+ * and if an error is returned no changes will have been applied to any of the
+ * clocks. Although this command is available to all callers that are a member
+ * of the GENERAL privilege group an extra privilege check may be performed
+ * against the target region in addition to tbe check performed by
+ * MC_CMD_PR_OPEN. Returns ENOENT if the session handle doesn't exist; ESTALE
+ * if the target region has been updated by another session since the session
+ * was opened; EINVAL if the target region is 'empty' or the wrong number of
+ * desired clock frequencies was specified in the input; ERANGE if one or more
+ * desired clock frequencies were not achievable.
+ */
+#define	MC_CMD_PR_FREQ_SET 0x1ab
+#define	MC_CMD_PR_FREQ_SET_MSGSET 0x1ab
+#undef	MC_CMD_0x1ab_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ab_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_FREQ_SET_IN msgrequest */
+#define	MC_CMD_PR_FREQ_SET_IN_LENMIN 16
+#define	MC_CMD_PR_FREQ_SET_IN_LENMAX 248
+#define	MC_CMD_PR_FREQ_SET_IN_LENMAX_MCDI2 1016
+#define	MC_CMD_PR_FREQ_SET_IN_LEN(num) (8+8*(num))
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_NUM(len) (((len)-8)/8)
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_FREQ_SET_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_FREQ_SET_IN_HANDLE_LEN 4
+/* Reserved, must be zero. */
+#define	MC_CMD_PR_FREQ_SET_IN_RESERVED_OFST 4
+#define	MC_CMD_PR_FREQ_SET_IN_RESERVED_LEN 4
+/* Desired frequency for each clock */
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_OFST 8
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LEN 8
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_OFST 8
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_LEN 4
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_LBN 64
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_WIDTH 32
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_OFST 12
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_LEN 4
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_LBN 96
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_WIDTH 32
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_MINNUM 1
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_MAXNUM 30
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_MAXNUM_MCDI2 126
+/* enum: Leave the clock frequency unchanged. */
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_DONT_CHANGE 0x0
+
+/* MC_CMD_PR_FREQ_SET_OUT msgresponse */
+#define	MC_CMD_PR_FREQ_SET_OUT_LEN 0
+
 /* TABLE_FIELD_DESCR structuredef: An individual table field descriptor. This
  * describes the location and properties of one N-bit field within a wider
  * M-bit key/mask/response value.
@@ -34323,4 +39938,151 @@
 /* MC_CMD_TABLE_DELETE_OUT msgresponse */
 #define	MC_CMD_TABLE_DELETE_OUT_LEN 0
 
+/* MC_CMD_QUEUE_HANDLE structuredef: On X4, to distinguish between full-
+ * featured (X2-style) VIs and low-latency (X3-style) queues, we use the top
+ * bits of the queue handle to specify the queue type in all MCDI calls which
+ * refer to VIs/queues. These bits should be masked off when indexing into a
+ * queue in the BAR.
+ */
+#define	MC_CMD_QUEUE_HANDLE_LEN 4
+/* Combined queue number and type. This is the ID returned by and passed into
+ * MCDI calls that use queues.
+ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_OFST 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LEN 4
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_NUM_OFST 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_NUM_LBN 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_NUM_WIDTH 24
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_OFST 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LBN 24
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_WIDTH 8
+/* enum: Indicates that the queue instance is a full-featured VI */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0
+/* enum: Indicates that the queue instance is a LL TXQ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1
+/* enum: Indicates that the queue instance is a LL RXQ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2
+/* enum: Indicates that the queue instance is a LL EVQ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LBN 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_WIDTH 32
+
+/* QUEUE_HANDLE structuredef: This definition is deprecated, use
+ * MC_CMD_QUEUE_HANDLE above.
+ */
+#define	QUEUE_HANDLE_LEN 4
+/* Combined queue number and type. This is the ID returned by and passed into
+ * MCDI calls that use queues.
+ */
+#define	QUEUE_HANDLE_QUEUE_HANDLE_OFST 0
+#define	QUEUE_HANDLE_QUEUE_HANDLE_LEN 4
+#define	QUEUE_HANDLE_QUEUE_NUM_OFST 0
+#define	QUEUE_HANDLE_QUEUE_NUM_LBN 0
+#define	QUEUE_HANDLE_QUEUE_NUM_WIDTH 24
+#define	QUEUE_HANDLE_QUEUE_TYPE_OFST 0
+#define	QUEUE_HANDLE_QUEUE_TYPE_LBN 24
+#define	QUEUE_HANDLE_QUEUE_TYPE_WIDTH 8
+/* enum: Indicates that the queue instance is a full-featured VI */
+#define	QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0
+/* enum: Indicates that the queue instance is a LL TXQ */
+#define	QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1
+/* enum: Indicates that the queue instance is a LL RXQ */
+#define	QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2
+/* enum: Indicates that the queue instance is a LL EVQ */
+#define	QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3
+#define	QUEUE_HANDLE_QUEUE_HANDLE_LBN 0
+#define	QUEUE_HANDLE_QUEUE_HANDLE_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_ALLOC_LL_QUEUES
+ * Allocate low latency (X3-style) queues for current PCI function. Can be
+ * called more than once if desired to allocate more queues.
+ */
+#define	MC_CMD_ALLOC_LL_QUEUES 0x1dd
+#define	MC_CMD_ALLOC_LL_QUEUES_MSGSET 0x1dd
+#undef	MC_CMD_0x1dd_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1dd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_ALLOC_LL_QUEUES_IN msgrequest */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_LEN 24
+/* The minimum number of TXQs that is acceptable */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_OFST 0
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_LEN 4
+/* The maximum number of TXQs that would be useful */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_OFST 4
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_LEN 4
+/* The minimum number of RXQs that is acceptable */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_OFST 8
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_LEN 4
+/* The maximum number of RXQs that would be useful */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_OFST 12
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_LEN 4
+/* The minimum number of EVQs that is acceptable */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_OFST 16
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_LEN 4
+/* The maximum number of EVQs that would be useful */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_OFST 20
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_LEN 4
+
+/* MC_CMD_ALLOC_LL_QUEUES_OUT msgresponse */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LENMIN 16
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX 252
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LEN(num) (12+4*(num))
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_NUM(len) (((len)-12)/4)
+/* The number of TXQs allocated in this request */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_OFST 0
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_LEN 4
+/* The number of RXQs allocated in this request */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_OFST 4
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_LEN 4
+/* The number of EVQs allocated in this request */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_OFST 8
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_LEN 4
+/* A list of allocated queues, returned as MC_CMD_QUEUE_HANDLEs, not
+ * necessarily contiguous. TXQs are first in the list, followed by RXQs then
+ * EVQs. The type of each queue is indicated by the top bits (see the
+ * QUEUE_TYPE enum)
+ */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_OFST 12
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_LEN 4
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MINNUM 1
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM 60
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM_MCDI2 252
+
+
+/***********************************/
+/* MC_CMD_FREE_LL_QUEUES
+ * Free low latency (X3-style) queues for current PCI function.
+ */
+#define	MC_CMD_FREE_LL_QUEUES 0x1de
+#define	MC_CMD_FREE_LL_QUEUES_MSGSET 0x1de
+#undef	MC_CMD_0x1de_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1de_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FREE_LL_QUEUES_IN msgrequest */
+#define	MC_CMD_FREE_LL_QUEUES_IN_LENMIN 8
+#define	MC_CMD_FREE_LL_QUEUES_IN_LENMAX 252
+#define	MC_CMD_FREE_LL_QUEUES_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_FREE_LL_QUEUES_IN_LEN(num) (4+4*(num))
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_NUM(len) (((len)-4)/4)
+/* The number of queues to free. */
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_OFST 0
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_LEN 4
+/* A list of queues to free, as a list of MC_CMD_QUEUE_HANDLEs. They must have
+ * all been previously allocated by MC_CMD_ALLOC_LL_QUEUES. The type of each
+ * queue should be indicated by the top bits.
+ */
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_OFST 4
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_LEN 4
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MINNUM 1
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM 62
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM_MCDI2 254
+
+/* MC_CMD_FREE_LL_QUEUES_OUT msgresponse */
+#define	MC_CMD_FREE_LL_QUEUES_OUT_LEN 0
+
 #endif /* _SIENA_MC_DRIVER_PCOL_H */
-- 
2.39.5

[PATCH 20/46] common/sfc_efx/base: provide a stub for basic netport attach

[Ivan Malov]

New NICs (for instance, Medford4) offer new netport MCDI for
managing physical ports, which will supersede the legacy one.
Scope out the new interface initialisation on NIC probe path.
That will be augmented with the actual code by later patches.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_nic.c  | 30 ++++++++++++++++++------
 drivers/common/sfc_efx/base/efx_impl.h  | 15 ++++++++++++
 drivers/common/sfc_efx/base/efx_np.c    | 31 +++++++++++++++++++++++++
 drivers/common/sfc_efx/base/meson.build |  1 +
 4 files changed, 70 insertions(+), 7 deletions(-)
 create mode 100644 drivers/common/sfc_efx/base/efx_np.c

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index e1e8de5396..eb1b68b17e 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -2221,6 +2221,9 @@ efx_mcdi_nic_board_cfg(
 
 	encp->enc_board_type = board_type;
 
+	if (efx_np_supported(enp) != B_FALSE)
+		goto skip_phy_props;
+
 	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
 		goto fail8;
@@ -2246,6 +2249,7 @@ efx_mcdi_nic_board_cfg(
 	epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
 	epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
 
+skip_phy_props:
 	/* Check capabilities of running datapath firmware */
 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
 		goto fail10;
@@ -2499,6 +2503,10 @@ ef10_nic_probe(
 	if ((rc = ef10_nic_board_cfg(enp)) != 0)
 		goto fail4;
 
+	rc = efx_np_attach(enp);
+	if (rc != 0)
+		goto fail5;
+
 	/*
 	 * Set default driver config limits (based on board config).
 	 *
@@ -2516,36 +2524,41 @@ ef10_nic_probe(
 #if EFSYS_OPT_MAC_STATS
 	/* Wipe the MAC statistics */
 	if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
-		goto fail5;
+		goto fail6;
 #endif
 
 #if EFSYS_OPT_LOOPBACK
-	if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
-		goto fail6;
+	if (efx_np_supported(enp) == B_FALSE) {
+		rc = efx_mcdi_get_loopback_modes(enp);
+		if (rc != 0)
+			goto fail7;
+	}
 #endif
 
 #if EFSYS_OPT_MON_STATS
 	if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
 		/* Unprivileged functions do not have access to sensors */
 		if (rc != EACCES)
-			goto fail7;
+			goto fail8;
 	}
 #endif
 
 	return (0);
 
 #if EFSYS_OPT_MON_STATS
+fail8:
+	EFSYS_PROBE(fail8);
+#endif
+#if EFSYS_OPT_LOOPBACK
 fail7:
 	EFSYS_PROBE(fail7);
 #endif
-#if EFSYS_OPT_LOOPBACK
+#if EFSYS_OPT_MAC_STATS
 fail6:
 	EFSYS_PROBE(fail6);
 #endif
-#if EFSYS_OPT_MAC_STATS
 fail5:
 	EFSYS_PROBE(fail5);
-#endif
 fail4:
 	EFSYS_PROBE(fail4);
 fail3:
@@ -3005,6 +3018,9 @@ ef10_nic_unprobe(
 #if EFSYS_OPT_MON_STATS
 	mcdi_mon_cfg_free(enp);
 #endif /* EFSYS_OPT_MON_STATS */
+
+	efx_np_detach(enp);
+
 	(void) efx_mcdi_drv_attach(enp, B_FALSE);
 }
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 89b7e0292e..9ad973ded7 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1880,6 +1880,21 @@ struct efx_virtio_vq_s {
 
 #endif /* EFSYS_OPT_VIRTIO */
 
+LIBEFX_INTERNAL
+extern			boolean_t
+efx_np_supported(
+	__in		efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_attach(
+	__in		efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern		void
+efx_np_detach(
+	__in	efx_nic_t *enp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
new file mode 100644
index 0000000000..432185f311
--- /dev/null
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#include "efx.h"
+#include "efx_impl.h"
+
+			boolean_t
+efx_np_supported(
+	__in		efx_nic_t *enp)
+{
+	return (enp->en_family >= EFX_FAMILY_MEDFORD4) ? B_TRUE : B_FALSE;
+}
+
+	__checkReturn	efx_rc_t
+efx_np_attach(
+	__in		efx_nic_t *enp)
+{
+	if (efx_np_supported(enp) == B_FALSE)
+		return (0);
+
+	return (0);
+}
+
+		void
+efx_np_detach(
+	__in	efx_nic_t *enp)
+{
+	if (efx_np_supported(enp) == B_FALSE)
+		return;
+}
diff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build
index c8deb4555e..02d5b2fbb9 100644
--- a/drivers/common/sfc_efx/base/meson.build
+++ b/drivers/common/sfc_efx/base/meson.build
@@ -20,6 +20,7 @@ sources = [
         'efx_mcdi.c',
         'efx_mon.c',
         'efx_nic.c',
+        'efx_np.c',
         'efx_nvram.c',
         'efx_pci.c',
         'efx_phy.c',
-- 
2.39.5

[PATCH 21/46] common/sfc_efx/base: provide defaults on netport attach path

[Ivan Malov]

Fill in some port information, including legacy Siena fields.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_np.c | 44 ++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 432185f311..3200bc0a90 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -12,13 +12,57 @@ efx_np_supported(
 	return (enp->en_family >= EFX_FAMILY_MEDFORD4) ? B_TRUE : B_FALSE;
 }
 
+static				void
+efx_np_assign_legacy_props(
+	__in			efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+
+	memset(encp->enc_phy_revision, 0, sizeof (encp->enc_phy_revision));
+	encp->enc_phy_type = 0;
+
+#if EFSYS_OPT_NAMES
+	memset(encp->enc_phy_name, 0, sizeof (encp->enc_phy_name));
+#endif /* EFSYS_OPT_NAMES */
+
+#if EFSYS_OPT_PHY_STATS
+	encp->enc_mcdi_phy_stat_mask = 0;
+#endif /* EFSYS_OPT_PHY_STATS */
+
+#if EFSYS_OPT_PHY_FLAGS
+	encp->enc_phy_flags_mask = 0;
+#endif /* EFSYS_OPT_PHY_FLAGS */
+
+#if EFSYS_OPT_BIST
+	encp->enc_bist_mask = 0;
+#endif /* EFSYS_OPT_BIST */
+
+	encp->enc_mcdi_mdio_channel = 0;
+	encp->enc_port = 0;
+}
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
 {
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+
 	if (efx_np_supported(enp) == B_FALSE)
 		return (0);
 
+	/*
+	 * Some EFX properties are mostly leftover from Siena era
+	 * and we prefer to initialise those to harmless defaults.
+	 */
+	efx_np_assign_legacy_props(enp);
+
+#if EFSYS_OPT_PHY_LED_CONTROL
+	encp->enc_led_mask = 1U << EFX_PHY_LED_DEFAULT;
+#endif /* EFSYS_OPT_PHY_LED_CONTROL */
+
+	epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID;
+	epp->ep_module_type = EFX_PHY_MEDIA_INVALID;
 	return (0);
 }
 
-- 
2.39.5

[PATCH 22/46] common/sfc_efx/base: obtain assigned netport handle from NIC

[Ivan Malov]

Get an 'assigned' netport handle for the current MCDI entity.
This handle will be used when sending other netport commands.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h |  4 +++
 drivers/common/sfc_efx/base/efx_np.c   | 50 ++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 9ad973ded7..4952f45121 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -335,6 +335,8 @@ typedef struct efx_virtio_ops_s {
 } efx_virtio_ops_t;
 #endif /* EFSYS_OPT_VIRTIO */
 
+typedef uint32_t efx_np_handle_t;
+
 typedef struct efx_port_s {
 	efx_mac_type_t		ep_mac_type;
 	uint32_t		ep_phy_type;
@@ -378,6 +380,8 @@ typedef struct efx_port_s {
 #endif
 	const efx_mac_ops_t	*ep_emop;
 	const efx_phy_ops_t	*ep_epop;
+
+	efx_np_handle_t		ep_np_handle;
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 3200bc0a90..ec6a432623 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -41,12 +41,53 @@ efx_np_assign_legacy_props(
 	encp->enc_port = 0;
 }
 
+static	__checkReturn		efx_rc_t
+efx_np_get_assigned_handle(
+	__in			efx_nic_t *enp,
+	__out			efx_np_handle_t *nphp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN,
+	    MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN;
+	req.emr_in_length = MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN;
+	req.emr_cmd = MC_CMD_GET_ASSIGNED_PORT_HANDLE;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	*nphp = MCDI_OUT_DWORD(req, GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE);
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
 
 	if (efx_np_supported(enp) == B_FALSE)
 		return (0);
@@ -63,7 +104,16 @@ efx_np_attach(
 
 	epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID;
 	epp->ep_module_type = EFX_PHY_MEDIA_INVALID;
+
+	rc = efx_np_get_assigned_handle(enp, &epp->ep_np_handle);
+	if (rc != 0)
+		goto fail1;
+
 	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
 }
 
 		void
-- 
2.39.5

[PATCH 23/46] common/sfc_efx/base: allow for const in MCDI struct accessor

[Ivan Malov]

The existing code is fine, however, future patches will need
to use this macro on buffers that are passed by callers with
const qualifier. With 'cast-qual' enabled, this macro causes
compile warnings in such cases. Rework it to allow for const.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_mcdi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/sfc_efx/base/efx_mcdi.h b/drivers/common/sfc_efx/base/efx_mcdi.h
index f13bf43da6..4e82717015 100644
--- a/drivers/common/sfc_efx/base/efx_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_mcdi.h
@@ -536,7 +536,7 @@ efx_mcdi_set_nic_addr_regions(
 		EFX_DWORD_1) << 32)
 
 #define MCDI_STRUCT_MEMBER(_buf, _type, _ofst)				\
-	((_type *)((char *)_buf + _ofst ## _OFST))	\
+	((_type *)((char *)(uintptr_t)(_buf) + _ofst ## _OFST))
 
 #define MCDI_STRUCT_BYTE(_buf, _ofst)					\
 	EFX_BYTE_FIELD(*MCDI_STRUCT_MEMBER(_buf, efx_byte_t, _ofst),	\
-- 
2.39.5

[PATCH 24/46] common/sfc_efx/base: get netport fixed capabilities on probe

[Ivan Malov]

These make the basic subset of PHY capabilities known to EFX

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx.h    |  21 ++-
 drivers/common/sfc_efx/base/efx_np.c | 209 +++++++++++++++++++++++++++
 2 files changed, 224 insertions(+), 6 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index a9ed3f423f..2c6af5f6b5 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1212,6 +1212,11 @@ typedef enum efx_phy_cap_type_e {
 	EFX_PHY_CAP_RS_FEC_REQUESTED,
 	EFX_PHY_CAP_25G_BASER_FEC,
 	EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
+	EFX_PHY_CAP_200000FDX,
+	EFX_PHY_CAP_IEEE_RS_INT_FEC,
+	EFX_PHY_CAP_IEEE_RS_INT_FEC_REQUESTED,
+	EFX_PHY_CAP_ETCS_RS_LL_FEC,
+	EFX_PHY_CAP_ETCS_RS_LL_FEC_REQUESTED,
 	EFX_PHY_CAP_NTYPES
 } efx_phy_cap_type_t;
 
@@ -4009,12 +4014,16 @@ typedef enum efx_phy_fec_type_e {
 
 #define EFX_PHY_CAP_FEC_BIT(_fec_bit) (1U << EFX_PHY_CAP_##_fec_bit)
 #define EFX_PHY_CAP_FEC_MASK \
-	(EFX_PHY_CAP_FEC_BIT(BASER_FEC) |		\
-	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) |		\
-	 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED) |	\
-	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED) |	\
-	 EFX_PHY_CAP_FEC_BIT(RS_FEC) |			\
-	 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED))
+	(EFX_PHY_CAP_FEC_BIT(BASER_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED) |		\
+	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED) |		\
+	 EFX_PHY_CAP_FEC_BIT(RS_FEC) |				\
+	 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED) |		\
+	 EFX_PHY_CAP_FEC_BIT(IEEE_RS_INT_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(IEEE_RS_INT_FEC_REQUESTED) |	\
+	 EFX_PHY_CAP_FEC_BIT(ETCS_RS_LL_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(ETCS_RS_LL_FEC_REQUESTED))
 
 LIBEFX_API
 extern	__checkReturn	efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index ec6a432623..6a36abf5c9 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -76,6 +76,203 @@ efx_np_get_assigned_handle(
 fail2:
 	EFSYS_PROBE(fail2);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+struct efx_np_cap_map {
+	uint16_t	encm_hw;
+	uint16_t	encm_sw;
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_tech[] = {
+	/* 1G */
+	{ MC_CMD_ETH_TECH_1000BASEKX, EFX_PHY_CAP_1000FDX },
+	{ MC_CMD_ETH_TECH_1000BASEX, EFX_PHY_CAP_1000FDX },
+
+	/* 10G */
+	{ MC_CMD_ETH_TECH_10GBASE_KR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_CR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_SR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_LR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_LRM, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_ER, EFX_PHY_CAP_10000FDX },
+
+	/* 25GBASE */
+	{ MC_CMD_ETH_TECH_25GBASE_CR, EFX_PHY_CAP_25000FDX },
+	{ MC_CMD_ETH_TECH_25GBASE_KR, EFX_PHY_CAP_25000FDX },
+	{ MC_CMD_ETH_TECH_25GBASE_SR, EFX_PHY_CAP_25000FDX },
+	{ MC_CMD_ETH_TECH_25GBASE_LR_ER, EFX_PHY_CAP_25000FDX },
+
+	/* 40G */
+	{ MC_CMD_ETH_TECH_40GBASE_KR4, EFX_PHY_CAP_40000FDX },
+	{ MC_CMD_ETH_TECH_40GBASE_CR4, EFX_PHY_CAP_40000FDX },
+	{ MC_CMD_ETH_TECH_40GBASE_SR4, EFX_PHY_CAP_40000FDX },
+	{ MC_CMD_ETH_TECH_40GBASE_LR4, EFX_PHY_CAP_40000FDX },
+
+	/* 50G */
+	{ MC_CMD_ETH_TECH_50GBASE_CR2, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_KR2, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_SR2, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_KR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_SR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_CR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_LR_ER_FR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_DR, EFX_PHY_CAP_50000FDX },
+
+	/* 100G */
+	{ MC_CMD_ETH_TECH_100GBASE_KR4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_SR4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_LR4_ER4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_KR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_SR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_DR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_KR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_SR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_LR_ER_FR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_DR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR10, EFX_PHY_CAP_100000FDX },
+
+	/* 200G */
+	{ MC_CMD_ETH_TECH_200GBASE_KR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_SR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_DR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_CR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_KR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_SR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_DR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_CR2, EFX_PHY_CAP_200000FDX },
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_fec[] = {
+	{ MC_CMD_FEC_BASER, EFX_PHY_CAP_BASER_FEC },
+	{ MC_CMD_FEC_RS, EFX_PHY_CAP_RS_FEC },
+	{ MC_CMD_FEC_IEEE_RS_INT, EFX_PHY_CAP_IEEE_RS_INT_FEC },
+	{ MC_CMD_FEC_ETCS_RS_LL, EFX_PHY_CAP_ETCS_RS_LL_FEC },
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_fec_req[] = {
+	{ MC_CMD_FEC_BASER, EFX_PHY_CAP_BASER_FEC_REQUESTED },
+	{ MC_CMD_FEC_RS, EFX_PHY_CAP_RS_FEC_REQUESTED },
+	{ MC_CMD_FEC_IEEE_RS_INT, EFX_PHY_CAP_IEEE_RS_INT_FEC_REQUESTED },
+	{ MC_CMD_FEC_ETCS_RS_LL, EFX_PHY_CAP_ETCS_RS_LL_FEC_REQUESTED },
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_pause[] = {
+	{ MC_CMD_PAUSE_MODE_AN_ASYM_DIR, EFX_PHY_CAP_ASYM },
+	{ MC_CMD_PAUSE_MODE_AN_PAUSE, EFX_PHY_CAP_PAUSE },
+};
+
+#define	CAP_BYTE(_map)	((_map)->encm_hw / CHAR_BIT)
+
+#define	CAP_VLD(_map, _data_nbytes)	(CAP_BYTE(_map) < (_data_nbytes))
+
+#define	CAP_FLAG(_map)	(1U << ((_map)->encm_hw % CHAR_BIT))
+
+#define	CAP_SUP(_map, _data)						\
+	(((_data)[CAP_BYTE(_map)] & CAP_FLAG(_map)) == CAP_FLAG(_map))
+
+#define	FOREACH_SUP_CAP(_map, _map_nentries, _data, _data_nbytes)	\
+	for (unsigned int _i = 0; _i < (_map_nentries); ++_i, ++(_map))	\
+		if (CAP_VLD(_map, _data_nbytes) && CAP_SUP(_map, _data))
+
+static					void
+efx_np_cap_mask_hw_to_sw(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__out				uint32_t *sw_cap_maskp)
+{
+	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
+	    hw_cap_data, hw_cap_data_nbytes) {
+		*sw_cap_maskp |= 1U << hw_sw_map->encm_sw;
+	}
+}
+
+/*
+ * Convert the given fraction of raw HW netport capability data (identified by
+ * the given section name of the MCDI response) to the EFX mask representation,
+ * in accordance with the specified collection of HW-to-SW capability mappings.
+ */
+#define	EFX_NP_CAP_MASK_HW_TO_SW(					\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data, _sw_maskp)	\
+	efx_np_cap_mask_hw_to_sw((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN, (_sw_maskp))
+
+static				void
+efx_np_cap_hw_data_to_sw_mask(
+	__in			const uint8_t *hw_data,
+	__out			uint32_t *sw_maskp)
+{
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_tech, ETH_AN_FIELDS_TECH_MASK,
+	    hw_data, sw_maskp);
+
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_fec, ETH_AN_FIELDS_FEC_MASK,
+	    hw_data, sw_maskp);
+
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_fec_req, ETH_AN_FIELDS_FEC_REQ,
+	    hw_data, sw_maskp);
+
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_pause, ETH_AN_FIELDS_PAUSE_MASK,
+	    hw_data, sw_maskp);
+}
+
+static	__checkReturn		efx_rc_t
+efx_np_get_fixed_port_props(
+	__in			efx_nic_t *enp,
+	__in			efx_np_handle_t nph,
+	__out_opt		uint32_t *sup_cap_maskp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN,
+	    MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN);
+	const uint8_t *cap_data;
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN;
+	req.emr_in_length = MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN;
+	req.emr_cmd = MC_CMD_GET_FIXED_PORT_PROPERTIES;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE, nph);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used <
+	    MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	cap_data = MCDI_OUT2(req, const uint8_t,
+		    GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES);
+
+	if (sup_cap_maskp != NULL)
+		efx_np_cap_hw_data_to_sw_mask(cap_data, sup_cap_maskp);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
@@ -109,8 +306,20 @@ efx_np_attach(
 	if (rc != 0)
 		goto fail1;
 
+	/*
+	 * FIXME: This may need revisiting for VFs, which
+	 * don't necessarily have access to these details.
+	 */
+	rc = efx_np_get_fixed_port_props(enp, epp->ep_np_handle,
+		    &epp->ep_phy_cap_mask);
+	if (rc != 0)
+		goto fail2;
+
 	return (0);
 
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
-- 
2.39.5

[PATCH 25/46] common/sfc_efx/base: decode netport link state on probe path

[Ivan Malov]

Retrieved properties form the advertised PHY capability mask.
The new code also helps to check support for autonegotiation.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h | 12 +++++
 drivers/common/sfc_efx/base/efx_np.c   | 67 ++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 4952f45121..a3e60fd19b 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1899,6 +1899,18 @@ extern		void
 efx_np_detach(
 	__in	efx_nic_t *enp);
 
+typedef struct efx_np_link_state_s {
+	uint32_t		enls_adv_cap_mask;
+	boolean_t		enls_an_supported;
+} efx_np_link_state_t;
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_link_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_link_state_t *lsp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 6a36abf5c9..4d69e620d9 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -273,6 +273,61 @@ efx_np_get_fixed_port_props(
 fail2:
 	EFSYS_PROBE(fail2);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+efx_np_link_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_link_state_t *lsp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_LINK_STATE_IN_LEN,
+	    MC_CMD_LINK_STATE_OUT_V3_LEN);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_LINK_STATE_OUT_V3_LEN;
+	req.emr_in_length = MC_CMD_LINK_STATE_IN_LEN;
+	req.emr_cmd = MC_CMD_LINK_STATE;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, LINK_STATE_IN_PORT_HANDLE, nph);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_LINK_STATE_OUT_V3_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	memset(lsp, 0, sizeof (*lsp));
+
+	if (MCDI_OUT_DWORD(req, LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT) !=
+	    MC_CMD_AN_NONE)
+		lsp->enls_an_supported = B_TRUE;
+
+	if (lsp->enls_an_supported != B_FALSE)
+		lsp->enls_adv_cap_mask |= 1U << EFX_PHY_CAP_AN;
+
+	efx_np_cap_hw_data_to_sw_mask(
+	    MCDI_OUT2(req, const uint8_t, LINK_STATE_OUT_ADVERTISED_ABILITIES),
+	    &lsp->enls_adv_cap_mask);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
@@ -284,6 +339,7 @@ efx_np_attach(
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
+	efx_np_link_state_t ls;
 	efx_rc_t rc;
 
 	if (efx_np_supported(enp) == B_FALSE)
@@ -315,8 +371,19 @@ efx_np_attach(
 	if (rc != 0)
 		goto fail2;
 
+	rc = efx_np_link_state(enp, epp->ep_np_handle, &ls);
+	if (rc != 0)
+		goto fail3;
+
+	if (ls.enls_an_supported != B_FALSE)
+		epp->ep_phy_cap_mask |= 1U << EFX_PHY_CAP_AN;
+
+	epp->ep_adv_cap_mask = ls.enls_adv_cap_mask;
 	return (0);
 
+fail3:
+	EFSYS_PROBE(fail3);
+
 fail2:
 	EFSYS_PROBE(fail2);
 
-- 
2.39.5

[PATCH 26/46] common/sfc_efx/base: fill in loopback modes on netport probe

[Ivan Malov]

Indicate support for some of the loopback modes known to EFX.
Such have been technology-dependent, but, on netport capable
NICs, they are backed by new generic modes, that are tied to
the stages in the processing chain where loopback can happen.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx.h      |   1 +
 drivers/common/sfc_efx/base/efx_impl.h |   2 +
 drivers/common/sfc_efx/base/efx_np.c   | 159 ++++++++++++++++++++++++-
 3 files changed, 160 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 2c6af5f6b5..7ffa1f4cbd 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -655,6 +655,7 @@ typedef enum efx_link_mode_e {
 	EFX_LINK_25000FDX,
 	EFX_LINK_50000FDX,
 	EFX_LINK_100000FDX,
+	EFX_LINK_200000FDX,
 	EFX_LINK_NMODES
 } efx_link_mode_t;
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index a3e60fd19b..3a9c6fe3fd 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -382,6 +382,8 @@ typedef struct efx_port_s {
 	const efx_phy_ops_t	*ep_epop;
 
 	efx_np_handle_t		ep_np_handle;
+	efx_qword_t		ep_np_loopback_cap_mask;
+	uint8_t			ep_np_cap_data_raw[MC_CMD_ETH_AN_FIELDS_LEN];
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 4d69e620d9..2e4cdcf863 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -232,7 +232,9 @@ static	__checkReturn		efx_rc_t
 efx_np_get_fixed_port_props(
 	__in			efx_nic_t *enp,
 	__in			efx_np_handle_t nph,
-	__out_opt		uint32_t *sup_cap_maskp)
+	__out_opt		uint8_t *sup_cap_rawp,
+	__out_opt		uint32_t *sup_cap_maskp,
+	__out_opt		efx_qword_t *loopback_cap_maskp)
 {
 	EFX_MCDI_DECLARE_BUF(payload,
 	    MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN,
@@ -268,6 +270,18 @@ efx_np_get_fixed_port_props(
 	if (sup_cap_maskp != NULL)
 		efx_np_cap_hw_data_to_sw_mask(cap_data, sup_cap_maskp);
 
+	if (sup_cap_rawp != NULL) {
+		memcpy(sup_cap_rawp,
+		    MCDI_OUT2(req, const uint8_t,
+			    GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES),
+		    MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_LEN);
+	}
+
+	if (loopback_cap_maskp != NULL) {
+		*loopback_cap_maskp = *MCDI_OUT2(req, efx_qword_t,
+		    GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2);
+	}
+
 	return (0);
 
 fail2:
@@ -333,6 +347,141 @@ efx_np_link_state(
 	return (rc);
 }
 
+#if EFSYS_OPT_LOOPBACK
+static	__checkReturn		efx_rc_t
+efx_np_sw_link_mode_to_cap(
+	__in			efx_link_mode_t link_mode,
+	__out			uint16_t *capp)
+{
+	switch (link_mode) {
+	case EFX_LINK_1000FDX:
+		*capp = EFX_PHY_CAP_1000FDX;
+		break;
+	case EFX_LINK_10000FDX:
+		*capp = EFX_PHY_CAP_10000FDX;
+		break;
+	case EFX_LINK_40000FDX:
+		*capp = EFX_PHY_CAP_40000FDX;
+		break;
+	case EFX_LINK_25000FDX:
+		*capp = EFX_PHY_CAP_25000FDX;
+		break;
+	case EFX_LINK_50000FDX:
+		*capp = EFX_PHY_CAP_50000FDX;
+		break;
+	case EFX_LINK_100000FDX:
+		*capp = EFX_PHY_CAP_100000FDX;
+		break;
+	case EFX_LINK_200000FDX:
+		*capp = EFX_PHY_CAP_200000FDX;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	return (0);
+}
+
+static					void
+efx_np_cap_enum_sw_to_hw(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__in				uint16_t enum_sw,
+	__out				boolean_t *supportedp,
+	__out_opt			uint16_t *enum_hwp)
+{
+	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
+	    hw_cap_data, hw_cap_data_nbytes) {
+		if (hw_sw_map->encm_sw != enum_sw)
+			continue;
+
+		if (enum_hwp != NULL)
+			*enum_hwp = hw_sw_map->encm_hw;
+
+		*supportedp = B_TRUE;
+		return;
+	}
+
+	*supportedp = B_FALSE;
+}
+
+/*
+ * Convert the given EFX PHY capability enum value to the HW counterpart,
+ * provided that the capability is supported by the HW, where the latter
+ * is detected from the given fraction of raw HW netport capability data.
+ *
+ * As the mapping of a capability from EFX to HW can be one to many, use
+ * the first supported HW capability bit, in accordance with the HW data.
+ */
+#define	EFX_NP_CAP_ENUM_SW_TO_HW(						\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
+	    _enum_sw, _supportedp, _enum_hwp)				\
+	efx_np_cap_enum_sw_to_hw((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN, (_enum_sw),			\
+	    (_supportedp), (_enum_hwp))
+
+static				void
+efx_np_assign_loopback_props(
+	__in			efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+	efx_qword_t lbm_off;
+	efx_qword_t lbm_sup;
+	unsigned int i;
+
+	EFX_ZERO_QWORD(lbm_off);
+	EFX_SET_QWORD_BIT(lbm_off, EFX_LOOPBACK_OFF);
+
+	/*
+	 * Netport MCDI capable NICs support loopback modes which are
+	 * generalisations of the existing modes that specify roughly
+	 * where in the processing chain the loopback occurs, without
+	 * the need to refer to the specific technology. Provide some
+	 * to users under the guise of older technology-specific ones.
+	 *
+	 * FIXME: correct this if need be and augment with more modes.
+	 */
+	EFX_ZERO_QWORD(lbm_sup);
+	EFX_SET_QWORD_BIT(lbm_sup, EFX_LOOPBACK_OFF);
+
+	if (EFX_TEST_QWORD_BIT(epp->ep_np_loopback_cap_mask,
+			    MC_CMD_LOOPBACK_V2_AUTO))
+		EFX_SET_QWORD_BIT(lbm_sup, EFX_LOOPBACK_DATA);
+
+	if (EFX_TEST_QWORD_BIT(epp->ep_np_loopback_cap_mask,
+			    MC_CMD_LOOPBACK_V2_POST_PCS))
+		EFX_SET_QWORD_BIT(lbm_sup, EFX_LOOPBACK_PCS);
+
+	for (i = 0; i < EFX_ARRAY_SIZE(encp->enc_loopback_types); ++i) {
+		boolean_t supported = B_FALSE;
+		uint16_t cap_enum_sw;
+		efx_rc_t rc;
+
+		rc = efx_np_sw_link_mode_to_cap(i, &cap_enum_sw);
+		if (rc != 0) {
+			/* No support for this link mode => no loopbacks. */
+			encp->enc_loopback_types[i] = lbm_off;
+			continue;
+		}
+
+		EFX_NP_CAP_ENUM_SW_TO_HW(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, epp->ep_np_cap_data_raw,
+		    cap_enum_sw, &supported, NULL);
+
+		if (supported != B_FALSE)
+			encp->enc_loopback_types[i] = lbm_sup;
+		else
+			encp->enc_loopback_types[i] = lbm_off;
+	}
+}
+#endif /* EFSYS_OPT_LOOPBACK */
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
@@ -367,7 +516,8 @@ efx_np_attach(
 	 * don't necessarily have access to these details.
 	 */
 	rc = efx_np_get_fixed_port_props(enp, epp->ep_np_handle,
-		    &epp->ep_phy_cap_mask);
+		    epp->ep_np_cap_data_raw, &epp->ep_phy_cap_mask,
+		    &epp->ep_np_loopback_cap_mask);
 	if (rc != 0)
 		goto fail2;
 
@@ -379,6 +529,11 @@ efx_np_attach(
 		epp->ep_phy_cap_mask |= 1U << EFX_PHY_CAP_AN;
 
 	epp->ep_adv_cap_mask = ls.enls_adv_cap_mask;
+
+#if EFSYS_OPT_LOOPBACK
+	efx_np_assign_loopback_props(enp);
+#endif /* EFSYS_OPT_LOOPBACK */
+
 	return (0);
 
 fail3:
-- 
2.39.5

[PATCH 27/46] common/sfc_efx/base: introduce Medford4 stub for PHY methods

[Ivan Malov]

Provide only a couple of no-op methods for now. Next patches
will augment the file with more, based on newer netport MCDI.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      |  4 +++
 drivers/common/sfc_efx/base/efx_phy.c       | 22 +++++++++++++++-
 drivers/common/sfc_efx/base/medford4_impl.h | 29 +++++++++++++++++++++
 drivers/common/sfc_efx/base/medford4_phy.c  | 28 ++++++++++++++++++++
 drivers/common/sfc_efx/base/meson.build     |  1 +
 5 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
 create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 3a9c6fe3fd..16b7f7640d 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -45,6 +45,10 @@
 #include "rhead_impl.h"
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+#include "medford4_impl.h"
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index 3d792f20b8..537865767a 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -68,6 +68,26 @@ static const efx_phy_ops_t	__efx_phy_rhead_ops = {
 };
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+static const efx_phy_ops_t	__efx_phy_medford4_ops = {
+	medford4_phy_power,		/* epo_power */
+	NULL,				/* epo_reset */
+	ef10_phy_reconfigure,		/* epo_reconfigure */
+	medford4_phy_verify,		/* epo_verify */
+	ef10_phy_oui_get,		/* epo_oui_get */
+	ef10_phy_link_state_get,	/* epo_link_state_get */
+#if EFSYS_OPT_PHY_STATS
+	ef10_phy_stats_update,		/* epo_stats_update */
+#endif	/* EFSYS_OPT_PHY_STATS */
+#if EFSYS_OPT_BIST
+	ef10_bist_enable_offline,	/* epo_bist_enable_offline */
+	ef10_bist_start,		/* epo_bist_start */
+	ef10_bist_poll,			/* epo_bist_poll */
+	ef10_bist_stop,			/* epo_bist_stop */
+#endif	/* EFSYS_OPT_BIST */
+};
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	__checkReturn	efx_rc_t
 efx_phy_probe(
 	__in		efx_nic_t *enp)
@@ -116,7 +136,7 @@ efx_phy_probe(
 
 #if EFSYS_OPT_MEDFORD4
 	case EFX_FAMILY_MEDFORD4:
-		epop = &__efx_phy_ef10_ops;
+		epop = &__efx_phy_medford4_ops;
 	break;
 #endif	/* EFSYS_OPT_MEDFORD4 */
 
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
new file mode 100644
index 0000000000..ec8b3cec86
--- /dev/null
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#ifndef	_SYS_MEDFORD4_IMPL_H
+#define	_SYS_MEDFORD4_IMPL_H
+
+#include "efx.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_phy_power(
+	__in		efx_nic_t *enp,
+	__in		boolean_t power);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_phy_verify(
+	__in		efx_nic_t *enp);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MEDFORD4_IMPL_H */
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
new file mode 100644
index 0000000000..3e6080b4de
--- /dev/null
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#include "efx.h"
+#include "efx_impl.h"
+#include "medford4_impl.h"
+
+#if EFSYS_OPT_MEDFORD4
+	__checkReturn	efx_rc_t
+medford4_phy_power(
+	__in		efx_nic_t *enp,
+	__in		boolean_t power)
+{
+	if (power)
+		enp->en_reset_flags |= EFX_RESET_PHY;
+
+	return (0);
+}
+
+	__checkReturn	efx_rc_t
+medford4_phy_verify(
+	__in		efx_nic_t *enp)
+{
+	_NOTE(ARGUNUSED(enp))
+	return (0);
+}
+#endif	/* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build
index 02d5b2fbb9..937e3820a0 100644
--- a/drivers/common/sfc_efx/base/meson.build
+++ b/drivers/common/sfc_efx/base/meson.build
@@ -57,6 +57,7 @@ sources = [
         'hunt_nic.c',
         'medford_nic.c',
         'medford2_nic.c',
+        'medford4_phy.c',
         'rhead_ev.c',
         'rhead_intr.c',
         'rhead_nic.c',
-- 
2.39.5

[PATCH 28/46] common/sfc_efx/base: refactor EF10 link mode decoding helper

[Ivan Malov]

Future patches will use this change for netport MCDI support.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_impl.h | 13 +++++++++++
 drivers/common/sfc_efx/base/ef10_phy.c  | 31 ++++++++++++++++++-------
 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_impl.h b/drivers/common/sfc_efx/base/ef10_impl.h
index 3476f274ce..b872ec626c 100644
--- a/drivers/common/sfc_efx/base/ef10_impl.h
+++ b/drivers/common/sfc_efx/base/ef10_impl.h
@@ -801,6 +801,19 @@ ef10_phy_stats_update(
 
 #endif	/* EFSYS_OPT_PHY_STATS */
 
+LIBEFX_INTERNAL
+extern				void
+mcdi_phy_decode_link_mode(
+	__in			efx_nic_t *enp,
+	__in			boolean_t fd,
+	__in			boolean_t up,
+	__in			unsigned int speed,
+	__in			unsigned int fcntl,
+	__in			uint32_t fec,
+	__out			efx_link_mode_t *link_modep,
+	__out			unsigned int *fcntlp,
+	__out			efx_phy_fec_type_t *fecp);
+
 #if EFSYS_OPT_BIST
 
 LIBEFX_INTERNAL
diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index 49babdecd5..d458199c7a 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -92,10 +92,21 @@ mcdi_phy_decode_cap(
 	*maskp = mask;
 }
 
-static			void
+static				void
+mcdi_phy_decode_link_up_duplex(
+	__in			uint32_t link_flags,
+	__out			boolean_t *fdp,
+	__out			boolean_t *upp)
+{
+	*fdp = !!(link_flags & (1U << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
+	*upp = !!(link_flags & (1U << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
+}
+
+			void
 mcdi_phy_decode_link_mode(
 	__in		efx_nic_t *enp,
-	__in		uint32_t link_flags,
+	__in		boolean_t fd,
+	__in		boolean_t up,
 	__in		unsigned int speed,
 	__in		unsigned int fcntl,
 	__in		uint32_t fec,
@@ -103,11 +114,6 @@ mcdi_phy_decode_link_mode(
 	__out		unsigned int *fcntlp,
 	__out		efx_phy_fec_type_t *fecp)
 {
-	boolean_t fd = !!(link_flags &
-		    (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
-	boolean_t up = !!(link_flags &
-		    (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
-
 	_NOTE(ARGUNUSED(enp))
 
 	if (!up)
@@ -179,6 +185,8 @@ ef10_phy_link_ev(
 	unsigned int ev_fcntl;
 	unsigned int ev_speed;
 	uint32_t lp_cap_mask;
+	boolean_t fd;
+	boolean_t up;
 
 	if (ev_is_v2) {
 		link_flags = (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN);
@@ -226,7 +234,8 @@ ef10_phy_link_ev(
 		break;
 	}
 
-	mcdi_phy_decode_link_mode(enp, link_flags, speed, ev_fcntl,
+	mcdi_phy_decode_link_up_duplex(link_flags, &fd, &up);
+	mcdi_phy_decode_link_mode(enp, fd, up, speed, ev_fcntl,
 				    MC_CMD_FEC_NONE, &link_mode,
 				    &fcntl, &fec);
 	mcdi_phy_decode_cap(ev_lp_cap, &lp_cap_mask);
@@ -281,6 +290,8 @@ ef10_phy_get_link(
 	uint32_t fec;
 	EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,
 		MC_CMD_GET_LINK_OUT_V2_LEN);
+	boolean_t fd;
+	boolean_t up;
 	efx_rc_t rc;
 
 	req.emr_cmd = MC_CMD_GET_LINK;
@@ -311,7 +322,9 @@ ef10_phy_get_link(
 	else
 		fec = MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_FEC_TYPE);
 
-	mcdi_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
+	mcdi_phy_decode_link_up_duplex(MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
+				    &fd, &up);
+	mcdi_phy_decode_link_mode(enp, fd, up,
 			    MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
 			    MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
 			    fec, &elsp->epls.epls_link_mode,
-- 
2.39.5

[PATCH 29/46] common/sfc_efx/base: provide PHY link get method on Medford4

[Ivan Malov]

To do so, make use of new netport MCDI supported by Medford4.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_phy.c      |  8 ++
 drivers/common/sfc_efx/base/efx.h           |  4 +-
 drivers/common/sfc_efx/base/efx_impl.h      | 19 ++++
 drivers/common/sfc_efx/base/efx_np.c        | 98 ++++++++++++++++++++-
 drivers/common/sfc_efx/base/efx_phy.c       |  2 +-
 drivers/common/sfc_efx/base/medford4_impl.h | 12 +++
 drivers/common/sfc_efx/base/medford4_phy.c  | 62 +++++++++++++
 7 files changed, 202 insertions(+), 3 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index d458199c7a..8c3de273b4 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -118,6 +118,8 @@ mcdi_phy_decode_link_mode(
 
 	if (!up)
 		*link_modep = EFX_LINK_DOWN;
+	else if (speed == 200000 && fd)
+		*link_modep = EFX_LINK_200000FDX;
 	else if (speed == 100000 && fd)
 		*link_modep = EFX_LINK_100000FDX;
 	else if (speed == 50000 && fd)
@@ -160,6 +162,12 @@ mcdi_phy_decode_link_mode(
 	case MC_CMD_FEC_RS:
 		*fecp = EFX_PHY_FEC_RS;
 		break;
+	case MC_CMD_FEC_IEEE_RS_INT:
+		*fecp = EFX_PHY_FEC_IEEE_RS_INT;
+		break;
+	case MC_CMD_FEC_ETCS_RS_LL:
+		*fecp = EFX_PHY_FEC_ETCS_RS_LL;
+		break;
 	default:
 		EFSYS_PROBE1(mc_pcol_error, int, fec);
 		*fecp = EFX_PHY_FEC_NONE;
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 7ffa1f4cbd..6ca108cffe 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -4010,7 +4010,9 @@ efx_nic_set_fw_subvariant(
 typedef enum efx_phy_fec_type_e {
 	EFX_PHY_FEC_NONE = 0,
 	EFX_PHY_FEC_BASER,
-	EFX_PHY_FEC_RS
+	EFX_PHY_FEC_RS,
+	EFX_PHY_FEC_IEEE_RS_INT,
+	EFX_PHY_FEC_ETCS_RS_LL,
 } efx_phy_fec_type_t;
 
 #define EFX_PHY_CAP_FEC_BIT(_fec_bit) (1U << EFX_PHY_CAP_##_fec_bit)
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 16b7f7640d..63ff112194 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1907,7 +1907,14 @@ efx_np_detach(
 
 typedef struct efx_np_link_state_s {
 	uint32_t		enls_adv_cap_mask;
+	uint32_t		enls_lp_cap_mask;
+	efx_loopback_type_t	enls_loopback;
+	uint32_t		enls_speed;
+	uint8_t			enls_fec;
+
 	boolean_t		enls_an_supported;
+	boolean_t		enls_fd;
+	boolean_t		enls_up;
 } efx_np_link_state_t;
 
 LIBEFX_INTERNAL
@@ -1917,6 +1924,18 @@ efx_np_link_state(
 	__in		efx_np_handle_t nph,
 	__out		efx_np_link_state_t *lsp);
 
+typedef struct efx_np_mac_state_s {
+	uint32_t	enms_fcntl;
+	boolean_t	enms_up;
+} efx_np_mac_state_t;
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_mac_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_mac_state_t *msp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 2e4cdcf863..1b67fd16aa 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -301,7 +301,9 @@ efx_np_link_state(
 	EFX_MCDI_DECLARE_BUF(payload,
 	    MC_CMD_LINK_STATE_IN_LEN,
 	    MC_CMD_LINK_STATE_OUT_V3_LEN);
+	uint32_t status_flags;
 	efx_mcdi_req_t req;
+	uint32_t v3_flags;
 	efx_rc_t rc;
 
 	req.emr_out_length = MC_CMD_LINK_STATE_OUT_V3_LEN;
@@ -324,12 +326,44 @@ efx_np_link_state(
 		goto fail2;
 	}
 
+	status_flags = MCDI_OUT_DWORD(req, LINK_STATE_OUT_STATUS_FLAGS_LO);
+	v3_flags = MCDI_OUT_DWORD(req, LINK_STATE_OUT_V3_FLAGS);
 	memset(lsp, 0, sizeof (*lsp));
 
-	if (MCDI_OUT_DWORD(req, LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT) !=
+	if (status_flags & (1U << MC_CMD_LINK_STATUS_FLAGS_AN_ABLE) &&
+	    MCDI_OUT_DWORD(req, LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT) !=
 	    MC_CMD_AN_NONE)
 		lsp->enls_an_supported = B_TRUE;
 
+	if (v3_flags & (1U << MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN))
+		lsp->enls_fd = B_TRUE;
+
+	if (status_flags & (1U << MC_CMD_LINK_STATUS_FLAGS_LINK_UP))
+		lsp->enls_up = B_TRUE;
+
+	lsp->enls_speed = MCDI_OUT_DWORD(req, LINK_STATE_OUT_V3_LINK_SPEED);
+	lsp->enls_fec = MCDI_OUT_BYTE(req, LINK_STATE_OUT_FEC_MODE);
+
+#if EFSYS_OPT_LOOPBACK
+	/* FIXME: correct this if need be and augment with more modes. */
+	switch (MCDI_OUT_BYTE(req, LINK_STATE_OUT_LOOPBACK)) {
+	case MC_CMD_LOOPBACK_V2_NONE:
+		lsp->enls_loopback = EFX_LOOPBACK_OFF;
+		break;
+	case MC_CMD_LOOPBACK_V2_AUTO:
+		lsp->enls_loopback = EFX_LOOPBACK_DATA;
+		break;
+	case MC_CMD_LOOPBACK_V2_POST_PCS:
+		lsp->enls_loopback = EFX_LOOPBACK_PCS;
+		break;
+	default:
+		rc = EINVAL;
+		goto fail3;
+	}
+#else /* ! EFSYS_OPT_LOOPBACK */
+	_NOTE(ARGUNUSED(lbp))
+#endif /* EFSYS_OPT_LOOPBACK */
+
 	if (lsp->enls_an_supported != B_FALSE)
 		lsp->enls_adv_cap_mask |= 1U << EFX_PHY_CAP_AN;
 
@@ -337,8 +371,21 @@ efx_np_link_state(
 	    MCDI_OUT2(req, const uint8_t, LINK_STATE_OUT_ADVERTISED_ABILITIES),
 	    &lsp->enls_adv_cap_mask);
 
+	if (lsp->enls_an_supported != B_FALSE)
+		lsp->enls_lp_cap_mask |= 1U << EFX_PHY_CAP_AN;
+
+	efx_np_cap_hw_data_to_sw_mask(
+	    MCDI_OUT2(req, const uint8_t,
+		    LINK_STATE_OUT_LINK_PARTNER_ABILITIES),
+	    &lsp->enls_lp_cap_mask);
+
 	return (0);
 
+#if EFSYS_OPT_LOOPBACK
+fail3:
+	EFSYS_PROBE(fail3);
+#endif /* EFSYS_OPT_LOOPBACK */
+
 fail2:
 	EFSYS_PROBE(fail2);
 
@@ -554,3 +601,52 @@ efx_np_detach(
 	if (efx_np_supported(enp) == B_FALSE)
 		return;
 }
+
+	__checkReturn	efx_rc_t
+efx_np_mac_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_mac_state_t *msp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_MAC_STATE_IN_LEN,
+	    MC_CMD_MAC_STATE_OUT_LEN);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_MAC_STATE_OUT_LEN;
+	req.emr_in_length = MC_CMD_MAC_STATE_IN_LEN;
+	req.emr_cmd = MC_CMD_MAC_STATE;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, MAC_STATE_IN_PORT_HANDLE, nph);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_MAC_STATE_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	memset(msp, 0, sizeof (*msp));
+
+	if (MCDI_OUT_DWORD(req, MAC_STATE_OUT_MAC_FAULT_FLAGS) == 0)
+		msp->enms_up = B_TRUE;
+
+	msp->enms_fcntl = MCDI_OUT_DWORD(req, MAC_STATE_OUT_FCNTL);
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+	return (rc);
+}
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index 537865767a..0f748e32a4 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -75,7 +75,7 @@ static const efx_phy_ops_t	__efx_phy_medford4_ops = {
 	ef10_phy_reconfigure,		/* epo_reconfigure */
 	medford4_phy_verify,		/* epo_verify */
 	ef10_phy_oui_get,		/* epo_oui_get */
-	ef10_phy_link_state_get,	/* epo_link_state_get */
+	medford4_phy_link_state_get,	/* epo_link_state_get */
 #if EFSYS_OPT_PHY_STATS
 	ef10_phy_stats_update,		/* epo_stats_update */
 #endif	/* EFSYS_OPT_PHY_STATS */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index ec8b3cec86..f24c9d1e6c 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -22,6 +22,18 @@ extern	__checkReturn	efx_rc_t
 medford4_phy_verify(
 	__in		efx_nic_t *enp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_phy_get_link(
+	__in		efx_nic_t *enp,
+	__out		ef10_link_state_t *elsp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_phy_link_state_get(
+	__in			efx_nic_t *enp,
+	__out			efx_phy_link_state_t *eplsp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
index 3e6080b4de..6a61645384 100644
--- a/drivers/common/sfc_efx/base/medford4_phy.c
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -25,4 +25,66 @@ medford4_phy_verify(
 	_NOTE(ARGUNUSED(enp))
 	return (0);
 }
+
+	__checkReturn	efx_rc_t
+medford4_phy_get_link(
+	__in		efx_nic_t *enp,
+	__out		ef10_link_state_t *elsp)
+{
+	efx_np_handle_t nph = enp->en_port.ep_np_handle;
+	efx_np_link_state_t ls;
+	efx_np_mac_state_t ms;
+	uint32_t fcntl;
+	efx_rc_t rc;
+
+	rc = efx_np_link_state(enp, nph, &ls);
+	if (rc != 0)
+		goto fail1;
+
+	elsp->epls.epls_adv_cap_mask = ls.enls_adv_cap_mask;
+	elsp->epls.epls_lp_cap_mask = ls.enls_lp_cap_mask;
+	elsp->els_loopback = ls.enls_loopback;
+
+	rc = efx_np_mac_state(enp, nph, &ms);
+	if (rc != 0)
+		goto fail2;
+
+	elsp->els_mac_up = ms.enms_up;
+
+	mcdi_phy_decode_link_mode(enp, ls.enls_fd, ls.enls_up, ls.enls_speed,
+			    ms.enms_fcntl, ls.enls_fec,
+			    &elsp->epls.epls_link_mode,
+			    &elsp->epls.epls_fcntl,
+			    &elsp->epls.epls_fec);
+
+	elsp->epls.epls_ld_cap_mask = 0;
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_phy_link_state_get(
+	__in			efx_nic_t *enp,
+	__out			efx_phy_link_state_t *eplsp)
+{
+	ef10_link_state_t els;
+	efx_rc_t rc;
+
+	rc = medford4_phy_get_link(enp, &els);
+	if (rc != 0)
+		goto fail1;
+
+	*eplsp = els.epls;
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
 #endif	/* EFSYS_OPT_MEDFORD4 */
-- 
2.39.5

[PATCH 30/46] common/sfc_efx/base: implement PHY link control for Medford4

[Ivan Malov]

Use new MCDI to select loopback, speed, flow control and FEC.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_impl.h     |   6 +
 drivers/common/sfc_efx/base/ef10_phy.c      |   2 +-
 drivers/common/sfc_efx/base/efx_impl.h      |  11 +
 drivers/common/sfc_efx/base/efx_np.c        | 277 ++++++++++++++++++++
 drivers/common/sfc_efx/base/efx_phy.c       |   2 +-
 drivers/common/sfc_efx/base/medford4_impl.h |   5 +
 drivers/common/sfc_efx/base/medford4_phy.c  |  65 +++++
 7 files changed, 366 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_impl.h b/drivers/common/sfc_efx/base/ef10_impl.h
index b872ec626c..df4fd77833 100644
--- a/drivers/common/sfc_efx/base/ef10_impl.h
+++ b/drivers/common/sfc_efx/base/ef10_impl.h
@@ -814,6 +814,12 @@ mcdi_phy_decode_link_mode(
 	__out			unsigned int *fcntlp,
 	__out			efx_phy_fec_type_t *fecp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_mcdi_phy_set_led(
+	__in		efx_nic_t *enp,
+	__in		efx_phy_led_mode_t phy_led_mode);
+
 #if EFSYS_OPT_BIST
 
 LIBEFX_INTERNAL
diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index 8c3de273b4..114543e156 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -473,7 +473,7 @@ efx_mcdi_phy_set_link(
 	return (rc);
 }
 
-static	__checkReturn	efx_rc_t
+	__checkReturn	efx_rc_t
 efx_mcdi_phy_set_led(
 	__in		efx_nic_t *enp,
 	__in		efx_phy_led_mode_t phy_led_mode)
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 63ff112194..15cf62506e 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1936,6 +1936,17 @@ efx_np_mac_state(
 	__in		efx_np_handle_t nph,
 	__out		efx_np_mac_state_t *msp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_link_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const uint8_t *cap_mask_sup_raw,
+	__in		efx_link_mode_t loopback_link_mode,
+	__in		efx_loopback_type_t loopback_mode,
+	__in		uint32_t cap_mask_sw,
+	__in		boolean_t fcntl_an);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 1b67fd16aa..03d49b9c78 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -650,3 +650,280 @@ efx_np_mac_state(
 
 	return (rc);
 }
+
+static					void
+efx_np_cap_mask_sw_to_hw(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__in				uint32_t mask_sw,
+	__out				uint8_t *mask_hwp)
+{
+	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
+	    hw_cap_data, hw_cap_data_nbytes) {
+		uint32_t flag_sw = 1U << hw_sw_map->encm_sw;
+
+		if ((mask_sw & flag_sw) != flag_sw)
+			continue;
+
+		mask_hwp[CAP_BYTE(hw_sw_map)] |= CAP_FLAG(hw_sw_map);
+		mask_sw &= ~(flag_sw);
+	}
+}
+
+/*
+ * Convert the given EFX PHY capability mask to the HW representation.
+ *
+ * The mapping of a capability from EFX to HW can be one to many. Use
+ * the given fraction of raw HW netport capability data to choose the
+ * first supported HW capability bit encountered for a particular EFX
+ * one and proceed with handling the next EFX bit, if any, afterwards.
+ *
+ * Do not check the input mask for leftover bits (unknown to EFX), as
+ * inputs should have been validated by efx_phy_adv_cap_set() already.
+ */
+#define	EFX_NP_CAP_MASK_SW_TO_HW(					\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
+	    _mask_sw, _mask_hwp)					\
+	efx_np_cap_mask_sw_to_hw((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN,				\
+	    (_mask_sw), (_mask_hwp))
+
+static					void
+efx_np_cap_sw_mask_to_hw_enum(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__in				uint32_t mask_sw,
+	__out				boolean_t *supportedp,
+	__out_opt			uint16_t *enum_hwp)
+{
+	unsigned int sw_nflags_req = 0;
+	unsigned int sw_nflags_sup = 0;
+	uint32_t sw_check_mask = 0;
+	unsigned int i;
+
+	for (i = 0; i < hw_sw_map_nentries; ++i) {
+		uint32_t flag_sw = 1U << hw_sw_map->encm_sw;
+		unsigned int byte_idx = CAP_BYTE(hw_sw_map);
+		uint8_t flag_hw = CAP_FLAG(hw_sw_map);
+
+		if (byte_idx >= hw_cap_data_nbytes) {
+			++(hw_sw_map);
+			continue;
+		}
+
+		if ((mask_sw & flag_sw) == flag_sw) {
+			if ((sw_check_mask & flag_sw) == 0)
+				++(sw_nflags_req);
+
+			sw_check_mask |= flag_sw;
+
+			if ((hw_cap_data[byte_idx] & flag_hw) == flag_hw) {
+				mask_sw &= ~(flag_sw);
+
+				if (enum_hwp != NULL)
+					*enum_hwp = hw_sw_map->encm_hw;
+			}
+		}
+
+		++(hw_sw_map);
+	}
+
+	/*
+	 * FIXME: in the absence of autonegotiation capability, drivers
+	 * may still pass multiple capability bits of the same category.
+	 * That is supposed to work on EF10; do not enforce below check.
+	 */
+#if 0
+	if (sw_nflags_req != 1) {
+		/*
+		 * The mask must contain exactly one relevant
+		 * flag which represents some specific choice.
+		 */
+		*supportedp = B_FALSE;
+		return;
+	}
+#endif
+
+	if (sw_check_mask != 0 && (mask_sw & sw_check_mask) == sw_check_mask) {
+		/* Failed to select the enum by at least one capability bit. */
+		*supportedp = B_FALSE;
+		return;
+	}
+
+	*supportedp = B_TRUE;
+}
+
+/*
+ * Convert (conceivably) the only EFX capability bit of the given mask to
+ * the HW enum value, provided that the capability is supported by the HW,
+ * where the latter follows from the given fraction of HW capability data.
+ */
+#define	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(					\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
+	    _mask_sw, _supportedp, _enum_hwp)				\
+	efx_np_cap_sw_mask_to_hw_enum((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN, (_mask_sw),			\
+	    (_supportedp), (_enum_hwp))
+
+	__checkReturn	efx_rc_t
+efx_np_link_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const uint8_t *cap_data_raw,
+	__in		efx_link_mode_t loopback_link_mode,
+	__in		efx_loopback_type_t loopback_mode,
+	__in		uint32_t cap_mask_sw,
+	__in		boolean_t fcntl_an)
+{
+	uint32_t flags = 1U << MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ;
+	uint8_t loopback = MC_CMD_LOOPBACK_V2_NONE;
+	uint16_t link_tech = MC_CMD_ETH_TECH_NONE;
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_LINK_CTRL_IN_LEN,
+	    MC_CMD_LINK_CTRL_OUT_LEN);
+	uint8_t *cap_mask_hw_pausep;
+	uint8_t *cap_mask_hw_techp;
+	uint16_t cap_enum_hw;
+	boolean_t supported;
+	efx_mcdi_req_t req;
+	boolean_t phy_an;
+	efx_rc_t rc;
+	uint8_t fec;
+
+	req.emr_out_length = MC_CMD_LINK_CTRL_OUT_LEN;
+	req.emr_in_length = MC_CMD_LINK_CTRL_IN_LEN;
+	req.emr_cmd = MC_CMD_LINK_CTRL;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, LINK_CTRL_IN_PORT_HANDLE, nph);
+
+	cap_mask_hw_pausep = MCDI_IN2(req, uint8_t,
+	    LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK);
+
+	cap_mask_hw_techp = MCDI_IN2(req, uint8_t,
+	    LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK);
+
+	/* FIXME: correct this if need be and augment with more modes. */
+	if (loopback_mode != EFX_LOOPBACK_OFF) {
+#if EFSYS_OPT_LOOPBACK
+		uint16_t cap_enum_sw;
+
+		switch (loopback_mode) {
+		case EFX_LOOPBACK_DATA:
+			loopback = MC_CMD_LOOPBACK_V2_AUTO;
+			break;
+		case EFX_LOOPBACK_PCS:
+			loopback = MC_CMD_LOOPBACK_V2_POST_PCS;
+			break;
+		default:
+			rc = ENOTSUP;
+			goto fail1;
+		}
+
+		rc = efx_np_sw_link_mode_to_cap(loopback_link_mode,
+					    &cap_enum_sw);
+		if (rc != 0)
+			goto fail2;
+
+		EFX_NP_CAP_ENUM_SW_TO_HW(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_enum_sw,
+		    &supported, &link_tech);
+
+		if (supported == B_FALSE) {
+			rc = ENOTSUP;
+			goto fail3;
+		}
+#else /* ! EFSYS_OPT_LOOPBACK */
+		rc = ENOTSUP;
+		goto fail1;
+#endif /* EFSYS_OPT_LOOPBACK */
+	} else if (cap_mask_sw & (1U << EFX_PHY_CAP_AN)) {
+		EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    cap_mask_hw_techp);
+
+		if (fcntl_an != B_FALSE) {
+			EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_pause,
+			    ETH_AN_FIELDS_PAUSE_MASK, cap_data_raw, cap_mask_sw,
+			    cap_mask_hw_pausep);
+		}
+
+		flags |= 1U << MC_CMD_LINK_FLAGS_AUTONEG_EN;
+		link_tech = MC_CMD_ETH_TECH_AUTO;
+	} else {
+		EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    &supported, &link_tech);
+
+		if (supported == B_FALSE) {
+			rc = ENOTSUP;
+			goto fail4;
+		}
+	}
+
+	/* The software mask may have no requested FEC bits. Default is NONE. */
+	cap_enum_hw = MC_CMD_FEC_NONE;
+
+	/*
+	 * Compared to older EF10 interface, in netport MCDI, FEC mode is a
+	 * single enum choice. For compatibility, do not enforce only single
+	 * requested FEC bit in the original mask.
+	 *
+	 * No requested FEC bits in the original mask gives supported=TRUE.
+	 */
+	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_fec_req,
+	    ETH_AN_FIELDS_FEC_REQ, cap_data_raw, cap_mask_sw,
+	    &supported, &cap_enum_hw);
+
+	if ((cap_mask_sw & EFX_PHY_CAP_FEC_MASK) != 0 && supported == B_FALSE) {
+		rc = ENOTSUP;
+		goto fail5;
+	}
+
+	EFSYS_ASSERT(cap_enum_hw <= UINT8_MAX);
+	fec = cap_enum_hw;
+
+	MCDI_IN_SET_WORD(req, LINK_CTRL_IN_LINK_TECHNOLOGY, link_tech);
+	MCDI_IN_SET_DWORD(req, LINK_CTRL_IN_CONTROL_FLAGS, flags);
+	MCDI_IN_SET_BYTE(req, LINK_CTRL_IN_LOOPBACK, loopback);
+	MCDI_IN_SET_BYTE(req, LINK_CTRL_IN_FEC_MODE, fec);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail6;
+	}
+
+	return (0);
+
+fail6:
+	EFSYS_PROBE(fail6);
+
+fail5:
+	EFSYS_PROBE(fail5);
+
+fail4:
+	EFSYS_PROBE(fail4);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index 0f748e32a4..e3b9d20d59 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -72,7 +72,7 @@ static const efx_phy_ops_t	__efx_phy_rhead_ops = {
 static const efx_phy_ops_t	__efx_phy_medford4_ops = {
 	medford4_phy_power,		/* epo_power */
 	NULL,				/* epo_reset */
-	ef10_phy_reconfigure,		/* epo_reconfigure */
+	medford4_phy_reconfigure,	/* epo_reconfigure */
 	medford4_phy_verify,		/* epo_verify */
 	ef10_phy_oui_get,		/* epo_oui_get */
 	medford4_phy_link_state_get,	/* epo_link_state_get */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index f24c9d1e6c..795fd45bd4 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -34,6 +34,11 @@ medford4_phy_link_state_get(
 	__in			efx_nic_t *enp,
 	__out			efx_phy_link_state_t *eplsp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_phy_reconfigure(
+	__in			efx_nic_t *enp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
index 6a61645384..cc4e77587b 100644
--- a/drivers/common/sfc_efx/base/medford4_phy.c
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -83,6 +83,71 @@ medford4_phy_link_state_get(
 	*eplsp = els.epls;
 	return (0);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_phy_reconfigure(
+	__in			efx_nic_t *enp)
+{
+	efx_link_mode_t loopback_link_mode;
+	efx_port_t *epp = &(enp->en_port);
+	efx_loopback_type_t loopback;
+	efx_phy_led_mode_t led;
+	boolean_t supported;
+	efx_rc_t rc;
+
+	rc = efx_mcdi_link_control_supported(enp, &supported);
+	if (rc != 0)
+		goto fail1;
+
+	if (supported == B_FALSE)
+		goto exit;
+
+#if EFSYS_OPT_LOOPBACK
+	loopback_link_mode = epp->ep_loopback_link_mode;
+	loopback = epp->ep_loopback_type;
+#else /* ! EFSYS_OPT_LOOPBACK */
+	loopback_link_mode = EFX_LINK_UNKNOWN;
+	loopback = EFX_LOOPBACK_OFF;
+#endif /* EFSYS_OPT_LOOPBACK */
+
+	rc = efx_np_link_ctrl(enp, epp->ep_np_handle, epp->ep_np_cap_data_raw,
+		    loopback_link_mode, loopback, epp->ep_adv_cap_mask,
+		    epp->ep_fcntl_autoneg);
+	if (rc != 0)
+		goto fail2;
+
+#if EFSYS_OPT_PHY_LED_CONTROL
+	led = epp->ep_phy_led_mode;
+#else /* ! EFSYS_OPT_PHY_LED_CONTROL */
+	led = EFX_PHY_LED_DEFAULT;
+#endif /* EFSYS_OPT_PHY_LED_CONTROL */
+
+	rc = efx_mcdi_phy_set_led(enp, led);
+	if (rc != 0) {
+		/*
+		 * If LED control is not supported by firmware, we can
+		 * silently ignore default mode set failure
+		 * (see FWRIVERHD-198).
+		 */
+		if (rc == EOPNOTSUPP && led == EFX_PHY_LED_DEFAULT)
+			goto exit;
+
+		goto fail3;
+	}
+
+exit:
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
-- 
2.39.5

Re: [PATCH 30/46] common/sfc_efx/base: implement PHY link control for Medford4

[Andrew Rybchenko]

On 4/16/25 17:00, Ivan Malov wrote:
> Use new MCDI to select loopback, speed, flow control and FEC.
> 
> Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>
> Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>

[snip]

> +static					void
> +efx_np_cap_sw_mask_to_hw_enum(
> +	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
> +	__in				unsigned int hw_sw_map_nentries,
> +	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
> +	__in				size_t hw_cap_data_nbytes,
> +	__in				uint32_t mask_sw,
> +	__out				boolean_t *supportedp,
> +	__out_opt			uint16_t *enum_hwp)
> +{
> +	unsigned int sw_nflags_req = 0;
> +	unsigned int sw_nflags_sup = 0;
> +	uint32_t sw_check_mask = 0;
> +	unsigned int i;
> +
> +	for (i = 0; i < hw_sw_map_nentries; ++i) {
> +		uint32_t flag_sw = 1U << hw_sw_map->encm_sw;
> +		unsigned int byte_idx = CAP_BYTE(hw_sw_map);
> +		uint8_t flag_hw = CAP_FLAG(hw_sw_map);
> +
> +		if (byte_idx >= hw_cap_data_nbytes) {
> +			++(hw_sw_map);
> +			continue;
> +		}
> +
> +		if ((mask_sw & flag_sw) == flag_sw) {
> +			if ((sw_check_mask & flag_sw) == 0)
> +				++(sw_nflags_req);
> +
> +			sw_check_mask |= flag_sw;
> +
> +			if ((hw_cap_data[byte_idx] & flag_hw) == flag_hw) {
> +				mask_sw &= ~(flag_sw);
> +
> +				if (enum_hwp != NULL)
> +					*enum_hwp = hw_sw_map->encm_hw;
> +			}
> +		}
> +
> +		++(hw_sw_map);
> +	}
> +
> +	/*
> +	 * FIXME: in the absence of autonegotiation capability, drivers
> +	 * may still pass multiple capability bits of the same category.
> +	 * That is supposed to work on EF10; do not enforce below check.
> +	 */
> +#if 0

It looks rather strange when code with #if 0 comes.

> +	if (sw_nflags_req != 1) {
> +		/*
> +		 * The mask must contain exactly one relevant
> +		 * flag which represents some specific choice.
> +		 */
> +		*supportedp = B_FALSE;
> +		return;
> +	}
> +#endif
> +
> +	if (sw_check_mask != 0 && (mask_sw & sw_check_mask) == sw_check_mask) {
> +		/* Failed to select the enum by at least one capability bit. */
> +		*supportedp = B_FALSE;
> +		return;
> +	}
> +
> +	*supportedp = B_TRUE;
> +}

[snip]

[PATCH 31/46] common/sfc_efx/base: introduce Medford4 stub for MAC methods

[Ivan Malov]

Provide only a small subset of methods for now. Next patches
will augment the file with more, based on newer netport MCDI.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_mac.c       | 32 +++++++++++-
 drivers/common/sfc_efx/base/medford4_impl.h | 12 +++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 54 +++++++++++++++++++++
 drivers/common/sfc_efx/base/meson.build     |  1 +
 4 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c

diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index a2cbf02b46..dde0e5ab87 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -89,6 +89,31 @@ static const efx_mac_ops_t	__efx_mac_rhead_ops = {
 };
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+static const efx_mac_ops_t	__efx_mac_medford4_ops = {
+	medford4_mac_poll,			/* emo_poll */
+	medford4_mac_up,			/* emo_up */
+	ef10_mac_addr_set,			/* emo_addr_set */
+	ef10_mac_pdu_set,			/* emo_pdu_set */
+	ef10_mac_pdu_get,			/* emo_pdu_get */
+	ef10_mac_reconfigure,			/* emo_reconfigure */
+	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
+	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
+	ef10_mac_filter_default_rxq_clear,
+					/* emo_filter_default_rxq_clear */
+#if EFSYS_OPT_LOOPBACK
+	ef10_mac_loopback_set,			/* emo_loopback_set */
+#endif	/* EFSYS_OPT_LOOPBACK */
+#if EFSYS_OPT_MAC_STATS
+	ef10_mac_stats_get_mask,		/* emo_stats_get_mask */
+	efx_mcdi_mac_stats_clear,		/* emo_stats_clear */
+	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
+	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
+	ef10_mac_stats_update			/* emo_stats_update */
+#endif	/* EFSYS_OPT_MAC_STATS */
+};
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	__checkReturn			efx_rc_t
 efx_mac_pdu_set(
 	__in				efx_nic_t *enp,
@@ -271,6 +296,11 @@ efx_mac_drain(
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 	EFSYS_ASSERT(emop != NULL);
 
+	if (efx_np_supported(enp) != B_FALSE) {
+		/* Only pre-Medford4 boards have supported MAC drain control. */
+		return (0);
+	}
+
 	if (epp->ep_mac_drain == enabled)
 		return (0);
 
@@ -955,7 +985,7 @@ efx_mac_select(
 
 #if EFSYS_OPT_MEDFORD4
 	case EFX_FAMILY_MEDFORD4:
-		emop = &__efx_mac_ef10_ops;
+		emop = &__efx_mac_medford4_ops;
 		type = EFX_MAC_MEDFORD4;
 		break;
 #endif /* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 795fd45bd4..6aa065c730 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -39,6 +39,18 @@ extern	__checkReturn		efx_rc_t
 medford4_phy_reconfigure(
 	__in			efx_nic_t *enp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_poll(
+	__in		efx_nic_t *enp,
+	__out		efx_link_mode_t *link_modep);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_up(
+	__in		efx_nic_t *enp,
+	__out		boolean_t *mac_upp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
new file mode 100644
index 0000000000..57ddbecfaa
--- /dev/null
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#include "efx.h"
+#include "efx_impl.h"
+#include "medford4_impl.h"
+
+#if EFSYS_OPT_MEDFORD4
+	__checkReturn	efx_rc_t
+medford4_mac_poll(
+	__in		efx_nic_t *enp,
+	__out		efx_link_mode_t *link_modep)
+{
+	efx_port_t *epp = &(enp->en_port);
+	ef10_link_state_t els;
+	efx_rc_t rc;
+
+	rc = medford4_phy_get_link(enp, &els);
+	if (rc != 0)
+		goto fail1;
+
+	epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
+	epp->ep_fcntl = els.epls.epls_fcntl;
+
+	*link_modep = els.epls.epls_link_mode;
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	*link_modep = EFX_LINK_UNKNOWN;
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+medford4_mac_up(
+	__in		efx_nic_t *enp,
+	__out		boolean_t *mac_upp)
+{
+	ef10_link_state_t els;
+	efx_rc_t rc;
+
+	rc = medford4_phy_get_link(enp, &els);
+	if (rc != 0)
+		goto fail1;
+
+	*mac_upp = els.els_mac_up;
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build
index 937e3820a0..f18011e186 100644
--- a/drivers/common/sfc_efx/base/meson.build
+++ b/drivers/common/sfc_efx/base/meson.build
@@ -57,6 +57,7 @@ sources = [
         'hunt_nic.c',
         'medford_nic.c',
         'medford2_nic.c',
+        'medford4_mac.c',
         'medford4_phy.c',
         'rhead_ev.c',
         'rhead_intr.c',
-- 
2.39.5

[PATCH 32/46] common/sfc_efx/base: add MAC reconfigure method for Medford4

[Ivan Malov]

That leverages MAC control functionality of new netport MCDI.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      | 13 ++++
 drivers/common/sfc_efx/base/efx_mac.c       |  2 +-
 drivers/common/sfc_efx/base/efx_np.c        | 73 +++++++++++++++++++++
 drivers/common/sfc_efx/base/medford4_impl.h |  5 ++
 drivers/common/sfc_efx/base/medford4_mac.c  | 32 +++++++++
 5 files changed, 124 insertions(+), 1 deletion(-)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 15cf62506e..ac1cd5292b 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1947,6 +1947,19 @@ efx_np_link_ctrl(
 	__in		uint32_t cap_mask_sw,
 	__in		boolean_t fcntl_an);
 
+typedef struct efx_np_mac_ctrl_s {
+	boolean_t	enmc_fcntl_autoneg;
+	boolean_t	enmc_include_fcs;
+	uint32_t	enmc_fcntl;
+} efx_np_mac_ctrl_t;
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_mac_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const efx_np_mac_ctrl_t *mc);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index dde0e5ab87..3c29db0016 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -96,7 +96,7 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 	ef10_mac_addr_set,			/* emo_addr_set */
 	ef10_mac_pdu_set,			/* emo_pdu_set */
 	ef10_mac_pdu_get,			/* emo_pdu_get */
-	ef10_mac_reconfigure,			/* emo_reconfigure */
+	medford4_mac_reconfigure,		/* emo_reconfigure */
 	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
 	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
 	ef10_mac_filter_default_rxq_clear,
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 03d49b9c78..826ee93f0f 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -923,6 +923,79 @@ efx_np_link_ctrl(
 fail2:
 	EFSYS_PROBE(fail2);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+efx_np_mac_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const efx_np_mac_ctrl_t *mc)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_MAC_CTRL_IN_LEN,
+	    MC_CMD_MAC_CTRL_OUT_LEN);
+	efx_mcdi_req_t req;
+	uint32_t flags = 0;
+	uint32_t cfg = 0;
+	uint32_t fcntl;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_MAC_CTRL_OUT_LEN;
+	req.emr_in_length = MC_CMD_MAC_CTRL_IN_LEN;
+	req.emr_cmd = MC_CMD_MAC_CTRL;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_PORT_HANDLE, nph);
+
+	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS;
+	if (mc->enmc_include_fcs != B_FALSE)
+		flags |= 1U << MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS;
+
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FLAGS, flags);
+
+	if (mc->enmc_fcntl_autoneg != B_FALSE) {
+		fcntl = MC_CMD_FCNTL_AUTO;
+	} else {
+		switch (mc->enmc_fcntl) {
+		case 0:
+			fcntl = MC_CMD_FCNTL_OFF;
+			break;
+		case EFX_FCNTL_RESPOND:
+			fcntl = MC_CMD_FCNTL_RESPOND;
+			break;
+		case EFX_FCNTL_GENERATE:
+			fcntl = MC_CMD_FCNTL_GENERATE;
+			break;
+		case EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE:
+			fcntl = MC_CMD_FCNTL_BIDIR;
+			break;
+		default:
+			rc = EINVAL;
+			goto fail1;
+		}
+	}
+
+	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL;
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FCNTL, fcntl);
+
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_V2_CONTROL_FLAGS, cfg);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail2;
+	}
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 6aa065c730..8b232c516a 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -51,6 +51,11 @@ medford4_mac_up(
 	__in		efx_nic_t *enp,
 	__out		boolean_t *mac_upp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_reconfigure(
+	__in			efx_nic_t *enp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index 57ddbecfaa..c037c29b92 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -47,6 +47,38 @@ medford4_mac_up(
 	*mac_upp = els.els_mac_up;
 	return (0);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_mac_reconfigure(
+	__in			efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_np_mac_ctrl_t mc = {0};
+	efx_rc_t rc;
+
+	mc.enmc_fcntl_autoneg = epp->ep_fcntl_autoneg;
+	mc.enmc_include_fcs = epp->ep_include_fcs;
+	mc.enmc_fcntl = epp->ep_fcntl;
+
+	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
+	if (rc != 0)
+		goto fail1;
+
+	/*
+	 * Apply the filters for the MAC configuration. If the NIC isn't ready
+	 * to accept filters, this may return success without setting anything.
+	 */
+	rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
+				    epp->ep_all_unicst, epp->ep_mulcst,
+				    epp->ep_all_mulcst, epp->ep_brdcst,
+				    epp->ep_mulcst_addr_list,
+				    epp->ep_mulcst_addr_count);
+	return (0);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
-- 
2.39.5

Re: [PATCH 32/46] common/sfc_efx/base: add MAC reconfigure method for Medford4

[Andrew Rybchenko]

On 4/16/25 17:00, Ivan Malov wrote:
> That leverages MAC control functionality of new netport MCDI.
> 
> Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>
> Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
> ---
>   drivers/common/sfc_efx/base/efx_impl.h      | 13 ++++
>   drivers/common/sfc_efx/base/efx_mac.c       |  2 +-
>   drivers/common/sfc_efx/base/efx_np.c        | 73 +++++++++++++++++++++
>   drivers/common/sfc_efx/base/medford4_impl.h |  5 ++
>   drivers/common/sfc_efx/base/medford4_mac.c  | 32 +++++++++
>   5 files changed, 124 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
> index 15cf62506e..ac1cd5292b 100644
> --- a/drivers/common/sfc_efx/base/efx_impl.h
> +++ b/drivers/common/sfc_efx/base/efx_impl.h
> @@ -1947,6 +1947,19 @@ efx_np_link_ctrl(
>   	__in		uint32_t cap_mask_sw,
>   	__in		boolean_t fcntl_an);
>   
> +typedef struct efx_np_mac_ctrl_s {
> +	boolean_t	enmc_fcntl_autoneg;
> +	boolean_t	enmc_include_fcs;
> +	uint32_t	enmc_fcntl;
> +} efx_np_mac_ctrl_t;
> +
> +LIBEFX_INTERNAL
> +extern	__checkReturn	efx_rc_t
> +efx_np_mac_ctrl(
> +	__in		efx_nic_t *enp,
> +	__in		efx_np_handle_t nph,
> +	__in		const efx_np_mac_ctrl_t *mc);
> +
>   #ifdef	__cplusplus
>   }
>   #endif
> diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
> index dde0e5ab87..3c29db0016 100644
> --- a/drivers/common/sfc_efx/base/efx_mac.c
> +++ b/drivers/common/sfc_efx/base/efx_mac.c
> @@ -96,7 +96,7 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
>   	ef10_mac_addr_set,			/* emo_addr_set */
>   	ef10_mac_pdu_set,			/* emo_pdu_set */
>   	ef10_mac_pdu_get,			/* emo_pdu_get */
> -	ef10_mac_reconfigure,			/* emo_reconfigure */
> +	medford4_mac_reconfigure,		/* emo_reconfigure */
>   	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
>   	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
>   	ef10_mac_filter_default_rxq_clear,
> diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
> index 03d49b9c78..826ee93f0f 100644
> --- a/drivers/common/sfc_efx/base/efx_np.c
> +++ b/drivers/common/sfc_efx/base/efx_np.c
> @@ -923,6 +923,79 @@ efx_np_link_ctrl(
>   fail2:
>   	EFSYS_PROBE(fail2);
>   
> +fail1:
> +	EFSYS_PROBE1(fail1, efx_rc_t, rc);
> +	return (rc);
> +}
> +
> +	__checkReturn	efx_rc_t
> +efx_np_mac_ctrl(
> +	__in		efx_nic_t *enp,
> +	__in		efx_np_handle_t nph,
> +	__in		const efx_np_mac_ctrl_t *mc)
> +{
> +	EFX_MCDI_DECLARE_BUF(payload,
> +	    MC_CMD_MAC_CTRL_IN_LEN,
> +	    MC_CMD_MAC_CTRL_OUT_LEN);
> +	efx_mcdi_req_t req;
> +	uint32_t flags = 0;
> +	uint32_t cfg = 0;
> +	uint32_t fcntl;
> +	efx_rc_t rc;
> +
> +	req.emr_out_length = MC_CMD_MAC_CTRL_OUT_LEN;
> +	req.emr_in_length = MC_CMD_MAC_CTRL_IN_LEN;
> +	req.emr_cmd = MC_CMD_MAC_CTRL;
> +	req.emr_out_buf = payload;
> +	req.emr_in_buf = payload;
> +
> +	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_PORT_HANDLE, nph);
> +
> +	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS;
> +	if (mc->enmc_include_fcs != B_FALSE)
> +		flags |= 1U << MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS;
> +
> +	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FLAGS, flags);
> +
> +	if (mc->enmc_fcntl_autoneg != B_FALSE) {
> +		fcntl = MC_CMD_FCNTL_AUTO;
> +	} else {
> +		switch (mc->enmc_fcntl) {
> +		case 0:
> +			fcntl = MC_CMD_FCNTL_OFF;
> +			break;
> +		case EFX_FCNTL_RESPOND:
> +			fcntl = MC_CMD_FCNTL_RESPOND;
> +			break;
> +		case EFX_FCNTL_GENERATE:
> +			fcntl = MC_CMD_FCNTL_GENERATE;
> +			break;
> +		case EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE:
> +			fcntl = MC_CMD_FCNTL_BIDIR;
> +			break;
> +		default:
> +			rc = EINVAL;
> +			goto fail1;
> +		}
> +	}
> +
> +	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL;
> +	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FCNTL, fcntl);
> +
> +	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_V2_CONTROL_FLAGS, cfg);
> +
> +	efx_mcdi_execute(enp, &req);
> +
> +	if (req.emr_rc != 0) {
> +		rc = req.emr_rc;
> +		goto fail2;
> +	}
> +
> +	return (0);
> +
> +fail2:
> +	EFSYS_PROBE(fail2);
> +
>   fail1:
>   	EFSYS_PROBE1(fail1, efx_rc_t, rc);
>   	return (rc);
> diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
> index 6aa065c730..8b232c516a 100644
> --- a/drivers/common/sfc_efx/base/medford4_impl.h
> +++ b/drivers/common/sfc_efx/base/medford4_impl.h
> @@ -51,6 +51,11 @@ medford4_mac_up(
>   	__in		efx_nic_t *enp,
>   	__out		boolean_t *mac_upp);
>   
> +LIBEFX_INTERNAL
> +extern	__checkReturn		efx_rc_t
> +medford4_mac_reconfigure(
> +	__in			efx_nic_t *enp);
> +
>   #ifdef	__cplusplus
>   }
>   #endif
> diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
> index 57ddbecfaa..c037c29b92 100644
> --- a/drivers/common/sfc_efx/base/medford4_mac.c
> +++ b/drivers/common/sfc_efx/base/medford4_mac.c
> @@ -47,6 +47,38 @@ medford4_mac_up(
>   	*mac_upp = els.els_mac_up;
>   	return (0);
>   
> +fail1:
> +	EFSYS_PROBE1(fail1, efx_rc_t, rc);
> +	return (rc);
> +}
> +
> +	__checkReturn		efx_rc_t
> +medford4_mac_reconfigure(
> +	__in			efx_nic_t *enp)
> +{
> +	efx_port_t *epp = &(enp->en_port);
> +	efx_np_mac_ctrl_t mc = {0};
> +	efx_rc_t rc;
> +
> +	mc.enmc_fcntl_autoneg = epp->ep_fcntl_autoneg;
> +	mc.enmc_include_fcs = epp->ep_include_fcs;
> +	mc.enmc_fcntl = epp->ep_fcntl;
> +
> +	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
> +	if (rc != 0)
> +		goto fail1;
> +
> +	/*
> +	 * Apply the filters for the MAC configuration. If the NIC isn't ready
> +	 * to accept filters, this may return success without setting anything.
> +	 */
> +	rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
> +				    epp->ep_all_unicst, epp->ep_mulcst,
> +				    epp->ep_all_mulcst, epp->ep_brdcst,
> +				    epp->ep_mulcst_addr_list,
> +				    epp->ep_mulcst_addr_count);

I'm sorry, but above comments are insufficient for me to understand why
ignoring rc is OK and it looks like a bug.

> +	return (0);
> +
>   fail1:
>   	EFSYS_PROBE1(fail1, efx_rc_t, rc);
>   	return (rc);

[PATCH 33/46] common/sfc_efx/base: fill in software LUT for MAC statistics

[Ivan Malov]

To support MAC statistics, it is required to fill in a table
which will be used by EFX to get DMA field IDs (offsets into
the DMA buffer where MC FW uploads the data) by software IDs.

Fill in the lookup table by parsing HW statistic descriptors.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h |   8 +
 drivers/common/sfc_efx/base/efx_np.c   | 291 +++++++++++++++++++++++++
 2 files changed, 299 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index ac1cd5292b..aafb2bf998 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -341,6 +341,12 @@ typedef struct efx_virtio_ops_s {
 
 typedef uint32_t efx_np_handle_t;
 
+typedef struct efx_np_stat_s {
+	uint32_t	ens_hw_id;
+	uint16_t	ens_dma_fld;
+	boolean_t	ens_valid;
+} efx_np_stat_t;
+
 typedef struct efx_port_s {
 	efx_mac_type_t		ep_mac_type;
 	uint32_t		ep_phy_type;
@@ -388,6 +394,8 @@ typedef struct efx_port_s {
 	efx_np_handle_t		ep_np_handle;
 	efx_qword_t		ep_np_loopback_cap_mask;
 	uint8_t			ep_np_cap_data_raw[MC_CMD_ETH_AN_FIELDS_LEN];
+	/* Lookup table providing DMA buffer field IDs by EFX statistic IDs. */
+	efx_np_stat_t		ep_np_mac_stat_lut[EFX_MAC_NSTATS];
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 826ee93f0f..d4ee17ffb4 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -529,6 +529,286 @@ efx_np_assign_loopback_props(
 }
 #endif /* EFSYS_OPT_LOOPBACK */
 
+#if EFSYS_OPT_MAC_STATS
+/* HW statistic IDs, as per MC_CMD_MAC_STATISTICS_DESCRIPTOR format. */
+#define	EFX_NP_HW_STAT_ID(_src, _idx)					\
+	(((MC_CMD_STAT_ID_##_src) << MC_CMD_STAT_ID_SOURCE_ID_LBN) |	\
+	    ((uint32_t)(MC_CMD_STAT_ID_##_idx) <<			\
+		    MC_CMD_STAT_ID_MAC_STAT_ID_LBN))
+
+/*
+ * Mapping between EFX statistic IDs (array indices) and their HW counterparts.
+ *
+ * This is used in conjunction with HW statistic descriptors bearing DMA field
+ * IDs (offsets into the DMA buffer) to provide a SW lookup table for readings.
+ *
+ * From the HW perspective, statistics come from MAC and PHY, hence two macros.
+ */
+static const efx_np_stat_t efx_np_mac_stat_map[] = {
+#define	EFX_NP_STAT_MAC(_hw, _sw)				\
+	[EFX_MAC_##_sw] = {					\
+		.ens_hw_id = EFX_NP_HW_STAT_ID(MAC, _hw),	\
+		.ens_valid = B_TRUE,				\
+	}
+
+	EFX_NP_STAT_MAC(TX_PKTS, TX_PKTS),
+	EFX_NP_STAT_MAC(TX_PAUSE_PKTS, TX_PAUSE_PKTS),
+	/* TODO: TX_CONTROL_PKTS */
+	EFX_NP_STAT_MAC(TX_UNICAST_PKTS, TX_UNICST_PKTS),
+	EFX_NP_STAT_MAC(TX_MULTICAST_PKTS, TX_MULTICST_PKTS),
+	EFX_NP_STAT_MAC(TX_BROADCAST_PKTS, TX_BRDCST_PKTS),
+	EFX_NP_STAT_MAC(TX_BYTES, TX_OCTETS),
+	/* FIXME: TX_64_PKTS; TODO: TX_BAD_BYTES, TX_GOOD_BYTES, TX_LT64_PKTS */
+	EFX_NP_STAT_MAC(TX_64_PKTS, TX_LE_64_PKTS),
+	EFX_NP_STAT_MAC(TX_65_TO_127_PKTS, TX_65_TO_127_PKTS),
+	EFX_NP_STAT_MAC(TX_128_TO_255_PKTS, TX_128_TO_255_PKTS),
+	EFX_NP_STAT_MAC(TX_256_TO_511_PKTS, TX_256_TO_511_PKTS),
+	EFX_NP_STAT_MAC(TX_512_TO_1023_PKTS, TX_512_TO_1023_PKTS),
+	EFX_NP_STAT_MAC(TX_1024_TO_15XX_PKTS, TX_1024_TO_15XX_PKTS),
+	/* FIXME: TX_15XX_TO_JUMBO_PKTS; TODO: TX_GTJUMBO_PKTS */
+	EFX_NP_STAT_MAC(TX_15XX_TO_JUMBO_PKTS, TX_GE_15XX_PKTS),
+	/* TODO: TX_BAD_FCS_PKTS, TX_GOOD_FCS_PKTS */
+	EFX_NP_STAT_MAC(RX_PKTS, RX_PKTS),
+	EFX_NP_STAT_MAC(RX_PAUSE_PKTS, RX_PAUSE_PKTS),
+	/* TODO: RX_GOOD_PKTS, RX_BAD_PKTS, RX_CONTROL_PKTS */
+	EFX_NP_STAT_MAC(RX_UNICAST_PKTS, RX_UNICST_PKTS),
+	EFX_NP_STAT_MAC(RX_MULTICAST_PKTS, RX_MULTICST_PKTS),
+	EFX_NP_STAT_MAC(RX_BROADCAST_PKTS, RX_BRDCST_PKTS),
+	EFX_NP_STAT_MAC(RX_BYTES, RX_OCTETS),
+	/* TODO: RX_BAD_BYTES, RX_GOOD_BYTES */
+	/* FIXME: RX_64_PKTS; TODO: RX_UNDERSIZE_PKTS */
+	EFX_NP_STAT_MAC(RX_64_PKTS, RX_LE_64_PKTS),
+	EFX_NP_STAT_MAC(RX_65_TO_127_PKTS, RX_65_TO_127_PKTS),
+	EFX_NP_STAT_MAC(RX_128_TO_255_PKTS, RX_128_TO_255_PKTS),
+	EFX_NP_STAT_MAC(RX_256_TO_511_PKTS, RX_256_TO_511_PKTS),
+	EFX_NP_STAT_MAC(RX_512_TO_1023_PKTS, RX_512_TO_1023_PKTS),
+	EFX_NP_STAT_MAC(RX_1024_TO_15XX_PKTS, RX_1024_TO_15XX_PKTS),
+	/* FIXME: RX_15XX_TO_JUMBO_PKTS; TODO: RX_GTJUMBO_PKTS */
+	EFX_NP_STAT_MAC(RX_15XX_TO_JUMBO_PKTS, RX_GE_15XX_PKTS),
+	EFX_NP_STAT_MAC(RX_BAD_FCS_PKTS, RX_FCS_ERRORS),
+	/* TODO: RX_GOOD_FCS_PKTS, RX_OVERFLOW_PKTS */
+	EFX_NP_STAT_MAC(RX_SYMBOL_ERROR_PKTS, RX_SYMBOL_ERRORS),
+	EFX_NP_STAT_MAC(RX_ALIGN_ERROR_PKTS, RX_ALIGN_ERRORS),
+	/* TODO: RX_LENGTH_ERROR_PKTS */
+	EFX_NP_STAT_MAC(RX_INTERNAL_ERROR_PKTS, RX_INTERNAL_ERRORS),
+	EFX_NP_STAT_MAC(RX_JABBER_PKTS, RX_JABBER_PKTS),
+	EFX_NP_STAT_MAC(RX_NODESC_DROPS, RX_NODESC_DROP_CNT),
+	/* TODO: RX_LANES01_CHAR_ERR, RX_LANES23_CHAR_ERR */
+	/* TODO: RX_LANES01_DISP_ERR, RX_LANES23_DISP_ERR */
+	EFX_NP_STAT_MAC(RX_MATCH_FAULT, RX_MATCH_FAULT),
+
+#undef EFX_NP_STAT_MAC
+
+#define	EFX_NP_STAT_PHY(_hw, _sw)				\
+	[EFX_MAC_##_sw] = {					\
+		.ens_hw_id = EFX_NP_HW_STAT_ID(PHY, _hw),	\
+		.ens_valid = B_TRUE,				\
+	}
+
+	EFX_NP_STAT_PHY(FEC_UNCORRECTED_ERRORS, FEC_UNCORRECTED_ERRORS),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_ERRORS, FEC_CORRECTED_ERRORS),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE0,
+	    FEC_CORRECTED_SYMBOLS_LANE0),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE1,
+	    FEC_CORRECTED_SYMBOLS_LANE1),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE2,
+	    FEC_CORRECTED_SYMBOLS_LANE2),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE3,
+	    FEC_CORRECTED_SYMBOLS_LANE3),
+
+#undef EFX_NP_STAT_PHY
+};
+#undef EFX_NP_HW_STAT_ID
+
+/* See efx_np_stats_describe() below. */
+static					void
+efx_np_stat_describe(
+	__in				uint8_t *hw_entry_buf,
+	__in				unsigned int lut_nentries,
+	__out_ecount_opt(lut_nentries)	efx_np_stat_t *lut)
+{
+	const efx_np_stat_t *map;
+	efx_mac_stat_t sw_id;
+	uint32_t hw_id;
+
+	hw_id = MCDI_STRUCT_DWORD(hw_entry_buf, MC_CMD_STAT_DESC_STAT_ID);
+
+	for (sw_id = 0; sw_id < EFX_ARRAY_SIZE(efx_np_mac_stat_map); ++sw_id) {
+		map = &efx_np_mac_stat_map[sw_id];
+
+		if (map->ens_valid != B_FALSE && map->ens_hw_id == hw_id)
+			goto found;
+	}
+
+	/* The statistic is unknown to EFX. */
+	return;
+
+found:
+	if (sw_id >= lut_nentries) {
+		/*
+		 * Static mapping size and the size of lookup
+		 * table are out-of-sync. Should never happen.
+		 */
+		return;
+	}
+
+	lut[sw_id].ens_dma_fld =
+	    MCDI_STRUCT_WORD(hw_entry_buf, MC_CMD_STAT_DESC_STAT_INDEX);
+	lut[sw_id].ens_valid = B_TRUE;
+	lut[sw_id].ens_hw_id = hw_id;
+}
+
+/*
+ * Get a fraction of statistic descriptors from the running FW, starting from
+ * the given HW ID offset, and fill DMA buffer field IDs in the corresponding
+ * entries of the software lookup table that will be used to get the readings.
+ */
+static	__checkReturn			efx_rc_t
+efx_np_stats_describe(
+	__in				efx_nic_t *enp,
+	__in				efx_np_handle_t nph,
+	__in				uint32_t req_ofst,
+	__in				unsigned int lut_nentries,
+	__out_ecount_opt(lut_nentries)	efx_np_stat_t *lut,
+	__out_opt			uint32_t *nprocessedp,
+	__out_opt			uint32_t *nstats_maxp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN,
+	    MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2);
+	efx_port_t *epp = &(enp->en_port);
+	uint32_t nprocessed;
+	efx_mcdi_req_t req;
+	uint8_t *entries;
+	uint32_t stride;
+	unsigned int i;
+	size_t out_sz;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2;
+	req.emr_in_length = MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN;
+	req.emr_cmd = MC_CMD_MAC_STATISTICS_DESCRIPTOR;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE, nph);
+	MCDI_IN_SET_DWORD(req, MAC_STATISTICS_DESCRIPTOR_IN_OFFSET, req_ofst);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	out_sz = req.emr_out_length_used;
+	if (out_sz < MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMIN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (nstats_maxp != NULL) {
+		*nstats_maxp = MCDI_OUT_DWORD(req,
+		    MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE) /
+		    sizeof (efx_qword_t);
+	}
+
+	if (lut_nentries == 0 || lut == NULL || nprocessedp == NULL)
+		return (0);
+
+	stride = MCDI_OUT_DWORD(req, MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE);
+	nprocessed = MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(out_sz);
+	if (nprocessed == 0) {
+		rc = EMSGSIZE;
+		goto fail3;
+	}
+
+	entries = MCDI_OUT2(req, uint8_t,
+	    MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES);
+
+	for (i = 0; i < nprocessed; ++i)
+		efx_np_stat_describe(entries + i * stride, lut_nentries, lut);
+
+	*nprocessedp = nprocessed;
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+static	__checkReturn	efx_rc_t
+efx_np_stats_assign(
+	__in		efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+	unsigned int lut_nentries;
+	uint32_t nprocessed = 0;
+	efx_mac_stat_t sw_id;
+	efx_rc_t rc;
+
+	memset(epp->ep_np_mac_stat_lut, 0, sizeof (epp->ep_np_mac_stat_lut));
+	lut_nentries = EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut);
+
+	/*
+	 * First get encp->enc_mac_stats_nstats from the firmware.
+	 *
+	 * Do not limit encp->enc_mac_stats_nstats by the size of
+	 * epp->ep_np_mac_stat_lut, because the former is used to
+	 * allocate DMA buffer by client drivers, which must have
+	 * its size match expectations of the running MC firmware.
+	 */
+	rc = efx_np_stats_describe(enp, epp->ep_np_handle, 0, 0, NULL,
+			    NULL, &encp->enc_mac_stats_nstats);
+	if (rc != 0)
+		goto fail1;
+
+	/* Then process the actual descriptor data. */
+	while (nprocessed < encp->enc_mac_stats_nstats) {
+		uint32_t batch;
+
+		rc = efx_np_stats_describe(enp, epp->ep_np_handle, nprocessed,
+		    lut_nentries, epp->ep_np_mac_stat_lut, &batch, NULL);
+		if (rc != 0)
+			goto fail2;
+
+		nprocessed += batch;
+
+		if (batch == 0) {
+			/* Failed to supply all descriptors. */
+			rc = EMSGSIZE;
+			goto fail3;
+		}
+	}
+
+	sw_id = EFX_MAC_FEC_UNCORRECTED_ERRORS;
+	if (epp->ep_np_mac_stat_lut[sw_id].ens_valid == B_FALSE)
+		encp->enc_fec_counters = B_FALSE;
+	else
+		encp->enc_fec_counters = B_TRUE;
+
+	encp->enc_hlb_counters = B_FALSE;
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MAC_STATS */
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
@@ -581,8 +861,19 @@ efx_np_attach(
 	efx_np_assign_loopback_props(enp);
 #endif /* EFSYS_OPT_LOOPBACK */
 
+#if EFSYS_OPT_MAC_STATS
+	rc = efx_np_stats_assign(enp);
+	if (rc != 0)
+		goto fail4;
+#endif /* EFSYS_OPT_MAC_STATS */
+
 	return (0);
 
+#if EFSYS_OPT_MAC_STATS
+fail4:
+	EFSYS_PROBE(fail4);
+#endif /* EFSYS_OPT_MAC_STATS */
+
 fail3:
 	EFSYS_PROBE(fail3);
 
-- 
2.39.5

[PATCH 34/46] common/sfc_efx/base: fill in MAC statistics mask on Medford4

[Ivan Malov]

Let client drivers know which MAC statistics can be accessed.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_mac.c       |  2 +-
 drivers/common/sfc_efx/base/medford4_impl.h |  9 ++++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 31 +++++++++++++++++++++
 3 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 3c29db0016..6abe2046e8 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -105,7 +105,7 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 	ef10_mac_loopback_set,			/* emo_loopback_set */
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_MAC_STATS
-	ef10_mac_stats_get_mask,		/* emo_stats_get_mask */
+	medford4_mac_stats_get_mask,		/* emo_stats_get_mask */
 	efx_mcdi_mac_stats_clear,		/* emo_stats_clear */
 	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
 	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 8b232c516a..2fbf1495d1 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -56,6 +56,15 @@ extern	__checkReturn		efx_rc_t
 medford4_mac_reconfigure(
 	__in			efx_nic_t *enp);
 
+#if EFSYS_OPT_MAC_STATS
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_get_mask(
+	__in			efx_nic_t *enp,
+	__inout_bcount(sz)	uint32_t *maskp,
+	__in			size_t sz);
+#endif /* EFSYS_OPT_MAC_STATS */
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index c037c29b92..b8a5aade16 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -83,4 +83,35 @@ medford4_mac_reconfigure(
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
 }
+
+#if EFSYS_OPT_MAC_STATS
+	__checkReturn		efx_rc_t
+medford4_mac_stats_get_mask(
+	__in			efx_nic_t *enp,
+	__inout_bcount(sz)	uint32_t *maskp,
+	__in			size_t sz)
+{
+	efx_port_t *epp = &(enp->en_port);
+	unsigned int i;
+	efx_rc_t rc;
+
+	for (i = 0; i < EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut); ++i) {
+		const struct efx_mac_stats_range rng[] = { { i, i } };
+
+		if (epp->ep_np_mac_stat_lut[i].ens_valid == B_FALSE)
+			continue;
+
+		rc = efx_mac_stats_mask_add_ranges(maskp, sz, rng, 1);
+		if (rc != 0)
+			goto fail1;
+	}
+
+	/* TODO: care about VADAPTOR statistics */
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MAC_STATS */
 #endif /* EFSYS_OPT_MEDFORD4 */
-- 
2.39.5

[PATCH 35/46] common/sfc_efx/base: support MAC statistics on Medford4 NICs

[Ivan Malov]

Supply Medford4-specific methods to clear, upload and update
MAC statistics, as well as the method to toggle periodic DMA
updates. All of these leverage the same netport MCDI command.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_nic.c      |   4 +-
 drivers/common/sfc_efx/base/efx_impl.h      |  11 ++
 drivers/common/sfc_efx/base/efx_mac.c       |   8 +-
 drivers/common/sfc_efx/base/efx_mcdi.c      |  12 +-
 drivers/common/sfc_efx/base/efx_np.c        |  89 +++++++++++++
 drivers/common/sfc_efx/base/medford4_impl.h |  27 ++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 138 ++++++++++++++++++++
 7 files changed, 282 insertions(+), 7 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index eb1b68b17e..31fcb361f2 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -2523,7 +2523,9 @@ ef10_nic_probe(
 
 #if EFSYS_OPT_MAC_STATS
 	/* Wipe the MAC statistics */
-	if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
+
+	rc = efx_mcdi_mac_stats_clear(enp);
+	if (rc != 0)
 		goto fail6;
 #endif
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index aafb2bf998..7dbad601ff 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1968,6 +1968,17 @@ efx_np_mac_ctrl(
 	__in		efx_np_handle_t nph,
 	__in		const efx_np_mac_ctrl_t *mc);
 
+#if EFSYS_OPT_MAC_STATS
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_mac_stats(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		efx_stats_action_t action,
+	__in_opt	const efsys_mem_t *esmp,
+	__in		uint16_t period_ms);
+#endif /* EFSYS_OPT_MAC_STATS */
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 6abe2046e8..f002cb838e 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -106,10 +106,10 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_MAC_STATS
 	medford4_mac_stats_get_mask,		/* emo_stats_get_mask */
-	efx_mcdi_mac_stats_clear,		/* emo_stats_clear */
-	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
-	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
-	ef10_mac_stats_update			/* emo_stats_update */
+	medford4_mac_stats_clear,		/* emo_stats_clear */
+	medford4_mac_stats_upload,		/* emo_stats_upload */
+	medford4_mac_stats_periodic,		/* emo_stats_periodic */
+	medford4_mac_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MAC_STATS */
 };
 #endif /* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c
index 0bd56dd84d..20051c7da9 100644
--- a/drivers/common/sfc_efx/base/efx_mcdi.c
+++ b/drivers/common/sfc_efx/base/efx_mcdi.c
@@ -2244,10 +2244,18 @@ efx_mcdi_mac_stats(
 efx_mcdi_mac_stats_clear(
 	__in		efx_nic_t *enp)
 {
+	efx_port_t *epp = &(enp->en_port);
 	efx_rc_t rc;
 
-	if ((rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL,
-			EFX_STATS_CLEAR, 0)) != 0)
+	if (efx_np_supported(enp) != B_FALSE) {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_CLEAR, NULL, 0);
+	} else {
+		rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL,
+				EFX_STATS_CLEAR, 0);
+	}
+
+	if (rc != 0)
 		goto fail1;
 
 	return (0);
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index d4ee17ffb4..df836f09a6 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -1291,3 +1291,92 @@ efx_np_mac_ctrl(
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
 }
+
+#if EFSYS_OPT_MAC_STATS
+	__checkReturn	efx_rc_t
+efx_np_mac_stats(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		efx_stats_action_t action,
+	__in_opt	const efsys_mem_t *esmp,
+	__in		uint16_t period_ms)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_GET_NETPORT_STATISTICS_IN_LEN,
+	    MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN);
+	int enable = (action == EFX_STATS_ENABLE_NOEVENTS);
+	int events = (action == EFX_STATS_ENABLE_EVENTS);
+	int disable = (action == EFX_STATS_DISABLE);
+	int upload = (action == EFX_STATS_UPLOAD);
+	int clear = (action == EFX_STATS_CLEAR);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN;
+	req.emr_in_length = MC_CMD_GET_NETPORT_STATISTICS_IN_LEN;
+	req.emr_cmd = MC_CMD_GET_NETPORT_STATISTICS;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_PORT_HANDLE, nph);
+
+	MCDI_IN_POPULATE_DWORD_6(req, GET_NETPORT_STATISTICS_IN_CMD,
+	    GET_NETPORT_STATISTICS_IN_DMA, upload,
+	    GET_NETPORT_STATISTICS_IN_CLEAR, clear,
+	    GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE,
+		    enable | events | disable,
+	    GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE, enable | events,
+	    GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT, !events,
+	    GET_NETPORT_STATISTICS_IN_PERIOD_MS,
+		    (enable | events) ? period_ms : 0);
+
+	if (enable || events || upload) {
+		const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
+		uint32_t sz;
+
+		/* Periodic stats or stats upload require a DMA buffer */
+		if (esmp == NULL) {
+			rc = EINVAL;
+			goto fail1;
+		}
+
+		/* TODO: validate encp->enc_mac_stats_nstats */
+		sz = encp->enc_mac_stats_nstats * sizeof (efx_qword_t);
+
+		if (EFSYS_MEM_SIZE(esmp) < sz) {
+			/* DMA buffer too small */
+			rc = ENOSPC;
+			goto fail2;
+		}
+
+		MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO,
+		    EFSYS_MEM_ADDR(esmp) & 0xffffffff);
+		MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI,
+		    EFSYS_MEM_ADDR(esmp) >> 32);
+		MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_DMA_LEN, sz);
+	}
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		/* EF10: Expect ENOENT if no DMA queues are initialised */
+		if ((req.emr_rc != ENOENT) ||
+		    (enp->en_rx_qcount + enp->en_tx_qcount != 0)) {
+			rc = req.emr_rc;
+			goto fail3;
+		}
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MAC_STATS */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 2fbf1495d1..cc45431a81 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -63,6 +63,33 @@ medford4_mac_stats_get_mask(
 	__in			efx_nic_t *enp,
 	__inout_bcount(sz)	uint32_t *maskp,
 	__in			size_t sz);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_clear(
+	__in			efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_upload(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_periodic(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp,
+	__in			uint16_t period_ms,
+	__in			boolean_t events);
+
+LIBEFX_INTERNAL
+extern	__checkReturn			efx_rc_t
+medford4_mac_stats_update(
+	__in				efx_nic_t *enp,
+	__in				efsys_mem_t *esmp,
+	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stats,
+	__inout_opt			uint32_t *generationp);
 #endif /* EFSYS_OPT_MAC_STATS */
 
 #ifdef	__cplusplus
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index b8a5aade16..bc55604017 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -113,5 +113,143 @@ medford4_mac_stats_get_mask(
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
 }
+
+	__checkReturn		efx_rc_t
+medford4_mac_stats_clear(
+	__in			efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
+
+	rc = efx_np_mac_stats(enp, epp->ep_np_handle, EFX_STATS_CLEAR, NULL, 0);
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_mac_stats_upload(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
+
+	rc = efx_np_mac_stats(enp,
+		    epp->ep_np_handle, EFX_STATS_UPLOAD, esmp, 0);
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_mac_stats_periodic(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp,
+	__in			uint16_t period_ms,
+	__in			boolean_t events)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
+
+	if (period_ms == 0) {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_DISABLE, NULL, 0);
+	} else if (events != B_FALSE) {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_ENABLE_EVENTS, esmp, period_ms);
+	} else {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_ENABLE_NOEVENTS, esmp, period_ms);
+	}
+
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+#define	MEDFORD4_MAC_STAT_READ(_esmp, _field, _eqp)			\
+	EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
+
+	__checkReturn			efx_rc_t
+medford4_mac_stats_update(
+	__in				efx_nic_t *enp,
+	__in				efsys_mem_t *esmp,
+	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stats,
+	__inout_opt			uint32_t *generationp)
+{
+	const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
+	efx_port_t *epp = &(enp->en_port);
+	efx_qword_t generation_start;
+	efx_qword_t generation_end;
+	unsigned int i;
+	efx_rc_t rc;
+
+	/* TODO: validate encp->enc_mac_stats_nstats */
+	if (EFSYS_MEM_SIZE(esmp) <
+	    (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
+		/* DMA buffer too small */
+		rc = ENOSPC;
+		goto fail1;
+	}
+
+	/* Read END first so we don't race with the MC */
+	EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
+	MEDFORD4_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
+	    &generation_end);
+	EFSYS_MEM_READ_BARRIER();
+
+	for (i = 0; i < EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut); ++i) {
+		efx_qword_t value;
+
+		if (epp->ep_np_mac_stat_lut[i].ens_valid == B_FALSE)
+			continue;
+
+		MEDFORD4_MAC_STAT_READ(esmp,
+		    epp->ep_np_mac_stat_lut[i].ens_dma_fld, &value);
+
+		EFSYS_STAT_SET_QWORD(&(stats[i]), &value);
+	}
+
+	/* TODO: care about VADAPTOR statistics */
+
+	/* Read START generation counter */
+	EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
+	EFSYS_MEM_READ_BARRIER();
+
+	/* FIXME: we never parse marker descriptors; assume start is 0 offset */
+	MEDFORD4_MAC_STAT_READ(esmp, 0, &generation_start);
+
+	/* Check that we didn't read the stats in the middle of a DMA */
+	if (memcmp(&generation_start, &generation_end,
+		    sizeof (generation_start)) != 0)
+		return (EAGAIN);
+
+	if (generationp != NULL)
+		*generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+#undef MEDFORD4_MAC_STAT_READ
 #endif /* EFSYS_OPT_MAC_STATS */
 #endif /* EFSYS_OPT_MEDFORD4 */
-- 
2.39.5

Re: [PATCH 35/46] common/sfc_efx/base: support MAC statistics on Medford4 NICs

[Andrew Rybchenko]

On 4/16/25 17:00, Ivan Malov wrote:
> Supply Medford4-specific methods to clear, upload and update
> MAC statistics, as well as the method to toggle periodic DMA
> updates. All of these leverage the same netport MCDI command.
> 
> Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>
> Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>

[snip]

> diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
> index eb1b68b17e..31fcb361f2 100644
> --- a/drivers/common/sfc_efx/base/ef10_nic.c
> +++ b/drivers/common/sfc_efx/base/ef10_nic.c
> @@ -2523,7 +2523,9 @@ ef10_nic_probe(
>   
>   #if EFSYS_OPT_MAC_STATS
>   	/* Wipe the MAC statistics */
> -	if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
> +
> +	rc = efx_mcdi_mac_stats_clear(enp);
> +	if (rc != 0)

it looks like unrelated style change.

>   		goto fail6;
>   #endif
>   

[snip]

> diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
> index d4ee17ffb4..df836f09a6 100644
> --- a/drivers/common/sfc_efx/base/efx_np.c
> +++ b/drivers/common/sfc_efx/base/efx_np.c
> @@ -1291,3 +1291,92 @@ efx_np_mac_ctrl(
>   	EFSYS_PROBE1(fail1, efx_rc_t, rc);
>   	return (rc);
>   }
> +
> +#if EFSYS_OPT_MAC_STATS
> +	__checkReturn	efx_rc_t
> +efx_np_mac_stats(
> +	__in		efx_nic_t *enp,
> +	__in		efx_np_handle_t nph,
> +	__in		efx_stats_action_t action,
> +	__in_opt	const efsys_mem_t *esmp,
> +	__in		uint16_t period_ms)
> +{
> +	EFX_MCDI_DECLARE_BUF(payload,
> +	    MC_CMD_GET_NETPORT_STATISTICS_IN_LEN,
> +	    MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN);
> +	int enable = (action == EFX_STATS_ENABLE_NOEVENTS);
> +	int events = (action == EFX_STATS_ENABLE_EVENTS);
> +	int disable = (action == EFX_STATS_DISABLE);
> +	int upload = (action == EFX_STATS_UPLOAD);
> +	int clear = (action == EFX_STATS_CLEAR);

IMHO boolean_t should be used for 5 above variables.

> +	efx_mcdi_req_t req;
> +	efx_rc_t rc;

[snip]

> +
> +		/* TODO: validate encp->enc_mac_stats_nstats */

TODO again. The new code is full of TODO and FIXME. It looks like it has
huge backlog. What's the problem to fix the TODO? Is the driver really
ready?

> +		sz = encp->enc_mac_stats_nstats * sizeof (efx_qword_t);
> +
[snip]

> +	__checkReturn		efx_rc_t
> +medford4_mac_stats_periodic(
> +	__in			efx_nic_t *enp,
> +	__in			efsys_mem_t *esmp,
> +	__in			uint16_t period_ms,
> +	__in			boolean_t events)
> +{
> +	efx_port_t *epp = &(enp->en_port);
> +	efx_rc_t rc;
> +
> +	if (period_ms == 0) {
> +		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
> +			    EFX_STATS_DISABLE, NULL, 0);
> +	} else if (events != B_FALSE) {
> +		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
> +			    EFX_STATS_ENABLE_EVENTS, esmp, period_ms);
> +	} else {
> +		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
> +			    EFX_STATS_ENABLE_NOEVENTS, esmp, period_ms);
> +	}
> +
> +	if (rc != 0)
> +		goto fail1;
> +
> +	return (0);
> +
> +fail1:
> +	EFSYS_PROBE1(fail1, efx_rc_t, rc);
> +	return (rc);
> +}
> +
> +#define	MEDFORD4_MAC_STAT_READ(_esmp, _field, _eqp)			\
> +	EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
> +
> +	__checkReturn			efx_rc_t
> +medford4_mac_stats_update(
> +	__in				efx_nic_t *enp,
> +	__in				efsys_mem_t *esmp,
> +	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stats,
> +	__inout_opt			uint32_t *generationp)
> +{
> +	const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
> +	efx_port_t *epp = &(enp->en_port);
> +	efx_qword_t generation_start;
> +	efx_qword_t generation_end;
> +	unsigned int i;
> +	efx_rc_t rc;
> +
> +	/* TODO: validate encp->enc_mac_stats_nstats */
> +	if (EFSYS_MEM_SIZE(esmp) <
> +	    (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
> +		/* DMA buffer too small */
> +		rc = ENOSPC;
> +		goto fail1;
> +	}
> +
> +	/* Read END first so we don't race with the MC */
> +	EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
> +	MEDFORD4_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
> +	    &generation_end);
> +	EFSYS_MEM_READ_BARRIER();
> +
> +	for (i = 0; i < EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut); ++i) {
> +		efx_qword_t value;
> +
> +		if (epp->ep_np_mac_stat_lut[i].ens_valid == B_FALSE)
> +			continue;
> +
> +		MEDFORD4_MAC_STAT_READ(esmp,
> +		    epp->ep_np_mac_stat_lut[i].ens_dma_fld, &value);
> +
> +		EFSYS_STAT_SET_QWORD(&(stats[i]), &value);
> +	}
> +
> +	/* TODO: care about VADAPTOR statistics */

TODO again

> +
> +	/* Read START generation counter */
> +	EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
> +	EFSYS_MEM_READ_BARRIER();
> +
> +	/* FIXME: we never parse marker descriptors; assume start is 0 offset */

FIXME again

> +	MEDFORD4_MAC_STAT_READ(esmp, 0, &generation_start);
> +
> +	/* Check that we didn't read the stats in the middle of a DMA */
> +	if (memcmp(&generation_start, &generation_end,
> +		    sizeof (generation_start)) != 0)
> +		return (EAGAIN);
> +
> +	if (generationp != NULL)
> +		*generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
> +
> +	return (0);
> +
> +fail1:
> +	EFSYS_PROBE1(fail1, efx_rc_t, rc);
> +	return (rc);
> +}
> +
> +#undef MEDFORD4_MAC_STAT_READ
>   #endif /* EFSYS_OPT_MAC_STATS */
>   #endif /* EFSYS_OPT_MEDFORD4 */

[PATCH 36/46] common/sfc_efx/base: implement MAC PDU controls for Medford4

[Ivan Malov]

Leverage new netport MCDI to implement support for such APIs.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      |  4 ++
 drivers/common/sfc_efx/base/efx_mac.c       |  4 +-
 drivers/common/sfc_efx/base/efx_np.c        | 17 ++++++++
 drivers/common/sfc_efx/base/medford4_impl.h | 11 ++++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 44 +++++++++++++++++++++
 5 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 7dbad601ff..43964ccdba 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1934,6 +1934,7 @@ efx_np_link_state(
 
 typedef struct efx_np_mac_state_s {
 	uint32_t	enms_fcntl;
+	uint32_t	enms_pdu;
 	boolean_t	enms_up;
 } efx_np_mac_state_t;
 
@@ -1956,9 +1957,12 @@ efx_np_link_ctrl(
 	__in		boolean_t fcntl_an);
 
 typedef struct efx_np_mac_ctrl_s {
+	boolean_t	enmc_set_pdu_only;
+
 	boolean_t	enmc_fcntl_autoneg;
 	boolean_t	enmc_include_fcs;
 	uint32_t	enmc_fcntl;
+	uint32_t	enmc_pdu;
 } efx_np_mac_ctrl_t;
 
 LIBEFX_INTERNAL
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index f002cb838e..8712d7c5ef 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -94,8 +94,8 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 	medford4_mac_poll,			/* emo_poll */
 	medford4_mac_up,			/* emo_up */
 	ef10_mac_addr_set,			/* emo_addr_set */
-	ef10_mac_pdu_set,			/* emo_pdu_set */
-	ef10_mac_pdu_get,			/* emo_pdu_get */
+	medford4_mac_pdu_set,			/* emo_pdu_set */
+	medford4_mac_pdu_get,			/* emo_pdu_get */
 	medford4_mac_reconfigure,		/* emo_reconfigure */
 	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
 	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index df836f09a6..88e13f0df9 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -816,6 +816,7 @@ efx_np_attach(
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
 	efx_np_link_state_t ls;
+	efx_np_mac_state_t ms;
 	efx_rc_t rc;
 
 	if (efx_np_supported(enp) == B_FALSE)
@@ -867,8 +868,16 @@ efx_np_attach(
 		goto fail4;
 #endif /* EFSYS_OPT_MAC_STATS */
 
+	rc = efx_np_mac_state(enp, epp->ep_np_handle, &ms);
+	if (rc != 0)
+		goto fail5;
+
+	epp->ep_mac_pdu = ms.enms_pdu;
 	return (0);
 
+fail5:
+	EFSYS_PROBE(fail5);
+
 #if EFSYS_OPT_MAC_STATS
 fail4:
 	EFSYS_PROBE(fail4);
@@ -930,6 +939,7 @@ efx_np_mac_state(
 	if (MCDI_OUT_DWORD(req, MAC_STATE_OUT_MAC_FAULT_FLAGS) == 0)
 		msp->enms_up = B_TRUE;
 
+	msp->enms_pdu = MCDI_OUT_DWORD(req, MAC_STATE_OUT_MAX_FRAME_LEN);
 	msp->enms_fcntl = MCDI_OUT_DWORD(req, MAC_STATE_OUT_FCNTL);
 	return (0);
 
@@ -1242,6 +1252,12 @@ efx_np_mac_ctrl(
 
 	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_PORT_HANDLE, nph);
 
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_MAX_FRAME_LEN, mc->enmc_pdu);
+	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN;
+
+	if (mc->enmc_set_pdu_only != B_FALSE)
+		goto skip_full_reconfigure;
+
 	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS;
 	if (mc->enmc_include_fcs != B_FALSE)
 		flags |= 1U << MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS;
@@ -1273,6 +1289,7 @@ efx_np_mac_ctrl(
 	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL;
 	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FCNTL, fcntl);
 
+skip_full_reconfigure:
 	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_V2_CONTROL_FLAGS, cfg);
 
 	efx_mcdi_execute(enp, &req);
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index cc45431a81..b9be5e4e82 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -51,6 +51,17 @@ medford4_mac_up(
 	__in		efx_nic_t *enp,
 	__out		boolean_t *mac_upp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_pdu_set(
+	__in		efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_pdu_get(
+	__in		efx_nic_t *enp,
+	__out		size_t *pdup);
+
 LIBEFX_INTERNAL
 extern	__checkReturn		efx_rc_t
 medford4_mac_reconfigure(
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index bc55604017..1390752e1e 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -47,6 +47,49 @@ medford4_mac_up(
 	*mac_upp = els.els_mac_up;
 	return (0);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+medford4_mac_pdu_set(
+	__in		efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_np_mac_ctrl_t mc = {0};
+	efx_rc_t rc;
+
+	mc.enmc_set_pdu_only = B_TRUE;
+	mc.enmc_pdu = epp->ep_mac_pdu;
+
+	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+medford4_mac_pdu_get(
+	__in		efx_nic_t *enp,
+	__out		size_t *pdup)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_np_mac_state_t ms;
+	efx_rc_t rc;
+
+	rc = efx_np_mac_state(enp, epp->ep_np_handle, &ms);
+	if (rc != 0)
+		goto fail1;
+
+	*pdup = ms.enms_pdu;
+	return (0);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
@@ -63,6 +106,7 @@ medford4_mac_reconfigure(
 	mc.enmc_fcntl_autoneg = epp->ep_fcntl_autoneg;
 	mc.enmc_include_fcs = epp->ep_include_fcs;
 	mc.enmc_fcntl = epp->ep_fcntl;
+	mc.enmc_pdu = epp->ep_mac_pdu;
 
 	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
 	if (rc != 0)
-- 
2.39.5

[PATCH 37/46] common/sfc_efx/base: correct MAC PDU calculation on Medford4

[Ivan Malov]

For managing MAC PDU (max. frame size), client drivers apply
EFX macros to switch between PDU and SDU forms. These macros
include a workaround for a bug that dates back to Siena NICs.

Starting with Medford4, the bug is no longer there and it is
wrong to use the macros, so provide users with a replacement.
The new APIs will either include the said workaround or omit
it, depending on whether support for netport MCDI is present.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx.h         | 25 +++++++++++++++++++++++
 drivers/common/sfc_efx/base/efx_mac.c     | 19 +++++++++++++++--
 drivers/common/sfc_efx/base/efx_nic.c     |  3 +++
 drivers/common/sfc_efx/sfc_base_symbols.c |  1 +
 4 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 6ca108cffe..73dc38f84e 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -668,24 +668,45 @@ typedef enum efx_link_mode_e {
 
 #define	EFX_MAC_SDU_MAX	9202
 
+/*
+ * NOTE: the PDU macros implement an obsolete workaround that is needed for
+ * MC_CMD_SET_MAC; do not use the PDU macros for the netport MCDI commands,
+ * which do not use the workaround.
+ */
+
 #define	EFX_MAC_PDU_ADJUSTMENT					\
 	(/* EtherII */ 14					\
 	    + /* VLAN */ 4					\
 	    + /* CRC */ 4					\
 	    + /* bug16011 */ 16)				\
 
+/* NOTE: this macro is deprecated; use efx_mac_pdu_from_sdu(). */
 #define	EFX_MAC_PDU(_sdu)					\
 	EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
 
 /*
  * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
  * the SDU rounded up slightly.
+ *
+ * NOTE: do not use this macro in new code as it is
+ * incorrect for the netport MCDI commands.
  */
 #define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
 
 #define	EFX_MAC_PDU_MIN	60
+
+/* NOTE: this macro is deprecated; use encp->enc_mac_pdu_max. */
 #define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
 
+/*
+ * For use with efx_mac_pdu_set(), convert the given SDU value to its PDU form.
+ */
+LIBEFX_API
+extern			size_t
+efx_mac_pdu_from_sdu(
+	__in		efx_nic_t *enp,
+	__in		size_t sdu);
+
 LIBEFX_API
 extern	__checkReturn	efx_rc_t
 efx_mac_pdu_get(
@@ -1729,6 +1750,10 @@ typedef struct efx_nic_cfg_s {
 	efx_nic_dma_mapping_t	enc_dma_mapping;
 	/* Physical ports shared by PFs */
 	efx_port_usage_t	enc_port_usage;
+	/* Minimum MAC PDU value to use with efx_mac_pdu_set() */
+	uint32_t		enc_mac_pdu_min;
+	/* Maximum MAC PDU value to use with efx_mac_pdu_set() */
+	uint32_t		enc_mac_pdu_max;
 } efx_nic_cfg_t;
 
 #define	EFX_PCI_VF_INVALID 0xffff
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 8712d7c5ef..606164bcf9 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -114,6 +114,20 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 };
 #endif /* EFSYS_OPT_MEDFORD4 */
 
+			size_t
+efx_mac_pdu_from_sdu(
+	__in		efx_nic_t *enp,
+	__in		size_t sdu)
+{
+	if (efx_np_supported(enp) != B_FALSE) {
+		/* PDU size for netport MCDI capable adaptors. */
+		return sdu + 14 /* ETH */ + 4 /* VLAN */ + 4 /* FCS */;
+	} else {
+		/* PDU size for legacy MC_CMD_SET_MAC command. */
+		return EFX_MAC_PDU(sdu);
+	}
+}
+
 	__checkReturn			efx_rc_t
 efx_mac_pdu_set(
 	__in				efx_nic_t *enp,
@@ -121,6 +135,7 @@ efx_mac_pdu_set(
 {
 	efx_port_t *epp = &(enp->en_port);
 	const efx_mac_ops_t *emop = epp->ep_emop;
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	uint32_t old_pdu;
 	efx_rc_t rc;
 
@@ -128,12 +143,12 @@ efx_mac_pdu_set(
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 	EFSYS_ASSERT(emop != NULL);
 
-	if (pdu < EFX_MAC_PDU_MIN) {
+	if (pdu < encp->enc_mac_pdu_min) {
 		rc = EINVAL;
 		goto fail1;
 	}
 
-	if (pdu > EFX_MAC_PDU_MAX) {
+	if (pdu > encp->enc_mac_pdu_max) {
 		rc = EINVAL;
 		goto fail2;
 	}
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 1ec684da40..1c25270792 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -491,6 +491,9 @@ efx_nic_probe(
 
 	encp->enc_features = enp->en_features;
 
+	encp->enc_mac_pdu_max = efx_mac_pdu_from_sdu(enp, EFX_MAC_SDU_MAX);
+	encp->enc_mac_pdu_min = EFX_MAC_PDU_MIN;
+
 	if ((rc = efx_phy_probe(enp)) != 0)
 		goto fail2;
 
diff --git a/drivers/common/sfc_efx/sfc_base_symbols.c b/drivers/common/sfc_efx/sfc_base_symbols.c
index ae6605632d..0e74034031 100644
--- a/drivers/common/sfc_efx/sfc_base_symbols.c
+++ b/drivers/common/sfc_efx/sfc_base_symbols.c
@@ -59,6 +59,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_trigger)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_status_line)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_status_message)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_fatal)
+RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_pdu_from_sdu)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_pdu_set)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_pdu_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_addr_set)
-- 
2.39.5

[PATCH 38/46] net/sfc: make use of generic EFX MAC PDU calculation helpers

[Ivan Malov]

To make sure that MAC PDU values do not come with legacy bug
workaround baked in when running on newer Medford4 NICs, use
generic replacement APIs from EFX in place of MAC PDU macros.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc_dp_tx.h   |  3 +++
 drivers/net/sfc/sfc_ef10_tx.c | 13 ++++++++-----
 drivers/net/sfc/sfc_ethdev.c  | 17 ++++++++++-------
 drivers/net/sfc/sfc_port.c    |  2 +-
 drivers/net/sfc/sfc_repr.c    |  7 ++++++-
 drivers/net/sfc/sfc_repr.h    |  1 +
 drivers/net/sfc/sfc_tx.c      |  2 ++
 7 files changed, 31 insertions(+), 14 deletions(-)

diff --git a/drivers/net/sfc/sfc_dp_tx.h b/drivers/net/sfc/sfc_dp_tx.h
index aad3b06595..0baf8c7dd6 100644
--- a/drivers/net/sfc/sfc_dp_tx.h
+++ b/drivers/net/sfc/sfc_dp_tx.h
@@ -84,6 +84,9 @@ struct sfc_dp_tx_qcreate_info {
 
 	/** NIC's DMA mapping information */
 	const struct sfc_nic_dma_info	*nic_dma_info;
+
+	/** Maximum MAC PDU (frame size) */
+	unsigned int		max_pdu;
 };
 
 /**
diff --git a/drivers/net/sfc/sfc_ef10_tx.c b/drivers/net/sfc/sfc_ef10_tx.c
index 116229382b..5543dc495f 100644
--- a/drivers/net/sfc/sfc_ef10_tx.c
+++ b/drivers/net/sfc/sfc_ef10_tx.c
@@ -65,6 +65,7 @@ struct sfc_ef10_txq {
 	unsigned int			max_fill_level;
 	unsigned int			free_thresh;
 	unsigned int			evq_read_ptr;
+	unsigned int			max_pdu;
 	struct sfc_ef10_tx_sw_desc	*sw_ring;
 	efx_qword_t			*txq_hw_ring;
 	volatile void			*doorbell;
@@ -252,7 +253,7 @@ sfc_ef10_tx_qpush(struct sfc_ef10_txq *txq, unsigned int added,
 }
 
 static unsigned int
-sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m)
+sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m, unsigned int max_pdu)
 {
 	unsigned int extra_descs_per_seg;
 	unsigned int extra_descs_per_pkt;
@@ -290,8 +291,7 @@ sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m)
 	 * maximum PDU size.
 	 */
 	extra_descs_per_pkt =
-		(RTE_MIN((unsigned int)EFX_MAC_PDU_MAX,
-			 SFC_MBUF_PKT_LEN_MAX) - 1) /
+		(RTE_MIN(max_pdu, SFC_MBUF_PKT_LEN_MAX) - 1) /
 		SFC_EF10_TX_DMA_DESC_LEN_MAX;
 
 	return m->nb_segs + RTE_MIN(m->nb_segs * extra_descs_per_seg,
@@ -672,7 +672,8 @@ sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 			goto dma_desc_space_update;
 		}
 
-		if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space) {
+		if (sfc_ef10_tx_pkt_descs_max(m_seg, txq->max_pdu) >
+		    dma_desc_space) {
 			if (reap_done)
 				break;
 
@@ -686,7 +687,8 @@ sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 			reap_done = true;
 			dma_desc_space = txq->max_fill_level -
 				(added - txq->completed);
-			if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space)
+			if (sfc_ef10_tx_pkt_descs_max(m_seg, txq->max_pdu) >
+			    dma_desc_space)
 				break;
 		}
 
@@ -986,6 +988,7 @@ sfc_ef10_tx_qcreate(uint16_t port_id, uint16_t queue_id,
 			(info->hw_index << info->vi_window_shift);
 	txq->evq_hw_ring = info->evq_hw_ring;
 	txq->tso_tcp_header_offset_limit = info->tso_tcp_header_offset_limit;
+	txq->max_pdu = info->max_pdu;
 
 	sfc_ef10_tx_info(&txq->dp.dpq, "TxQ doorbell is %p", txq->doorbell);
 
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 05194918f9..bd0061f557 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -90,6 +90,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev);
 	struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev);
 	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 	struct sfc_rss *rss = &sas->rss;
 	struct sfc_mae *mae = &sa->mae;
 
@@ -98,7 +99,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 	dev_info->max_mtu = EFX_MAC_SDU_MAX;
 
-	dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX;
+	dev_info->max_rx_pktlen = encp->enc_mac_pdu_max;
 
 	dev_info->max_vfs = sa->sriov.num_vfs;
 
@@ -1112,23 +1113,24 @@ static int
 sfc_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 {
 	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
-	size_t pdu = EFX_MAC_PDU(mtu);
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
+	size_t pdu = efx_mac_pdu_from_sdu(sa->nic, mtu);
 	size_t old_pdu;
 	int rc;
 
 	sfc_log_init(sa, "mtu=%u", mtu);
 
 	rc = EINVAL;
-	if (pdu < EFX_MAC_PDU_MIN) {
+	if (pdu < encp->enc_mac_pdu_min) {
 		sfc_err(sa, "too small MTU %u (PDU size %u less than min %u)",
 			(unsigned int)mtu, (unsigned int)pdu,
-			EFX_MAC_PDU_MIN);
+			encp->enc_mac_pdu_min);
 		goto fail_inval;
 	}
-	if (pdu > EFX_MAC_PDU_MAX) {
+	if (pdu > encp->enc_mac_pdu_max) {
 		sfc_err(sa, "too big MTU %u (PDU size %u greater than max %u)",
 			(unsigned int)mtu, (unsigned int)pdu,
-			(unsigned int)EFX_MAC_PDU_MAX);
+			encp->enc_mac_pdu_max);
 		goto fail_inval;
 	}
 
@@ -3378,6 +3380,7 @@ sfc_eth_dev_create_repr(struct sfc_adapter *sa,
 			uint16_t repr_port,
 			enum rte_eth_representor_type type)
 {
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 	struct sfc_repr_entity_info entity;
 	efx_mport_sel_t mport_sel;
 	int rc;
@@ -3414,7 +3417,7 @@ sfc_eth_dev_create_repr(struct sfc_adapter *sa,
 	entity.vf = repr_port;
 
 	rc = sfc_repr_create(sa->eth_dev, &entity, sa->mae.switch_domain_id,
-			     &mport_sel);
+			     encp->enc_mac_pdu_max, &mport_sel);
 	if (rc != 0) {
 		sfc_err(sa,
 			"failed to create representor for controller %u port %u repr_port %u: %s",
diff --git a/drivers/net/sfc/sfc_port.c b/drivers/net/sfc/sfc_port.c
index e5bb6d8620..5e80003ca1 100644
--- a/drivers/net/sfc/sfc_port.c
+++ b/drivers/net/sfc/sfc_port.c
@@ -391,7 +391,7 @@ sfc_port_configure(struct sfc_adapter *sa)
 
 	sfc_log_init(sa, "entry");
 
-	port->pdu = EFX_MAC_PDU(dev_data->mtu);
+	port->pdu = efx_mac_pdu_from_sdu(sa->nic, dev_data->mtu);
 
 	if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 		port->include_fcs = true;
diff --git a/drivers/net/sfc/sfc_repr.c b/drivers/net/sfc/sfc_repr.c
index 2c1421b959..18e76fa7da 100644
--- a/drivers/net/sfc/sfc_repr.c
+++ b/drivers/net/sfc/sfc_repr.c
@@ -32,6 +32,7 @@ struct sfc_repr_shared {
 	uint16_t		repr_id;
 	uint16_t		switch_domain_id;
 	uint16_t		switch_port_id;
+	unsigned int		max_pdu;
 };
 
 struct sfc_repr_queue_stats {
@@ -514,7 +515,7 @@ sfc_repr_dev_infos_get(struct rte_eth_dev *dev,
 
 	dev_info->device = dev->device;
 
-	dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX;
+	dev_info->max_rx_pktlen = srs->max_pdu;
 	dev_info->max_rx_queues = SFC_REPR_RXQ_MAX;
 	dev_info->max_tx_queues = SFC_REPR_TXQ_MAX;
 	dev_info->default_rxconf.rx_drop_en = 1;
@@ -920,6 +921,7 @@ struct sfc_repr_init_data {
 	efx_pcie_interface_t	intf;
 	uint16_t		pf;
 	uint16_t		vf;
+	unsigned int		max_pdu;
 };
 
 static int
@@ -1012,6 +1014,7 @@ sfc_repr_eth_dev_init(struct rte_eth_dev *dev, void *init_params)
 	srs->pf_port_id = repr_data->pf_port_id;
 	srs->repr_id = srs->switch_port_id;
 	srs->switch_domain_id = repr_data->switch_domain_id;
+	srs->max_pdu = repr_data->max_pdu;
 
 	dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 	dev->data->representor_id = srs->repr_id;
@@ -1062,6 +1065,7 @@ int
 sfc_repr_create(struct rte_eth_dev *parent,
 		struct sfc_repr_entity_info *entity,
 		uint16_t switch_domain_id,
+		unsigned int max_pdu,
 		const efx_mport_sel_t *mport_sel)
 {
 	struct sfc_repr_init_data repr_data;
@@ -1108,6 +1112,7 @@ sfc_repr_create(struct rte_eth_dev *parent,
 		repr_data.intf = entity->intf;
 		repr_data.pf = entity->pf;
 		repr_data.vf = entity->vf;
+		repr_data.max_pdu = max_pdu;
 
 		ret = rte_eth_dev_create(parent->device, name,
 					 sizeof(struct sfc_repr_shared),
diff --git a/drivers/net/sfc/sfc_repr.h b/drivers/net/sfc/sfc_repr.h
index 2093973761..01f5947a84 100644
--- a/drivers/net/sfc/sfc_repr.h
+++ b/drivers/net/sfc/sfc_repr.h
@@ -36,6 +36,7 @@ struct sfc_repr_entity_info {
 int sfc_repr_create(struct rte_eth_dev *parent,
 		    struct sfc_repr_entity_info *entity,
 		    uint16_t switch_domain_id,
+		    unsigned int max_pdu,
 		    const efx_mport_sel_t *mport_sel);
 
 #ifdef __cplusplus
diff --git a/drivers/net/sfc/sfc_tx.c b/drivers/net/sfc/sfc_tx.c
index f376f24f7b..ebc0a8235b 100644
--- a/drivers/net/sfc/sfc_tx.c
+++ b/drivers/net/sfc/sfc_tx.c
@@ -228,6 +228,8 @@ sfc_tx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
 
 	info.nic_dma_info = &sas->nic_dma_info;
 
+	info.max_pdu = encp->enc_mac_pdu_max;
+
 	rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
 				     &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
 				     socket_id, &info, &txq_info->dp);
-- 
2.39.5

[PATCH 39/46] common/sfc_efx/base: ignore legacy link events on new boards

[Ivan Malov]

New adaptors (for instance, Medford4) come with netport MCDI
and also support new link change events, however, older ones
can also be generated. For consistency, ignore legacy events.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_ev.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/common/sfc_efx/base/ef10_ev.c b/drivers/common/sfc_efx/base/ef10_ev.c
index 011ef49de7..82a2284f2b 100644
--- a/drivers/common/sfc_efx/base/ef10_ev.c
+++ b/drivers/common/sfc_efx/base/ef10_ev.c
@@ -907,6 +907,16 @@ ef10_ev_mcdi(
 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 
 	case MCDI_EVENT_CODE_LINKCHANGE_V2:
+		if (efx_np_supported(enp) != B_FALSE) {
+			/*
+			 * Netport MCDI capable NICs support new link change
+			 * events, but legacy LINKCHANGE_V2 events may still
+			 * show up should the firmware support them. For the
+			 * sake of consistency, ignore LINKCHANGE_V2 events.
+			 */
+			break;
+		}
+
 		ev_is_v2 = B_TRUE;
 		/* Fallthrough */
 	case MCDI_EVENT_CODE_LINKCHANGE: {
-- 
2.39.5

[PATCH 40/46] common/sfc_efx/base: add link event processing on new boards

[Ivan Malov]

Link change events on netport MCDI capable NICs do not carry
any specifics of the new link state. Such need to be queried
separately. Add processing of the events, with an indication
to the client driver telling it to collect the status itself.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_ev.c | 29 +++++++++++++++++++++++++++
 drivers/common/sfc_efx/base/efx.h     |  6 ++++++
 drivers/common/sfc_efx/base/efx_nic.c |  5 +++++
 3 files changed, 40 insertions(+)

diff --git a/drivers/common/sfc_efx/base/ef10_ev.c b/drivers/common/sfc_efx/base/ef10_ev.c
index 82a2284f2b..a97c1bf43e 100644
--- a/drivers/common/sfc_efx/base/ef10_ev.c
+++ b/drivers/common/sfc_efx/base/ef10_ev.c
@@ -866,6 +866,7 @@ ef10_ev_mcdi(
 	__in_opt	void *arg)
 {
 	efx_nic_t *enp = eep->ee_enp;
+	efx_port_t *epp = &(enp->en_port);
 	unsigned int code;
 	boolean_t should_abort = B_FALSE;
 	boolean_t ev_is_v2 = B_FALSE;
@@ -906,6 +907,34 @@ ef10_ev_mcdi(
 		break;
 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 
+	case MCDI_EVENT_CODE_PORT_LINKCHANGE:
+		/*
+		 * These events are generated on netport MCDI capable
+		 * boards. They supersede legacy LINKCHANGE_V2 events.
+		 */
+		if (MCDI_EV_FIELD(eqp, PORT_LINKCHANGE_PORT_HANDLE) ==
+		    epp->ep_np_handle) {
+			efx_link_mode_t mode;
+
+			if (MCDI_EV_FIELD(eqp, PORT_LINKCHANGE_LINK_UP) == 1)
+				mode = EFX_LINK_UNKNOWN;
+			else
+				mode = EFX_LINK_DOWN;
+
+			/*
+			 * The event does not contain full link state details.
+			 *
+			 * Either notify the client driver with a dummy link
+			 * mode value (UNKNOWN), just to say the link is up,
+			 * or, in case the link is not up, pass DOWN value.
+			 *
+			 * The client driver will need to poll for link state
+			 * in order to get full details like speed and duplex.
+			 */
+			should_abort = eecp->eec_link_change(arg, mode);
+		}
+		break;
+
 	case MCDI_EVENT_CODE_LINKCHANGE_V2:
 		if (efx_np_supported(enp) != B_FALSE) {
 			/*
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 73dc38f84e..7b43a89551 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1754,6 +1754,12 @@ typedef struct efx_nic_cfg_s {
 	uint32_t		enc_mac_pdu_min;
 	/* Maximum MAC PDU value to use with efx_mac_pdu_set() */
 	uint32_t		enc_mac_pdu_max;
+	/*
+	 * When true, the link mode value passed from eec_link_change() is
+	 * either UNKNOWN (merely saying the link is up) or DOWN. In order
+	 * to have exact speed/duplex, efx_port_poll() needs to be invoked.
+	 */
+	boolean_t		enc_link_ev_need_poll;
 } efx_nic_cfg_t;
 
 #define	EFX_PCI_VF_INVALID 0xffff
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 1c25270792..ab2bb1c160 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -494,6 +494,11 @@ efx_nic_probe(
 	encp->enc_mac_pdu_max = efx_mac_pdu_from_sdu(enp, EFX_MAC_SDU_MAX);
 	encp->enc_mac_pdu_min = EFX_MAC_PDU_MIN;
 
+	if (efx_np_supported(enp) == B_FALSE)
+		encp->enc_link_ev_need_poll = B_FALSE;
+	else
+		encp->enc_link_ev_need_poll = B_TRUE;
+
 	if ((rc = efx_phy_probe(enp)) != 0)
 		goto fail2;
 
-- 
2.39.5

[PATCH 41/46] net/sfc: query link status on link change events on new NICs

[Ivan Malov]

Link events signaled on new adaptors (Medford4 and later) do
not carry any specifics, so query the link status separately.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc.h        |  2 ++
 drivers/net/sfc/sfc_ethdev.c |  2 ++
 drivers/net/sfc/sfc_ev.c     | 51 +++++++++++++++++++++++++++++++++++-
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/drivers/net/sfc/sfc.h b/drivers/net/sfc/sfc.h
index 2432a2307e..819ce52529 100644
--- a/drivers/net/sfc/sfc.h
+++ b/drivers/net/sfc/sfc.h
@@ -309,6 +309,8 @@ struct sfc_adapter {
 	uint32_t			rxd_wait_timeout_ns;
 
 	bool				switchdev;
+
+	bool				link_ev_need_poll;
 };
 
 static inline struct sfc_adapter_shared *
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index bd0061f557..05933b1d39 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -3252,6 +3252,8 @@ sfc_eth_dev_init(struct rte_eth_dev *dev, void *init_params)
 	if (rc != 0)
 		goto fail_nic_dma_attach;
 
+	sa->link_ev_need_poll = encp->enc_link_ev_need_poll;
+
 	sfc_adapter_unlock(sa);
 
 	sfc_log_init(sa, "done");
diff --git a/drivers/net/sfc/sfc_ev.c b/drivers/net/sfc/sfc_ev.c
index c0d58c9554..1d1ee0671f 100644
--- a/drivers/net/sfc/sfc_ev.c
+++ b/drivers/net/sfc/sfc_ev.c
@@ -467,9 +467,58 @@ sfc_ev_link_change(void *arg, efx_link_mode_t link_mode)
 {
 	struct sfc_evq *evq = arg;
 	struct sfc_adapter *sa = evq->sa;
-	struct rte_eth_link new_link;
+	struct rte_eth_link new_link = {0};
 
+	if (sa->link_ev_need_poll) {
+		efx_link_mode_t new_mode;
+		bool poll_done = false;
+
+		/*
+		 * The event provides only the general status. When the link is
+		 * up, poll the port to get the speed, but it is not compulsory.
+		 */
+		if (link_mode != EFX_LINK_DOWN) {
+			int ret = 0;
+
+			if (sfc_adapter_trylock(sa)) {
+				/* Never poll when the adaptor is going down. */
+				if (sa->state == SFC_ETHDEV_STARTED) {
+					ret = efx_port_poll(sa->nic, &new_mode);
+					poll_done = true;
+				}
+
+				sfc_adapter_unlock(sa);
+			}
+
+			if (ret != 0) {
+				sfc_warn(sa, "port poll failed on link event");
+				poll_done = false;
+			}
+		}
+
+		if (poll_done) {
+			link_mode = new_mode;
+			goto decode_comprehensive;
+		}
+
+		new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		new_link.link_autoneg = RTE_ETH_LINK_AUTONEG;
+
+		if (link_mode == EFX_LINK_DOWN) {
+			new_link.link_speed  = RTE_ETH_SPEED_NUM_NONE;
+			new_link.link_status = RTE_ETH_LINK_DOWN;
+		} else {
+			new_link.link_speed  = RTE_ETH_SPEED_NUM_UNKNOWN;
+			new_link.link_status = RTE_ETH_LINK_UP;
+		}
+
+		goto set;
+	}
+
+decode_comprehensive:
 	sfc_port_link_mode_to_info(link_mode, &new_link);
+
+set:
 	if (rte_eth_linkstatus_set(sa->eth_dev, &new_link) == 0)
 		evq->sa->port.lsc_seq++;
 
-- 
2.39.5

[PATCH 42/46] common/sfc_efx/base: subscribe to netport link change events

[Ivan Malov]

Subscribe to the new link events on netport MCDI attach path.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_np.c | 56 ++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 88e13f0df9..73b022ac21 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -809,6 +809,48 @@ efx_np_stats_assign(
 }
 #endif /* EFSYS_OPT_MAC_STATS */
 
+static	__checkReturn	efx_rc_t
+efx_np_set_event_mask(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		boolean_t want_linkchange_events)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN,
+	    MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN);
+	efx_mcdi_req_t req;
+	efx_dword_t dword;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN;
+	req.emr_in_length = MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN;
+	req.emr_cmd = MC_CMD_SET_NETPORT_EVENTS_MASK;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	EFX_ZERO_DWORD(dword);
+
+	if (want_linkchange_events != B_FALSE)
+		EFX_SET_DWORD_BIT(dword, EVENT_MASK_PORT_LINKCHANGE);
+
+	MCDI_IN_SET_DWORD(req, SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE, nph);
+	MCDI_IN_SET_DWORD(req, SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK,
+	    dword.ed_u32[0]);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
@@ -873,8 +915,17 @@ efx_np_attach(
 		goto fail5;
 
 	epp->ep_mac_pdu = ms.enms_pdu;
+
+	/* Subscribe to link change events. */
+	rc = efx_np_set_event_mask(enp, epp->ep_np_handle, B_TRUE);
+	if (rc != 0)
+		goto fail6;
+
 	return (0);
 
+fail6:
+	EFSYS_PROBE(fail6);
+
 fail5:
 	EFSYS_PROBE(fail5);
 
@@ -898,8 +949,13 @@ efx_np_attach(
 efx_np_detach(
 	__in	efx_nic_t *enp)
 {
+	efx_port_t *epp = &(enp->en_port);
+
 	if (efx_np_supported(enp) == B_FALSE)
 		return;
+
+	/* Unsubscribe from link change events. */
+	(void) efx_np_set_event_mask(enp, epp->ep_np_handle, B_FALSE);
 }
 
 	__checkReturn	efx_rc_t
-- 
2.39.5

[PATCH 43/46] net/sfc: offer support for 200G link ability on new adaptors

[Ivan Malov]

New adaptors (for instance, Medford4) can support 200G speed.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc.c        |  5 ++++-
 drivers/net/sfc/sfc_ethdev.c | 15 +++++++++++++++
 drivers/net/sfc/sfc_port.c   |  6 ++++++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/sfc/sfc.c b/drivers/net/sfc/sfc.c
index 938c967430..69747e49ae 100644
--- a/drivers/net/sfc/sfc.c
+++ b/drivers/net/sfc/sfc.c
@@ -126,7 +126,8 @@ sfc_phy_cap_from_link_speeds(uint32_t speeds)
 				(1 << EFX_PHY_CAP_25000FDX) |
 				(1 << EFX_PHY_CAP_40000FDX) |
 				(1 << EFX_PHY_CAP_50000FDX) |
-				(1 << EFX_PHY_CAP_100000FDX);
+				(1 << EFX_PHY_CAP_100000FDX) |
+				(1 << EFX_PHY_CAP_200000FDX);
 	}
 	if (speeds & RTE_ETH_LINK_SPEED_1G)
 		phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
@@ -140,6 +141,8 @@ sfc_phy_cap_from_link_speeds(uint32_t speeds)
 		phy_caps |= (1 << EFX_PHY_CAP_50000FDX);
 	if (speeds & RTE_ETH_LINK_SPEED_100G)
 		phy_caps |= (1 << EFX_PHY_CAP_100000FDX);
+	if (speeds & RTE_ETH_LINK_SPEED_200G)
+		phy_caps |= (1 << EFX_PHY_CAP_200000FDX);
 
 	return phy_caps;
 }
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 05933b1d39..80eb39e58d 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -117,6 +117,8 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G;
 	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX))
 		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G;
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_200000FDX))
+		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_200G;
 
 	dev_info->max_rx_queues = sa->rxq_max;
 	dev_info->max_tx_queues = sa->txq_max;
@@ -2442,6 +2444,19 @@ sfc_fec_get_capa_speed_to_fec(uint32_t supported_caps,
 		}
 		num++;
 	}
+	if (supported_caps & (1u << EFX_PHY_CAP_200000FDX)) {
+		if (speed_fec_capa != NULL) {
+			speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_200G;
+			speed_fec_capa[num].capa =
+				RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+				RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
+			if (rs) {
+				speed_fec_capa[num].capa |=
+					RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+			}
+		}
+		num++;
+	}
 
 	return num;
 }
diff --git a/drivers/net/sfc/sfc_port.c b/drivers/net/sfc/sfc_port.c
index 5e80003ca1..0a31a394d5 100644
--- a/drivers/net/sfc/sfc_port.c
+++ b/drivers/net/sfc/sfc_port.c
@@ -144,6 +144,8 @@ sfc_port_init_dev_link(struct sfc_adapter *sa)
 static efx_link_mode_t
 sfc_port_phy_caps_to_max_link_speed(uint32_t phy_caps)
 {
+	if (phy_caps & (1u << EFX_PHY_CAP_200000FDX))
+		return EFX_LINK_200000FDX;
 	if (phy_caps & (1u << EFX_PHY_CAP_100000FDX))
 		return EFX_LINK_100000FDX;
 	if (phy_caps & (1u << EFX_PHY_CAP_50000FDX))
@@ -649,6 +651,10 @@ sfc_port_link_mode_to_info(efx_link_mode_t link_mode,
 		link_info->link_speed  = RTE_ETH_SPEED_NUM_100G;
 		link_info->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 		break;
+	case EFX_LINK_200000FDX:
+		link_info->link_speed  = RTE_ETH_SPEED_NUM_200G;
+		link_info->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		break;
 	default:
 		SFC_ASSERT(B_FALSE);
 		/* FALLTHROUGH */
-- 
2.39.5

[PATCH 44/46] common/sfc_efx/base: support controls for netport lane count

[Ivan Malov]

On netport MCDI capable adaptors, link modes exported by libefx can be
backed by different technologies with different lane counts. Allow the
client drivers to get and set the lane count and query possible values.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_phy.c     |   2 +
 drivers/common/sfc_efx/base/efx.h          |  29 ++++
 drivers/common/sfc_efx/base/efx_impl.h     |   4 +
 drivers/common/sfc_efx/base/efx_np.c       | 192 +++++++++++++++++++--
 drivers/common/sfc_efx/base/efx_phy.c      |  62 ++++++-
 drivers/common/sfc_efx/base/efx_port.c     |   1 +
 drivers/common/sfc_efx/base/medford4_phy.c |   5 +-
 drivers/common/sfc_efx/sfc_base_symbols.c  |   1 +
 8 files changed, 280 insertions(+), 16 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index 114543e156..aaad105735 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -338,6 +338,8 @@ ef10_phy_get_link(
 			    fec, &elsp->epls.epls_link_mode,
 			    &elsp->epls.epls_fcntl, &elsp->epls.epls_fec);
 
+	elsp->epls.epls_lane_count = EFX_PHY_LANE_COUNT_DEFAULT;
+
 	if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN) {
 		elsp->epls.epls_ld_cap_mask = 0;
 	} else {
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 7b43a89551..8958f1b170 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1266,6 +1266,28 @@ efx_phy_lp_cap_get(
 	__in		efx_nic_t *enp,
 	__out		uint32_t *maskp);
 
+typedef enum efx_phy_lane_count_e {
+	EFX_PHY_LANE_COUNT_DEFAULT = 0,
+	EFX_PHY_LANE_COUNT_1 = 1,
+	EFX_PHY_LANE_COUNT_2 = 2,
+	EFX_PHY_LANE_COUNT_4 = 4,
+	EFX_PHY_LANE_COUNT_10 = 10,
+	EFX_PHY_LANE_COUNT_NTYPES,
+} efx_phy_lane_count_t;
+
+/*
+ * Instruct the port to use the specified lane count. For this to work, the
+ * active subset of advertised link modes must include at least one mode that
+ * supports this value. This API works only on netport MCDI capable adaptors.
+ *
+ * To query the current lane count, use efx_phy_link_state_get().
+ */
+LIBEFX_API
+extern	__checkReturn	efx_rc_t
+efx_phy_lane_count_set(
+	__in		efx_nic_t *enp,
+	__in		efx_phy_lane_count_t lane_count);
+
 LIBEFX_API
 extern	__checkReturn	efx_rc_t
 efx_phy_oui_get(
@@ -1760,6 +1782,12 @@ typedef struct efx_nic_cfg_s {
 	 * to have exact speed/duplex, efx_port_poll() needs to be invoked.
 	 */
 	boolean_t		enc_link_ev_need_poll;
+	/*
+	 * An array of masks to tell which link mode supports which lane counts.
+	 * For bit definitions, see 'efx_phy_lane_count_t'. It is only filled in
+	 * on netport MCDI capable adaptors.
+	 */
+	efx_dword_t		enc_phy_lane_counts[EFX_LINK_NMODES];
 } efx_nic_cfg_t;
 
 #define	EFX_PCI_VF_INVALID 0xffff
@@ -4072,6 +4100,7 @@ typedef struct efx_phy_link_state_s {
 	unsigned int		epls_fcntl;
 	efx_phy_fec_type_t	epls_fec;
 	efx_link_mode_t		epls_link_mode;
+	efx_phy_lane_count_t	epls_lane_count;
 } efx_phy_link_state_t;
 
 LIBEFX_API
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 43964ccdba..69268546d2 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -396,6 +396,8 @@ typedef struct efx_port_s {
 	uint8_t			ep_np_cap_data_raw[MC_CMD_ETH_AN_FIELDS_LEN];
 	/* Lookup table providing DMA buffer field IDs by EFX statistic IDs. */
 	efx_np_stat_t		ep_np_mac_stat_lut[EFX_MAC_NSTATS];
+	/* Client-requested lane count for the physical link. */
+	efx_phy_lane_count_t	ep_np_lane_count_req;
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
@@ -1916,6 +1918,7 @@ efx_np_detach(
 typedef struct efx_np_link_state_s {
 	uint32_t		enls_adv_cap_mask;
 	uint32_t		enls_lp_cap_mask;
+	efx_phy_lane_count_t	enls_lane_count;
 	efx_loopback_type_t	enls_loopback;
 	uint32_t		enls_speed;
 	uint8_t			enls_fec;
@@ -1953,6 +1956,7 @@ efx_np_link_ctrl(
 	__in		const uint8_t *cap_mask_sup_raw,
 	__in		efx_link_mode_t loopback_link_mode,
 	__in		efx_loopback_type_t loopback_mode,
+	__in		efx_phy_lane_count_t lane_count,
 	__in		uint32_t cap_mask_sw,
 	__in		boolean_t fcntl_an);
 
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 73b022ac21..35ae07a9a0 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -86,6 +86,7 @@ struct efx_np_cap_map {
 	uint16_t	encm_sw;
 };
 
+/* NOTE: keep this in sync with 'efx_np_tech_to_lane_count'. */
 static const struct efx_np_cap_map efx_np_cap_map_tech[] = {
 	/* 1G */
 	{ MC_CMD_ETH_TECH_1000BASEKX, EFX_PHY_CAP_1000FDX },
@@ -292,6 +293,71 @@ efx_np_get_fixed_port_props(
 	return (rc);
 }
 
+static efx_phy_lane_count_t efx_np_tech_to_lane_count[] = {
+	/* 1G */
+	[MC_CMD_ETH_TECH_1000BASEKX] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_1000BASEX] = EFX_PHY_LANE_COUNT_1,
+
+	/* 10G */
+	[MC_CMD_ETH_TECH_10GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_LR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_LRM] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_ER] = EFX_PHY_LANE_COUNT_1,
+
+	/* 25GBASE */
+	[MC_CMD_ETH_TECH_25GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_25GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_25GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_25GBASE_LR_ER] = EFX_PHY_LANE_COUNT_1,
+
+	/* 40G */
+	[MC_CMD_ETH_TECH_40GBASE_KR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_40GBASE_CR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_40GBASE_SR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_40GBASE_LR4] = EFX_PHY_LANE_COUNT_4,
+
+	/* 50G */
+	[MC_CMD_ETH_TECH_50GBASE_CR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_50GBASE_KR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_50GBASE_SR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_50GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_LR_ER_FR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_DR] = EFX_PHY_LANE_COUNT_1,
+
+	/* 100G */
+	[MC_CMD_ETH_TECH_100GBASE_KR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_SR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_CR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_LR4_ER4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_KR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_SR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_CR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_DR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_LR_ER_FR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_DR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_CR10] = EFX_PHY_LANE_COUNT_10,
+
+	/* 200G */
+	[MC_CMD_ETH_TECH_200GBASE_KR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_SR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_DR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_CR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_KR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_SR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_DR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_CR2] = EFX_PHY_LANE_COUNT_2,
+};
+
 	__checkReturn	efx_rc_t
 efx_np_link_state(
 	__in		efx_nic_t *enp,
@@ -304,6 +370,7 @@ efx_np_link_state(
 	uint32_t status_flags;
 	efx_mcdi_req_t req;
 	uint32_t v3_flags;
+	uint16_t tech;
 	efx_rc_t rc;
 
 	req.emr_out_length = MC_CMD_LINK_STATE_OUT_V3_LEN;
@@ -379,6 +446,13 @@ efx_np_link_state(
 		    LINK_STATE_OUT_LINK_PARTNER_ABILITIES),
 	    &lsp->enls_lp_cap_mask);
 
+	tech = MCDI_OUT_WORD(req, LINK_STATE_OUT_LINK_TECHNOLOGY);
+
+	if (tech < EFX_ARRAY_SIZE(efx_np_tech_to_lane_count))
+		lsp->enls_lane_count = efx_np_tech_to_lane_count[tech];
+	else
+		lsp->enls_lane_count = EFX_PHY_LANE_COUNT_DEFAULT;
+
 	return (0);
 
 #if EFSYS_OPT_LOOPBACK
@@ -529,6 +603,53 @@ efx_np_assign_loopback_props(
 }
 #endif /* EFSYS_OPT_LOOPBACK */
 
+static				void
+efx_np_assign_lane_counts(
+	__in			efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+	unsigned int i;
+
+	for (i = 0; i < EFX_ARRAY_SIZE(encp->enc_phy_lane_counts); ++i) {
+		const struct efx_np_cap_map *map = efx_np_cap_map_tech;
+		uint16_t cap_enum_sw;
+		efx_dword_t dword;
+		efx_rc_t rc;
+
+		EFX_ZERO_DWORD(dword);
+
+		rc = efx_np_sw_link_mode_to_cap(i, &cap_enum_sw);
+		if (rc != 0) {
+			/* No support for this link mode => no lane counts. */
+			encp->enc_phy_lane_counts[i] = dword;
+			continue;
+		}
+
+		FOREACH_SUP_CAP(map,
+		    EFX_ARRAY_SIZE(efx_np_cap_map_tech),
+		    MCDI_STRUCT_MEMBER(epp->ep_np_cap_data_raw, const uint8_t,
+			    MC_CMD_ETH_AN_FIELDS_TECH_MASK),
+		    MC_CMD_ETH_AN_FIELDS_TECH_MASK_LEN) {
+			efx_phy_lane_count_t lane_count;
+
+			if (map->encm_sw != cap_enum_sw)
+				continue;
+
+			if (map->encm_hw >=
+			    EFX_ARRAY_SIZE(efx_np_tech_to_lane_count))
+				continue;
+
+			lane_count = efx_np_tech_to_lane_count[map->encm_hw];
+
+			if (lane_count != EFX_PHY_LANE_COUNT_DEFAULT)
+				EFX_SET_DWORD_BIT(dword, lane_count);
+		}
+
+		encp->enc_phy_lane_counts[i] = dword;
+	}
+}
+
 #if EFSYS_OPT_MAC_STATS
 /* HW statistic IDs, as per MC_CMD_MAC_STATISTICS_DESCRIPTOR format. */
 #define	EFX_NP_HW_STAT_ID(_src, _idx)					\
@@ -904,6 +1025,8 @@ efx_np_attach(
 	efx_np_assign_loopback_props(enp);
 #endif /* EFSYS_OPT_LOOPBACK */
 
+	efx_np_assign_lane_counts(enp);
+
 #if EFSYS_OPT_MAC_STATS
 	rc = efx_np_stats_assign(enp);
 	if (rc != 0)
@@ -1008,6 +1131,13 @@ efx_np_mac_state(
 	return (rc);
 }
 
+/* Filter callback for capability lookups. Return 'B_FALSE' to skip the enum. */
+typedef			boolean_t
+(efx_np_cap_filter_cb)(
+	__in		uint16_t enum_hw,
+	__in		void *arg);
+
+
 static					void
 efx_np_cap_mask_sw_to_hw(
 	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
@@ -1015,6 +1145,8 @@ efx_np_cap_mask_sw_to_hw(
 	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
 	__in				size_t hw_cap_data_nbytes,
 	__in				uint32_t mask_sw,
+	__in_opt			efx_np_cap_filter_cb *filter_cb,
+	__in_opt			void *filter_arg,
 	__out				uint8_t *mask_hwp)
 {
 	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
@@ -1024,6 +1156,10 @@ efx_np_cap_mask_sw_to_hw(
 		if ((mask_sw & flag_sw) != flag_sw)
 			continue;
 
+		if (filter_cb != NULL &&
+		    filter_cb(hw_sw_map->encm_hw, filter_arg) == B_FALSE)
+			continue;
+
 		mask_hwp[CAP_BYTE(hw_sw_map)] |= CAP_FLAG(hw_sw_map);
 		mask_sw &= ~(flag_sw);
 	}
@@ -1039,16 +1175,18 @@ efx_np_cap_mask_sw_to_hw(
  *
  * Do not check the input mask for leftover bits (unknown to EFX), as
  * inputs should have been validated by efx_phy_adv_cap_set() already.
+ *
+ * It is possible to use a callback to filter out certain mappings.
  */
 #define	EFX_NP_CAP_MASK_SW_TO_HW(					\
 	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
-	    _mask_sw, _mask_hwp)					\
+	    _mask_sw, _filter_cb, _filter_arg, _mask_hwp)		\
 	efx_np_cap_mask_sw_to_hw((_hw_sw_cap_map),			\
 	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
 	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
 		    MC_CMD_##_hw_cap_section),				\
-	    MC_CMD_##_hw_cap_section##_LEN,				\
-	    (_mask_sw), (_mask_hwp))
+	    MC_CMD_##_hw_cap_section##_LEN, (_mask_sw),			\
+	    (_filter_cb), (_filter_arg), (_mask_hwp))
 
 static					void
 efx_np_cap_sw_mask_to_hw_enum(
@@ -1057,6 +1195,8 @@ efx_np_cap_sw_mask_to_hw_enum(
 	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
 	__in				size_t hw_cap_data_nbytes,
 	__in				uint32_t mask_sw,
+	__in_opt			efx_np_cap_filter_cb *filter_cb,
+	__in_opt			void *filter_arg,
 	__out				boolean_t *supportedp,
 	__out_opt			uint16_t *enum_hwp)
 {
@@ -1082,10 +1222,14 @@ efx_np_cap_sw_mask_to_hw_enum(
 			sw_check_mask |= flag_sw;
 
 			if ((hw_cap_data[byte_idx] & flag_hw) == flag_hw) {
-				mask_sw &= ~(flag_sw);
-
-				if (enum_hwp != NULL)
-					*enum_hwp = hw_sw_map->encm_hw;
+				if (filter_cb == NULL ||
+				    filter_cb(hw_sw_map->encm_hw, filter_arg) !=
+				    B_FALSE) {
+					mask_sw &= ~(flag_sw);
+
+					if (enum_hwp != NULL)
+						*enum_hwp = hw_sw_map->encm_hw;
+				}
 			}
 		}
 
@@ -1121,17 +1265,39 @@ efx_np_cap_sw_mask_to_hw_enum(
  * Convert (conceivably) the only EFX capability bit of the given mask to
  * the HW enum value, provided that the capability is supported by the HW,
  * where the latter follows from the given fraction of HW capability data.
+ *
+ * It is possible to use a callback to filter out certain mappings.
  */
 #define	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(					\
 	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
-	    _mask_sw, _supportedp, _enum_hwp)				\
+	    _mask_sw, _filter_cb, _filter_arg, _supportedp, _enum_hwp)	\
 	efx_np_cap_sw_mask_to_hw_enum((_hw_sw_cap_map),			\
 	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
 	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
 		    MC_CMD_##_hw_cap_section),				\
 	    MC_CMD_##_hw_cap_section##_LEN, (_mask_sw),			\
+	    (_filter_cb), (_filter_arg),				\
 	    (_supportedp), (_enum_hwp))
 
+static					boolean_t
+efx_np_filter_tech_by_lane_count_cb(
+	__in				uint16_t enum_hw,
+	__in				void *arg)
+{
+	efx_phy_lane_count_t lane_count = *((efx_phy_lane_count_t *)arg);
+
+	if (lane_count == EFX_PHY_LANE_COUNT_DEFAULT)
+		return B_TRUE;
+
+	if (enum_hw >= EFX_ARRAY_SIZE(efx_np_tech_to_lane_count))
+		return B_FALSE;
+
+	if (efx_np_tech_to_lane_count[enum_hw] != lane_count)
+		return B_FALSE;
+
+	return B_TRUE;
+}
+
 	__checkReturn	efx_rc_t
 efx_np_link_ctrl(
 	__in		efx_nic_t *enp,
@@ -1139,6 +1305,7 @@ efx_np_link_ctrl(
 	__in		const uint8_t *cap_data_raw,
 	__in		efx_link_mode_t loopback_link_mode,
 	__in		efx_loopback_type_t loopback_mode,
+	__in		efx_phy_lane_count_t lane_count,
 	__in		uint32_t cap_mask_sw,
 	__in		boolean_t fcntl_an)
 {
@@ -1190,8 +1357,9 @@ efx_np_link_ctrl(
 
 		rc = efx_np_sw_link_mode_to_cap(loopback_link_mode,
 					    &cap_enum_sw);
-		if (rc != 0)
+		if (rc != 0) {
 			goto fail2;
+		}
 
 		EFX_NP_CAP_ENUM_SW_TO_HW(efx_np_cap_map_tech,
 		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_enum_sw,
@@ -1208,12 +1376,13 @@ efx_np_link_ctrl(
 	} else if (cap_mask_sw & (1U << EFX_PHY_CAP_AN)) {
 		EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_tech,
 		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    efx_np_filter_tech_by_lane_count_cb, &lane_count,
 		    cap_mask_hw_techp);
 
 		if (fcntl_an != B_FALSE) {
 			EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_pause,
 			    ETH_AN_FIELDS_PAUSE_MASK, cap_data_raw, cap_mask_sw,
-			    cap_mask_hw_pausep);
+			    NULL, NULL, cap_mask_hw_pausep);
 		}
 
 		flags |= 1U << MC_CMD_LINK_FLAGS_AUTONEG_EN;
@@ -1221,6 +1390,7 @@ efx_np_link_ctrl(
 	} else {
 		EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_tech,
 		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    efx_np_filter_tech_by_lane_count_cb, &lane_count,
 		    &supported, &link_tech);
 
 		if (supported == B_FALSE) {
@@ -1241,7 +1411,7 @@ efx_np_link_ctrl(
 	 */
 	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_fec_req,
 	    ETH_AN_FIELDS_FEC_REQ, cap_data_raw, cap_mask_sw,
-	    &supported, &cap_enum_hw);
+	    NULL, NULL, &supported, &cap_enum_hw);
 
 	if ((cap_mask_sw & EFX_PHY_CAP_FEC_MASK) != 0 && supported == B_FALSE) {
 		rc = ENOTSUP;
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index e3b9d20d59..1f99c72e62 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -262,6 +262,12 @@ efx_phy_adv_cap_set(
 		goto fail1;
 	}
 
+	if (efx_np_supported(enp) == B_FALSE &&
+	    epp->ep_np_lane_count_req != EFX_PHY_LANE_COUNT_DEFAULT) {
+		rc = ENOTSUP;
+		goto fail2;
+	}
+
 	if (epp->ep_adv_cap_mask == mask)
 		goto done;
 
@@ -269,13 +275,13 @@ efx_phy_adv_cap_set(
 	epp->ep_adv_cap_mask = mask;
 
 	if ((rc = epop->epo_reconfigure(enp)) != 0)
-		goto fail2;
+		goto fail3;
 
 done:
 	return (0);
 
-fail2:
-	EFSYS_PROBE(fail2);
+fail3:
+	EFSYS_PROBE(fail3);
 
 	epp->ep_adv_cap_mask = old_mask;
 	/* Reconfigure for robustness */
@@ -287,6 +293,9 @@ efx_phy_adv_cap_set(
 		EFSYS_ASSERT(0);
 	}
 
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 
@@ -306,6 +315,53 @@ efx_phy_lp_cap_get(
 	*maskp = epp->ep_lp_cap_mask;
 }
 
+	__checkReturn	efx_rc_t
+efx_phy_lane_count_set(
+	__in		efx_nic_t *enp,
+	__in		efx_phy_lane_count_t lane_count)
+{
+	efx_port_t *epp = &(enp->en_port);
+	const efx_phy_ops_t *epop = epp->ep_epop;
+	efx_phy_lane_count_t lane_count_prev = epp->ep_np_lane_count_req;
+	efx_rc_t rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+
+	if (lane_count == lane_count_prev)
+		return 0;
+
+	if (efx_np_supported(enp) == B_FALSE) {
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
+	if (lane_count >= EFX_PHY_LANE_COUNT_NTYPES) {
+		rc = EINVAL;
+		goto fail2;
+	}
+
+	epp->ep_np_lane_count_req = lane_count;
+
+	rc = epop->epo_reconfigure(enp);
+	if (rc != 0) {
+		epp->ep_np_lane_count_req = lane_count_prev;
+		goto fail3;
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
 	__checkReturn	efx_rc_t
 efx_phy_oui_get(
 	__in		efx_nic_t *enp,
diff --git a/drivers/common/sfc_efx/base/efx_port.c b/drivers/common/sfc_efx/base/efx_port.c
index 389efb2fe9..7e514e92dd 100644
--- a/drivers/common/sfc_efx/base/efx_port.c
+++ b/drivers/common/sfc_efx/base/efx_port.c
@@ -26,6 +26,7 @@ efx_port_init(
 
 	enp->en_mod_flags |= EFX_MOD_PORT;
 
+	epp->ep_np_lane_count_req = EFX_PHY_LANE_COUNT_DEFAULT;
 	epp->ep_mac_type = EFX_MAC_INVALID;
 	epp->ep_link_mode = EFX_LINK_UNKNOWN;
 	epp->ep_mac_drain = B_TRUE;
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
index cc4e77587b..9ba6dfbc10 100644
--- a/drivers/common/sfc_efx/base/medford4_phy.c
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -43,6 +43,7 @@ medford4_phy_get_link(
 
 	elsp->epls.epls_adv_cap_mask = ls.enls_adv_cap_mask;
 	elsp->epls.epls_lp_cap_mask = ls.enls_lp_cap_mask;
+	elsp->epls.epls_lane_count = ls.enls_lane_count;
 	elsp->els_loopback = ls.enls_loopback;
 
 	rc = efx_np_mac_state(enp, nph, &ms);
@@ -115,8 +116,8 @@ medford4_phy_reconfigure(
 #endif /* EFSYS_OPT_LOOPBACK */
 
 	rc = efx_np_link_ctrl(enp, epp->ep_np_handle, epp->ep_np_cap_data_raw,
-		    loopback_link_mode, loopback, epp->ep_adv_cap_mask,
-		    epp->ep_fcntl_autoneg);
+		    loopback_link_mode, loopback, epp->ep_np_lane_count_req,
+		    epp->ep_adv_cap_mask, epp->ep_fcntl_autoneg);
 	if (rc != 0)
 		goto fail2;
 
diff --git a/drivers/common/sfc_efx/sfc_base_symbols.c b/drivers/common/sfc_efx/sfc_base_symbols.c
index 0e74034031..bbb6f39924 100644
--- a/drivers/common/sfc_efx/sfc_base_symbols.c
+++ b/drivers/common/sfc_efx/sfc_base_symbols.c
@@ -195,6 +195,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(efx_nic_dma_map)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_verify)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_adv_cap_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_adv_cap_set)
+RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_lane_count_set)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_lp_cap_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_oui_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_media_type_get)
-- 
2.39.5

Re: [PATCH 44/46] common/sfc_efx/base: support controls for netport lane count

[Andrew Rybchenko]

On 4/16/25 17:00, Ivan Malov wrote:
> On netport MCDI capable adaptors, link modes exported by libefx can be
> backed by different technologies with different lane counts. Allow the
> client drivers to get and set the lane count and query possible values.
> 
> Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>
> Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>

[snip]

> @@ -1190,8 +1357,9 @@ efx_np_link_ctrl(
>   
>   		rc = efx_np_sw_link_mode_to_cap(loopback_link_mode,
>   					    &cap_enum_sw);
> -		if (rc != 0)
> +		if (rc != 0) {
>   			goto fail2;
> +		}

Looks like unrelated style change

>   
>   		EFX_NP_CAP_ENUM_SW_TO_HW(efx_np_cap_map_tech,
>   		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_enum_sw,

[PATCH 45/46] net/sfc: add support for control of physical port lane count

[Ivan Malov]

Since 24.11, DPDK has supported APIs to control lane count of the
physical link. Provide driver-level support for that on adaptors that
are netport MCDI capabale (Medford4, for instance).

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc.h        |   2 +
 drivers/net/sfc/sfc_ethdev.c | 147 +++++++++++++++++++++++++++++++++++
 drivers/net/sfc/sfc_port.c   |  19 +++++
 3 files changed, 168 insertions(+)

diff --git a/drivers/net/sfc/sfc.h b/drivers/net/sfc/sfc.h
index 819ce52529..af32ccfaa3 100644
--- a/drivers/net/sfc/sfc.h
+++ b/drivers/net/sfc/sfc.h
@@ -67,6 +67,8 @@ struct sfc_dp_rx;
 struct sfc_port {
 	unsigned int			lsc_seq;
 
+	efx_phy_lane_count_t		phy_lane_count_active;
+	efx_phy_lane_count_t		phy_lane_count_req;
 	uint32_t			phy_adv_cap_mask;
 	uint32_t			phy_adv_cap;
 	uint32_t			fec_cfg;
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 80eb39e58d..b38fc79d62 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -291,6 +291,150 @@ sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 	return ret;
 }
 
+static int
+sfc_dev_speed_lanes_get(struct rte_eth_dev *dev, uint32_t *lane_countp)
+{
+	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	struct sfc_port *port;
+	int rc = 0;
+
+	if (lane_countp == NULL)
+		return -EINVAL;
+
+	sfc_adapter_lock(sa);
+	port = &sa->port;
+
+	if (sa->state != SFC_ETHDEV_STARTED) {
+		/* The API wants 'active' lanes, so it is safe to indicate 0. */
+		*lane_countp = 0;
+		goto unlock;
+	}
+
+	if (port->phy_lane_count_active == EFX_PHY_LANE_COUNT_DEFAULT) {
+		rc = ENOTSUP;
+		goto unlock;
+	}
+
+	*lane_countp = port->phy_lane_count_active;
+
+unlock:
+	sfc_adapter_unlock(sa);
+	return -rc;
+}
+
+static int
+sfc_dev_speed_lanes_set(struct rte_eth_dev *dev, uint32_t lane_count)
+{
+	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	int rc = 0;
+
+	sfc_adapter_lock(sa);
+
+	if (sa->state == SFC_ETHDEV_STARTED) {
+		rc = EBUSY;
+		goto unlock;
+	}
+
+	if (lane_count == 0) {
+		rc = EINVAL;
+		goto unlock;
+	}
+
+	sa->port.phy_lane_count_req = lane_count;
+
+unlock:
+	sfc_adapter_unlock(sa);
+	return -rc;
+}
+
+static int
+sfc_dev_speed_lane_cap_handle(const efx_nic_cfg_t *encp,
+			      efx_link_mode_t link_mode,
+			      unsigned int *nb_caps_to_fillp,
+			      struct rte_eth_speed_lanes_capa **capp)
+{
+	uint32_t lane_counts = encp->enc_phy_lane_counts[link_mode].ed_u32[0];
+	struct rte_eth_speed_lanes_capa *cap = *capp;
+	uint32_t speed;
+
+	if (lane_counts == 0) {
+		/*
+		 * The mask of supported lane counts for this link mode is
+		 * empty. Do not waste output entries for such link modes.
+		 */
+		return 0;
+	}
+
+	switch (link_mode) {
+	case EFX_LINK_1000FDX:
+		speed = RTE_ETH_SPEED_NUM_1G;
+		break;
+	case EFX_LINK_10000FDX:
+		speed = RTE_ETH_SPEED_NUM_10G;
+		break;
+	case EFX_LINK_25000FDX:
+		speed = RTE_ETH_SPEED_NUM_25G;
+		break;
+	case EFX_LINK_40000FDX:
+		speed = RTE_ETH_SPEED_NUM_40G;
+		break;
+	case EFX_LINK_50000FDX:
+		speed = RTE_ETH_SPEED_NUM_50G;
+		break;
+	case EFX_LINK_100000FDX:
+		speed = RTE_ETH_SPEED_NUM_100G;
+		break;
+	case EFX_LINK_200000FDX:
+		speed = RTE_ETH_SPEED_NUM_200G;
+		break;
+	default:
+		/* No lane counts for this link mode. */
+		return 0;
+	}
+
+	if (*nb_caps_to_fillp == 0) {
+		if (cap == NULL) {
+			/* Dry run. Indicate that an entry is available. */
+			return 1;
+		}
+
+		/* We have run out of space in the user output buffer. */
+		return 0;
+	}
+
+	cap->capa = lane_counts;
+	cap->speed = speed;
+
+	--(*nb_caps_to_fillp);
+	++(*capp);
+	return 1;
+}
+
+static int
+sfc_dev_speed_lanes_get_capa(struct rte_eth_dev *dev,
+			     struct rte_eth_speed_lanes_capa *caps,
+			     unsigned int nb_caps)
+{
+	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
+	efx_link_mode_t i;
+	int ret = 0;
+
+	sfc_adapter_lock(sa);
+
+	if (sa->state < SFC_ETHDEV_INITIALIZED) {
+		ret = -ENODATA;
+		goto unlock;
+	}
+
+	for (i = 0; i < EFX_LINK_NMODES; ++i)
+		ret += sfc_dev_speed_lane_cap_handle(encp, i, &nb_caps, &caps);
+
+unlock:
+	sfc_adapter_unlock(sa);
+	return ret;
+}
+
 static int
 sfc_dev_stop(struct rte_eth_dev *dev)
 {
@@ -2759,6 +2903,9 @@ static const struct eth_dev_ops sfc_eth_dev_ops = {
 	.allmulticast_enable		= sfc_dev_allmulti_enable,
 	.allmulticast_disable		= sfc_dev_allmulti_disable,
 	.link_update			= sfc_dev_link_update,
+	.speed_lanes_get		= sfc_dev_speed_lanes_get,
+	.speed_lanes_set		= sfc_dev_speed_lanes_set,
+	.speed_lanes_get_capa		= sfc_dev_speed_lanes_get_capa,
 	.stats_get			= sfc_stats_get,
 	.stats_reset			= sfc_stats_reset,
 	.xstats_get			= sfc_xstats_get,
diff --git a/drivers/net/sfc/sfc_port.c b/drivers/net/sfc/sfc_port.c
index 0a31a394d5..e5a7b8358d 100644
--- a/drivers/net/sfc/sfc_port.c
+++ b/drivers/net/sfc/sfc_port.c
@@ -187,6 +187,7 @@ sfc_port_fill_mac_stats_info(struct sfc_adapter *sa)
 int
 sfc_port_start(struct sfc_adapter *sa)
 {
+	efx_phy_link_state_t link_state = {0};
 	struct sfc_port *port = &sa->port;
 	int rc;
 	uint32_t phy_adv_cap;
@@ -243,6 +244,20 @@ sfc_port_start(struct sfc_adapter *sa)
 	if (rc != 0)
 		goto fail_phy_adv_cap_set;
 
+	sfc_log_init(sa, "set phy lane count -- %s",
+		     (port->phy_lane_count_req == EFX_PHY_LANE_COUNT_DEFAULT) ?
+		     "let EFX pick default value" : "use custom value");
+	rc = efx_phy_lane_count_set(sa->nic, port->phy_lane_count_req);
+	if (rc != 0)
+		goto fail_phy_lane_count_set;
+
+	sfc_log_init(sa, "get phy lane count");
+	rc = efx_phy_link_state_get(sa->nic, &link_state);
+	if (rc != 0)
+		goto fail_phy_lane_count_get;
+
+	port->phy_lane_count_active = link_state.epls_lane_count;
+
 	sfc_log_init(sa, "set MAC PDU %u", (unsigned int)port->pdu);
 	rc = efx_mac_pdu_set(sa->nic, port->pdu);
 	if (rc != 0)
@@ -350,6 +365,8 @@ sfc_port_start(struct sfc_adapter *sa)
 fail_mac_filter_set:
 fail_mac_addr_set:
 fail_mac_pdu_set:
+fail_phy_lane_count_get:
+fail_phy_lane_count_set:
 fail_phy_adv_cap_set:
 fail_mac_fcntl_set:
 fail_mac_vlan_strip_set:
@@ -427,6 +444,8 @@ sfc_port_attach(struct sfc_adapter *sa)
 
 	sfc_log_init(sa, "entry");
 
+	port->phy_lane_count_req = EFX_PHY_LANE_COUNT_DEFAULT;
+
 	efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM, &port->phy_adv_cap_mask);
 
 	/* Enable flow control by default */
-- 
2.39.5

[PATCH 46/46] doc: advertise support for AMD Solarflare X45xx adapters

[Ivan Malov]

The two NICs, X4522 and X4542, are based on EF10 architecture.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 doc/guides/nics/sfc_efx.rst            | 9 ++++++++-
 doc/guides/rel_notes/release_25_07.rst | 4 ++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/sfc_efx.rst b/doc/guides/nics/sfc_efx.rst
index eafb88191a..4bd9f8c441 100644
--- a/doc/guides/nics/sfc_efx.rst
+++ b/doc/guides/nics/sfc_efx.rst
@@ -10,7 +10,8 @@ Solarflare libefx-based Poll Mode Driver
 
 The SFC EFX PMD (**librte_net_sfc_efx**) provides poll mode driver support
 for **Solarflare SFN7xxx and SFN8xxx** family of 10/40 Gbps adapters,
-**Solarflare XtremeScale X2xxx** family of 10/25/40/50/100 Gbps adapters and
+**Solarflare XtremeScale X2xxx** family of 10/25/40/50/100 Gbps adapters,
+**Solarflare X45xx** family of 10/25/40/50/100 Gbps adapters and
 **Alveo SN1000 SmartNICs** family of 10/25/40/50/100 Gbps adapters.
 SFC EFX PMD has support for the latest Linux and FreeBSD operating systems.
 
@@ -21,6 +22,12 @@ More information can be found at `Solarflare Communications website
 Supported NICs
 --------------
 
+- AMD Solarflare Adapters:
+
+   - AMD Solarflare X4522 Dual Port SFP56 Adapter
+
+   - AMD Solarflare X4542 Dual Port QSFP56 Adapter
+
 - Xilinx Adapters:
 
    - Alveo SN1022 SmartNIC
diff --git a/doc/guides/rel_notes/release_25_07.rst b/doc/guides/rel_notes/release_25_07.rst
index b8b56510f8..467536fe05 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -60,6 +60,10 @@ New Features
   Added a new network PMD which supports Mucse 10 Gigabit Ethernet NICs.
   See the :doc:`../nics/rnp` for more details.
 
+* **Updated Solarflare network PMD.**
+
+  Added support for AMD Solarflare X45xx adapters.
+
 
 Removed Items
 -------------
-- 
2.39.5

Re: [PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Stephen Hemminger]

On Wed, 16 Apr 2025 17:59:30 +0400
Ivan Malov <ivan.malov@arknetworks.am> wrote:

> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
> supports multiple network engine types. This series provides support
> only for the Medford2-alike, 'full-feature' (FF) network engine. This
> shall not be confused with the concept of 'datapath FW variants': the
> FF network engine supports both 'full-feature' and 'ultra-low-latency'
> datapath FW variants, with corresponding Medford2-alike feature sets.
> 
> The first part of the series provides general support for the adaptors,
> whilst the second one adds support for the new management controller
> interface for configuration of network port features (netport MCDI).
> 
> For now, only support for physical functions (PFs) is concerned. There
> is a small number of TODO and FIXME markings in the code. Those are
> normal at this development stage and will be removed by future patches
> when VF support has fleshed out.
> 
> 
> Andy Moreton (3):
>   common/sfc_efx/base: update X4 BAR layout and PCI IDs
>   net/sfc: add Medford4 with only full feature datapath engine
>   common/sfc_efx/base: add port mode for 8 port hardware
> 
> Denis Pryazhennikov (15):
>   common/sfc_efx/base: add Medford4 PCI IDs to common code
>   common/sfc_efx/base: add efsys option for Medford4
>   common/sfc_efx/base: add Medford4 support to NIC module
>   common/sfc_efx/base: add Medford4 support to EV module
>   common/sfc_efx/base: add Medford4 support to FILTER module
>   common/sfc_efx/base: add Medford4 support to INTR module
>   common/sfc_efx/base: add Medford4 support to MAC module
>   common/sfc_efx/base: add Medford4 support to PHY module
>   common/sfc_efx/base: add Medford4 support to TUNNEL module
>   common/sfc_efx/base: add Medford4 support to MCDI module
>   common/sfc_efx/base: add Medford4 support to Rx module
>   common/sfc_efx/base: add Medford4 support to Tx module
>   drivers: enable support for AMD Solarflare X4 adapter family
>   common/sfc_efx/base: add new X4 port mode
>   common/sfc_efx/base: extend list of supported X4 port modes
> 
> Ivan Malov (28):
>   common/sfc_efx/base: update MCDI headers
>   common/sfc_efx/base: provide a stub for basic netport attach
>   common/sfc_efx/base: provide defaults on netport attach path
>   common/sfc_efx/base: obtain assigned netport handle from NIC
>   common/sfc_efx/base: allow for const in MCDI struct accessor
>   common/sfc_efx/base: get netport fixed capabilities on probe
>   common/sfc_efx/base: decode netport link state on probe path
>   common/sfc_efx/base: fill in loopback modes on netport probe
>   common/sfc_efx/base: introduce Medford4 stub for PHY methods
>   common/sfc_efx/base: refactor EF10 link mode decoding helper
>   common/sfc_efx/base: provide PHY link get method on Medford4
>   common/sfc_efx/base: implement PHY link control for Medford4
>   common/sfc_efx/base: introduce Medford4 stub for MAC methods
>   common/sfc_efx/base: add MAC reconfigure method for Medford4
>   common/sfc_efx/base: fill in software LUT for MAC statistics
>   common/sfc_efx/base: fill in MAC statistics mask on Medford4
>   common/sfc_efx/base: support MAC statistics on Medford4 NICs
>   common/sfc_efx/base: implement MAC PDU controls for Medford4
>   common/sfc_efx/base: correct MAC PDU calculation on Medford4
>   net/sfc: make use of generic EFX MAC PDU calculation helpers
>   common/sfc_efx/base: ignore legacy link events on new boards
>   common/sfc_efx/base: add link event processing on new boards
>   net/sfc: query link status on link change events on new NICs
>   common/sfc_efx/base: subscribe to netport link change events
>   net/sfc: offer support for 200G link ability on new adaptors
>   common/sfc_efx/base: support controls for netport lane count
>   net/sfc: add support for control of physical port lane count
>   doc: advertise support for AMD Solarflare X45xx adapters
> 
>  .mailmap                                      |    3 +-
>  doc/guides/nics/sfc_efx.rst                   |    9 +-
>  doc/guides/rel_notes/release_25_07.rst        |    4 +
>  drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
>  drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
>  drivers/common/sfc_efx/base/ef10_nic.c        |   98 +-
>  drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
>  drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
>  drivers/common/sfc_efx/base/efx.h             |   98 +-
>  drivers/common/sfc_efx/base/efx_check.h       |   24 +-
>  drivers/common/sfc_efx/base/efx_ev.c          |    6 +
>  drivers/common/sfc_efx/base/efx_filter.c      |    6 +
>  drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
>  drivers/common/sfc_efx/base/efx_intr.c        |    6 +
>  drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
>  drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
>  drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
>  drivers/common/sfc_efx/base/efx_nic.c         |   60 +
>  drivers/common/sfc_efx/base/efx_np.c          | 1625 +++++
>  drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
>  drivers/common/sfc_efx/base/efx_port.c        |    1 +
>  drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
>  drivers/common/sfc_efx/base/efx_rx.c          |    6 +
>  drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
>  drivers/common/sfc_efx/base/efx_tx.c          |   33 +
>  drivers/common/sfc_efx/base/medford4_impl.h   |  110 +
>  drivers/common/sfc_efx/base/medford4_mac.c    |  299 +
>  drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
>  drivers/common/sfc_efx/base/meson.build       |    3 +
>  drivers/common/sfc_efx/efsys.h                |    2 +
>  drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
>  drivers/net/sfc/sfc.c                         |    5 +-
>  drivers/net/sfc/sfc.h                         |    4 +
>  drivers/net/sfc/sfc_dp_tx.h                   |    3 +
>  drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
>  drivers/net/sfc/sfc_ethdev.c                  |  186 +-
>  drivers/net/sfc/sfc_ev.c                      |   51 +-
>  drivers/net/sfc/sfc_port.c                    |   27 +-
>  drivers/net/sfc/sfc_repr.c                    |    7 +-
>  drivers/net/sfc/sfc_repr.h                    |    1 +
>  drivers/net/sfc/sfc_tx.c                      |    2 +
>  41 files changed, 9000 insertions(+), 125 deletions(-)
>  create mode 100644 drivers/common/sfc_efx/base/efx_np.c
>  create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
>  create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
>  create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c
> 

Overall looks good but:
  - need to fix build on FreeBSD, you are using an errno not available there.
  - can you address some of the checkpatch warnings in the base code.

Re: [PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Ivan Malov]

On Wed, 16 Apr 2025, Stephen Hemminger wrote:

> On Wed, 16 Apr 2025 17:59:30 +0400
> Ivan Malov <ivan.malov@arknetworks.am> wrote:
>
>> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
>> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
>> supports multiple network engine types. This series provides support
>> only for the Medford2-alike, 'full-feature' (FF) network engine. This
>> shall not be confused with the concept of 'datapath FW variants': the
>> FF network engine supports both 'full-feature' and 'ultra-low-latency'
>> datapath FW variants, with corresponding Medford2-alike feature sets.
>>
>> The first part of the series provides general support for the adaptors,
>> whilst the second one adds support for the new management controller
>> interface for configuration of network port features (netport MCDI).
>>
>> For now, only support for physical functions (PFs) is concerned. There
>> is a small number of TODO and FIXME markings in the code. Those are
>> normal at this development stage and will be removed by future patches
>> when VF support has fleshed out.
>>
>>
>> Andy Moreton (3):
>>   common/sfc_efx/base: update X4 BAR layout and PCI IDs
>>   net/sfc: add Medford4 with only full feature datapath engine
>>   common/sfc_efx/base: add port mode for 8 port hardware
>>
>> Denis Pryazhennikov (15):
>>   common/sfc_efx/base: add Medford4 PCI IDs to common code
>>   common/sfc_efx/base: add efsys option for Medford4
>>   common/sfc_efx/base: add Medford4 support to NIC module
>>   common/sfc_efx/base: add Medford4 support to EV module
>>   common/sfc_efx/base: add Medford4 support to FILTER module
>>   common/sfc_efx/base: add Medford4 support to INTR module
>>   common/sfc_efx/base: add Medford4 support to MAC module
>>   common/sfc_efx/base: add Medford4 support to PHY module
>>   common/sfc_efx/base: add Medford4 support to TUNNEL module
>>   common/sfc_efx/base: add Medford4 support to MCDI module
>>   common/sfc_efx/base: add Medford4 support to Rx module
>>   common/sfc_efx/base: add Medford4 support to Tx module
>>   drivers: enable support for AMD Solarflare X4 adapter family
>>   common/sfc_efx/base: add new X4 port mode
>>   common/sfc_efx/base: extend list of supported X4 port modes
>>
>> Ivan Malov (28):
>>   common/sfc_efx/base: update MCDI headers
>>   common/sfc_efx/base: provide a stub for basic netport attach
>>   common/sfc_efx/base: provide defaults on netport attach path
>>   common/sfc_efx/base: obtain assigned netport handle from NIC
>>   common/sfc_efx/base: allow for const in MCDI struct accessor
>>   common/sfc_efx/base: get netport fixed capabilities on probe
>>   common/sfc_efx/base: decode netport link state on probe path
>>   common/sfc_efx/base: fill in loopback modes on netport probe
>>   common/sfc_efx/base: introduce Medford4 stub for PHY methods
>>   common/sfc_efx/base: refactor EF10 link mode decoding helper
>>   common/sfc_efx/base: provide PHY link get method on Medford4
>>   common/sfc_efx/base: implement PHY link control for Medford4
>>   common/sfc_efx/base: introduce Medford4 stub for MAC methods
>>   common/sfc_efx/base: add MAC reconfigure method for Medford4
>>   common/sfc_efx/base: fill in software LUT for MAC statistics
>>   common/sfc_efx/base: fill in MAC statistics mask on Medford4
>>   common/sfc_efx/base: support MAC statistics on Medford4 NICs
>>   common/sfc_efx/base: implement MAC PDU controls for Medford4
>>   common/sfc_efx/base: correct MAC PDU calculation on Medford4
>>   net/sfc: make use of generic EFX MAC PDU calculation helpers
>>   common/sfc_efx/base: ignore legacy link events on new boards
>>   common/sfc_efx/base: add link event processing on new boards
>>   net/sfc: query link status on link change events on new NICs
>>   common/sfc_efx/base: subscribe to netport link change events
>>   net/sfc: offer support for 200G link ability on new adaptors
>>   common/sfc_efx/base: support controls for netport lane count
>>   net/sfc: add support for control of physical port lane count
>>   doc: advertise support for AMD Solarflare X45xx adapters
>>
>>  .mailmap                                      |    3 +-
>>  doc/guides/nics/sfc_efx.rst                   |    9 +-
>>  doc/guides/rel_notes/release_25_07.rst        |    4 +
>>  drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
>>  drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
>>  drivers/common/sfc_efx/base/ef10_nic.c        |   98 +-
>>  drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
>>  drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
>>  drivers/common/sfc_efx/base/efx.h             |   98 +-
>>  drivers/common/sfc_efx/base/efx_check.h       |   24 +-
>>  drivers/common/sfc_efx/base/efx_ev.c          |    6 +
>>  drivers/common/sfc_efx/base/efx_filter.c      |    6 +
>>  drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
>>  drivers/common/sfc_efx/base/efx_intr.c        |    6 +
>>  drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
>>  drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
>>  drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
>>  drivers/common/sfc_efx/base/efx_nic.c         |   60 +
>>  drivers/common/sfc_efx/base/efx_np.c          | 1625 +++++
>>  drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
>>  drivers/common/sfc_efx/base/efx_port.c        |    1 +
>>  drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
>>  drivers/common/sfc_efx/base/efx_rx.c          |    6 +
>>  drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
>>  drivers/common/sfc_efx/base/efx_tx.c          |   33 +
>>  drivers/common/sfc_efx/base/medford4_impl.h   |  110 +
>>  drivers/common/sfc_efx/base/medford4_mac.c    |  299 +
>>  drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
>>  drivers/common/sfc_efx/base/meson.build       |    3 +
>>  drivers/common/sfc_efx/efsys.h                |    2 +
>>  drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
>>  drivers/net/sfc/sfc.c                         |    5 +-
>>  drivers/net/sfc/sfc.h                         |    4 +
>>  drivers/net/sfc/sfc_dp_tx.h                   |    3 +
>>  drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
>>  drivers/net/sfc/sfc_ethdev.c                  |  186 +-
>>  drivers/net/sfc/sfc_ev.c                      |   51 +-
>>  drivers/net/sfc/sfc_port.c                    |   27 +-
>>  drivers/net/sfc/sfc_repr.c                    |    7 +-
>>  drivers/net/sfc/sfc_repr.h                    |    1 +
>>  drivers/net/sfc/sfc_tx.c                      |    2 +
>>  41 files changed, 9000 insertions(+), 125 deletions(-)
>>  create mode 100644 drivers/common/sfc_efx/base/efx_np.c
>>  create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
>>  create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
>>  create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c
>>
>
> Overall looks good but:
>  - need to fix build on FreeBSD, you are using an errno not available there.
>  - can you address some of the checkpatch warnings in the base code.
>

I can fix the errno, yes. Thanks for catching this.

As for the checkpatch warnings in the base code -- unfortunately, that part does
not follow DPDK style in general and has always triggered such warnings in DPDK.
Should I try to fix some anyway? Which, for instance?

Thank you.

Re: [PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Stephen Hemminger]

On Wed, 16 Apr 2025 19:38:58 +0400 (+04)
Ivan Malov <ivan.malov@arknetworks.am> wrote:

> On Wed, 16 Apr 2025, Stephen Hemminger wrote:
> 
> > On Wed, 16 Apr 2025 17:59:30 +0400
> > Ivan Malov <ivan.malov@arknetworks.am> wrote:
> >  
> >> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
> >> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
> >> supports multiple network engine types. This series provides support
> >> only for the Medford2-alike, 'full-feature' (FF) network engine. This
> >> shall not be confused with the concept of 'datapath FW variants': the
> >> FF network engine supports both 'full-feature' and 'ultra-low-latency'
> >> datapath FW variants, with corresponding Medford2-alike feature sets.
> >>
> >> The first part of the series provides general support for the adaptors,
> >> whilst the second one adds support for the new management controller
> >> interface for configuration of network port features (netport MCDI).
> >>
> >> For now, only support for physical functions (PFs) is concerned. There
> >> is a small number of TODO and FIXME markings in the code. Those are
> >> normal at this development stage and will be removed by future patches
> >> when VF support has fleshed out.
> >>
> >>
> >> Andy Moreton (3):
> >>   common/sfc_efx/base: update X4 BAR layout and PCI IDs
> >>   net/sfc: add Medford4 with only full feature datapath engine
> >>   common/sfc_efx/base: add port mode for 8 port hardware
> >>
> >> Denis Pryazhennikov (15):
> >>   common/sfc_efx/base: add Medford4 PCI IDs to common code
> >>   common/sfc_efx/base: add efsys option for Medford4
> >>   common/sfc_efx/base: add Medford4 support to NIC module
> >>   common/sfc_efx/base: add Medford4 support to EV module
> >>   common/sfc_efx/base: add Medford4 support to FILTER module
> >>   common/sfc_efx/base: add Medford4 support to INTR module
> >>   common/sfc_efx/base: add Medford4 support to MAC module
> >>   common/sfc_efx/base: add Medford4 support to PHY module
> >>   common/sfc_efx/base: add Medford4 support to TUNNEL module
> >>   common/sfc_efx/base: add Medford4 support to MCDI module
> >>   common/sfc_efx/base: add Medford4 support to Rx module
> >>   common/sfc_efx/base: add Medford4 support to Tx module
> >>   drivers: enable support for AMD Solarflare X4 adapter family
> >>   common/sfc_efx/base: add new X4 port mode
> >>   common/sfc_efx/base: extend list of supported X4 port modes
> >>
> >> Ivan Malov (28):
> >>   common/sfc_efx/base: update MCDI headers
> >>   common/sfc_efx/base: provide a stub for basic netport attach
> >>   common/sfc_efx/base: provide defaults on netport attach path
> >>   common/sfc_efx/base: obtain assigned netport handle from NIC
> >>   common/sfc_efx/base: allow for const in MCDI struct accessor
> >>   common/sfc_efx/base: get netport fixed capabilities on probe
> >>   common/sfc_efx/base: decode netport link state on probe path
> >>   common/sfc_efx/base: fill in loopback modes on netport probe
> >>   common/sfc_efx/base: introduce Medford4 stub for PHY methods
> >>   common/sfc_efx/base: refactor EF10 link mode decoding helper
> >>   common/sfc_efx/base: provide PHY link get method on Medford4
> >>   common/sfc_efx/base: implement PHY link control for Medford4
> >>   common/sfc_efx/base: introduce Medford4 stub for MAC methods
> >>   common/sfc_efx/base: add MAC reconfigure method for Medford4
> >>   common/sfc_efx/base: fill in software LUT for MAC statistics
> >>   common/sfc_efx/base: fill in MAC statistics mask on Medford4
> >>   common/sfc_efx/base: support MAC statistics on Medford4 NICs
> >>   common/sfc_efx/base: implement MAC PDU controls for Medford4
> >>   common/sfc_efx/base: correct MAC PDU calculation on Medford4
> >>   net/sfc: make use of generic EFX MAC PDU calculation helpers
> >>   common/sfc_efx/base: ignore legacy link events on new boards
> >>   common/sfc_efx/base: add link event processing on new boards
> >>   net/sfc: query link status on link change events on new NICs
> >>   common/sfc_efx/base: subscribe to netport link change events
> >>   net/sfc: offer support for 200G link ability on new adaptors
> >>   common/sfc_efx/base: support controls for netport lane count
> >>   net/sfc: add support for control of physical port lane count
> >>   doc: advertise support for AMD Solarflare X45xx adapters
> >>
> >>  .mailmap                                      |    3 +-
> >>  doc/guides/nics/sfc_efx.rst                   |    9 +-
> >>  doc/guides/rel_notes/release_25_07.rst        |    4 +
> >>  drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
> >>  drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
> >>  drivers/common/sfc_efx/base/ef10_nic.c        |   98 +-
> >>  drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
> >>  drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
> >>  drivers/common/sfc_efx/base/efx.h             |   98 +-
> >>  drivers/common/sfc_efx/base/efx_check.h       |   24 +-
> >>  drivers/common/sfc_efx/base/efx_ev.c          |    6 +
> >>  drivers/common/sfc_efx/base/efx_filter.c      |    6 +
> >>  drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
> >>  drivers/common/sfc_efx/base/efx_intr.c        |    6 +
> >>  drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
> >>  drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
> >>  drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
> >>  drivers/common/sfc_efx/base/efx_nic.c         |   60 +
> >>  drivers/common/sfc_efx/base/efx_np.c          | 1625 +++++
> >>  drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
> >>  drivers/common/sfc_efx/base/efx_port.c        |    1 +
> >>  drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
> >>  drivers/common/sfc_efx/base/efx_rx.c          |    6 +
> >>  drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
> >>  drivers/common/sfc_efx/base/efx_tx.c          |   33 +
> >>  drivers/common/sfc_efx/base/medford4_impl.h   |  110 +
> >>  drivers/common/sfc_efx/base/medford4_mac.c    |  299 +
> >>  drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
> >>  drivers/common/sfc_efx/base/meson.build       |    3 +
> >>  drivers/common/sfc_efx/efsys.h                |    2 +
> >>  drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
> >>  drivers/net/sfc/sfc.c                         |    5 +-
> >>  drivers/net/sfc/sfc.h                         |    4 +
> >>  drivers/net/sfc/sfc_dp_tx.h                   |    3 +
> >>  drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
> >>  drivers/net/sfc/sfc_ethdev.c                  |  186 +-
> >>  drivers/net/sfc/sfc_ev.c                      |   51 +-
> >>  drivers/net/sfc/sfc_port.c                    |   27 +-
> >>  drivers/net/sfc/sfc_repr.c                    |    7 +-
> >>  drivers/net/sfc/sfc_repr.h                    |    1 +
> >>  drivers/net/sfc/sfc_tx.c                      |    2 +
> >>  41 files changed, 9000 insertions(+), 125 deletions(-)
> >>  create mode 100644 drivers/common/sfc_efx/base/efx_np.c
> >>  create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
> >>  create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
> >>  create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c
> >>  
> >
> > Overall looks good but:
> >  - need to fix build on FreeBSD, you are using an errno not available there.
> >  - can you address some of the checkpatch warnings in the base code.
> >  
> 
> I can fix the errno, yes. Thanks for catching this.
> 
> As for the checkpatch warnings in the base code -- unfortunately, that part does
> not follow DPDK style in general and has always triggered such warnings in DPDK.
> Should I try to fix some anyway? Which, for instance?

Mostly it is the use of BSD style parens on returns that clutters the warnings.
I.e
	return (0);

Re: [PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Ivan Malov]

On Wed, 16 Apr 2025, Stephen Hemminger wrote:

> On Wed, 16 Apr 2025 19:38:58 +0400 (+04)
> Ivan Malov <ivan.malov@arknetworks.am> wrote:
>
>> On Wed, 16 Apr 2025, Stephen Hemminger wrote:
>>
>>> On Wed, 16 Apr 2025 17:59:30 +0400
>>> Ivan Malov <ivan.malov@arknetworks.am> wrote:
>>>
>>>> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
>>>> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
>>>> supports multiple network engine types. This series provides support
>>>> only for the Medford2-alike, 'full-feature' (FF) network engine. This
>>>> shall not be confused with the concept of 'datapath FW variants': the
>>>> FF network engine supports both 'full-feature' and 'ultra-low-latency'
>>>> datapath FW variants, with corresponding Medford2-alike feature sets.
>>>>
>>>> The first part of the series provides general support for the adaptors,
>>>> whilst the second one adds support for the new management controller
>>>> interface for configuration of network port features (netport MCDI).
>>>>
>>>> For now, only support for physical functions (PFs) is concerned. There
>>>> is a small number of TODO and FIXME markings in the code. Those are
>>>> normal at this development stage and will be removed by future patches
>>>> when VF support has fleshed out.
>>>>
>>>>
>>>> Andy Moreton (3):
>>>>   common/sfc_efx/base: update X4 BAR layout and PCI IDs
>>>>   net/sfc: add Medford4 with only full feature datapath engine
>>>>   common/sfc_efx/base: add port mode for 8 port hardware
>>>>
>>>> Denis Pryazhennikov (15):
>>>>   common/sfc_efx/base: add Medford4 PCI IDs to common code
>>>>   common/sfc_efx/base: add efsys option for Medford4
>>>>   common/sfc_efx/base: add Medford4 support to NIC module
>>>>   common/sfc_efx/base: add Medford4 support to EV module
>>>>   common/sfc_efx/base: add Medford4 support to FILTER module
>>>>   common/sfc_efx/base: add Medford4 support to INTR module
>>>>   common/sfc_efx/base: add Medford4 support to MAC module
>>>>   common/sfc_efx/base: add Medford4 support to PHY module
>>>>   common/sfc_efx/base: add Medford4 support to TUNNEL module
>>>>   common/sfc_efx/base: add Medford4 support to MCDI module
>>>>   common/sfc_efx/base: add Medford4 support to Rx module
>>>>   common/sfc_efx/base: add Medford4 support to Tx module
>>>>   drivers: enable support for AMD Solarflare X4 adapter family
>>>>   common/sfc_efx/base: add new X4 port mode
>>>>   common/sfc_efx/base: extend list of supported X4 port modes
>>>>
>>>> Ivan Malov (28):
>>>>   common/sfc_efx/base: update MCDI headers
>>>>   common/sfc_efx/base: provide a stub for basic netport attach
>>>>   common/sfc_efx/base: provide defaults on netport attach path
>>>>   common/sfc_efx/base: obtain assigned netport handle from NIC
>>>>   common/sfc_efx/base: allow for const in MCDI struct accessor
>>>>   common/sfc_efx/base: get netport fixed capabilities on probe
>>>>   common/sfc_efx/base: decode netport link state on probe path
>>>>   common/sfc_efx/base: fill in loopback modes on netport probe
>>>>   common/sfc_efx/base: introduce Medford4 stub for PHY methods
>>>>   common/sfc_efx/base: refactor EF10 link mode decoding helper
>>>>   common/sfc_efx/base: provide PHY link get method on Medford4
>>>>   common/sfc_efx/base: implement PHY link control for Medford4
>>>>   common/sfc_efx/base: introduce Medford4 stub for MAC methods
>>>>   common/sfc_efx/base: add MAC reconfigure method for Medford4
>>>>   common/sfc_efx/base: fill in software LUT for MAC statistics
>>>>   common/sfc_efx/base: fill in MAC statistics mask on Medford4
>>>>   common/sfc_efx/base: support MAC statistics on Medford4 NICs
>>>>   common/sfc_efx/base: implement MAC PDU controls for Medford4
>>>>   common/sfc_efx/base: correct MAC PDU calculation on Medford4
>>>>   net/sfc: make use of generic EFX MAC PDU calculation helpers
>>>>   common/sfc_efx/base: ignore legacy link events on new boards
>>>>   common/sfc_efx/base: add link event processing on new boards
>>>>   net/sfc: query link status on link change events on new NICs
>>>>   common/sfc_efx/base: subscribe to netport link change events
>>>>   net/sfc: offer support for 200G link ability on new adaptors
>>>>   common/sfc_efx/base: support controls for netport lane count
>>>>   net/sfc: add support for control of physical port lane count
>>>>   doc: advertise support for AMD Solarflare X45xx adapters
>>>>
>>>>  .mailmap                                      |    3 +-
>>>>  doc/guides/nics/sfc_efx.rst                   |    9 +-
>>>>  doc/guides/rel_notes/release_25_07.rst        |    4 +
>>>>  drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
>>>>  drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
>>>>  drivers/common/sfc_efx/base/ef10_nic.c        |   98 +-
>>>>  drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
>>>>  drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
>>>>  drivers/common/sfc_efx/base/efx.h             |   98 +-
>>>>  drivers/common/sfc_efx/base/efx_check.h       |   24 +-
>>>>  drivers/common/sfc_efx/base/efx_ev.c          |    6 +
>>>>  drivers/common/sfc_efx/base/efx_filter.c      |    6 +
>>>>  drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
>>>>  drivers/common/sfc_efx/base/efx_intr.c        |    6 +
>>>>  drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
>>>>  drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
>>>>  drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
>>>>  drivers/common/sfc_efx/base/efx_nic.c         |   60 +
>>>>  drivers/common/sfc_efx/base/efx_np.c          | 1625 +++++
>>>>  drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
>>>>  drivers/common/sfc_efx/base/efx_port.c        |    1 +
>>>>  drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
>>>>  drivers/common/sfc_efx/base/efx_rx.c          |    6 +
>>>>  drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
>>>>  drivers/common/sfc_efx/base/efx_tx.c          |   33 +
>>>>  drivers/common/sfc_efx/base/medford4_impl.h   |  110 +
>>>>  drivers/common/sfc_efx/base/medford4_mac.c    |  299 +
>>>>  drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
>>>>  drivers/common/sfc_efx/base/meson.build       |    3 +
>>>>  drivers/common/sfc_efx/efsys.h                |    2 +
>>>>  drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
>>>>  drivers/net/sfc/sfc.c                         |    5 +-
>>>>  drivers/net/sfc/sfc.h                         |    4 +
>>>>  drivers/net/sfc/sfc_dp_tx.h                   |    3 +
>>>>  drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
>>>>  drivers/net/sfc/sfc_ethdev.c                  |  186 +-
>>>>  drivers/net/sfc/sfc_ev.c                      |   51 +-
>>>>  drivers/net/sfc/sfc_port.c                    |   27 +-
>>>>  drivers/net/sfc/sfc_repr.c                    |    7 +-
>>>>  drivers/net/sfc/sfc_repr.h                    |    1 +
>>>>  drivers/net/sfc/sfc_tx.c                      |    2 +
>>>>  41 files changed, 9000 insertions(+), 125 deletions(-)
>>>>  create mode 100644 drivers/common/sfc_efx/base/efx_np.c
>>>>  create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
>>>>  create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
>>>>  create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c
>>>>
>>>
>>> Overall looks good but:
>>>  - need to fix build on FreeBSD, you are using an errno not available there.
>>>  - can you address some of the checkpatch warnings in the base code.
>>>
>>
>> I can fix the errno, yes. Thanks for catching this.
>>
>> As for the checkpatch warnings in the base code -- unfortunately, that part does
>> not follow DPDK style in general and has always triggered such warnings in DPDK.
>> Should I try to fix some anyway? Which, for instance?
>
> Mostly it is the use of BSD style parens on returns that clutters the warnings.
> I.e
> 	return (0);

I see. Unfortunately, this, as well as space character in 'sizeof ()', follows
the base driver's own style and it has been so for a long time. May be it is
acceptable to retain it. But I do care to comply with DPDK conventions in the
SFC driver itself. So shall I fix ENODATA->ENODEV and send v2?

Thank you.

Re: [PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Stephen Hemminger]

On Wed, 16 Apr 2025 21:37:09 +0400 (+04)
Ivan Malov <ivan.malov@arknetworks.am> wrote:

> On Wed, 16 Apr 2025, Stephen Hemminger wrote:
> 
> > On Wed, 16 Apr 2025 19:38:58 +0400 (+04)
> > Ivan Malov <ivan.malov@arknetworks.am> wrote:
> >  
> >> On Wed, 16 Apr 2025, Stephen Hemminger wrote:
> >>  
> >>> On Wed, 16 Apr 2025 17:59:30 +0400
> >>> Ivan Malov <ivan.malov@arknetworks.am> wrote:
> >>>  
> >>>> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
> >>>> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
> >>>> supports multiple network engine types. This series provides support
> >>>> only for the Medford2-alike, 'full-feature' (FF) network engine. This
> >>>> shall not be confused with the concept of 'datapath FW variants': the
> >>>> FF network engine supports both 'full-feature' and 'ultra-low-latency'
> >>>> datapath FW variants, with corresponding Medford2-alike feature sets.
> >>>>
> >>>> The first part of the series provides general support for the adaptors,
> >>>> whilst the second one adds support for the new management controller
> >>>> interface for configuration of network port features (netport MCDI).
> >>>>
> >>>> For now, only support for physical functions (PFs) is concerned. There
> >>>> is a small number of TODO and FIXME markings in the code. Those are
> >>>> normal at this development stage and will be removed by future patches
> >>>> when VF support has fleshed out.
> >>>>
> >>>>
> >>>> Andy Moreton (3):
> >>>>   common/sfc_efx/base: update X4 BAR layout and PCI IDs
> >>>>   net/sfc: add Medford4 with only full feature datapath engine
> >>>>   common/sfc_efx/base: add port mode for 8 port hardware
> >>>>
> >>>> Denis Pryazhennikov (15):
> >>>>   common/sfc_efx/base: add Medford4 PCI IDs to common code
> >>>>   common/sfc_efx/base: add efsys option for Medford4
> >>>>   common/sfc_efx/base: add Medford4 support to NIC module
> >>>>   common/sfc_efx/base: add Medford4 support to EV module
> >>>>   common/sfc_efx/base: add Medford4 support to FILTER module
> >>>>   common/sfc_efx/base: add Medford4 support to INTR module
> >>>>   common/sfc_efx/base: add Medford4 support to MAC module
> >>>>   common/sfc_efx/base: add Medford4 support to PHY module
> >>>>   common/sfc_efx/base: add Medford4 support to TUNNEL module
> >>>>   common/sfc_efx/base: add Medford4 support to MCDI module
> >>>>   common/sfc_efx/base: add Medford4 support to Rx module
> >>>>   common/sfc_efx/base: add Medford4 support to Tx module
> >>>>   drivers: enable support for AMD Solarflare X4 adapter family
> >>>>   common/sfc_efx/base: add new X4 port mode
> >>>>   common/sfc_efx/base: extend list of supported X4 port modes
> >>>>
> >>>> Ivan Malov (28):
> >>>>   common/sfc_efx/base: update MCDI headers
> >>>>   common/sfc_efx/base: provide a stub for basic netport attach
> >>>>   common/sfc_efx/base: provide defaults on netport attach path
> >>>>   common/sfc_efx/base: obtain assigned netport handle from NIC
> >>>>   common/sfc_efx/base: allow for const in MCDI struct accessor
> >>>>   common/sfc_efx/base: get netport fixed capabilities on probe
> >>>>   common/sfc_efx/base: decode netport link state on probe path
> >>>>   common/sfc_efx/base: fill in loopback modes on netport probe
> >>>>   common/sfc_efx/base: introduce Medford4 stub for PHY methods
> >>>>   common/sfc_efx/base: refactor EF10 link mode decoding helper
> >>>>   common/sfc_efx/base: provide PHY link get method on Medford4
> >>>>   common/sfc_efx/base: implement PHY link control for Medford4
> >>>>   common/sfc_efx/base: introduce Medford4 stub for MAC methods
> >>>>   common/sfc_efx/base: add MAC reconfigure method for Medford4
> >>>>   common/sfc_efx/base: fill in software LUT for MAC statistics
> >>>>   common/sfc_efx/base: fill in MAC statistics mask on Medford4
> >>>>   common/sfc_efx/base: support MAC statistics on Medford4 NICs
> >>>>   common/sfc_efx/base: implement MAC PDU controls for Medford4
> >>>>   common/sfc_efx/base: correct MAC PDU calculation on Medford4
> >>>>   net/sfc: make use of generic EFX MAC PDU calculation helpers
> >>>>   common/sfc_efx/base: ignore legacy link events on new boards
> >>>>   common/sfc_efx/base: add link event processing on new boards
> >>>>   net/sfc: query link status on link change events on new NICs
> >>>>   common/sfc_efx/base: subscribe to netport link change events
> >>>>   net/sfc: offer support for 200G link ability on new adaptors
> >>>>   common/sfc_efx/base: support controls for netport lane count
> >>>>   net/sfc: add support for control of physical port lane count
> >>>>   doc: advertise support for AMD Solarflare X45xx adapters
> >>>>
> >>>>  .mailmap                                      |    3 +-
> >>>>  doc/guides/nics/sfc_efx.rst                   |    9 +-
> >>>>  doc/guides/rel_notes/release_25_07.rst        |    4 +
> >>>>  drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
> >>>>  drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
> >>>>  drivers/common/sfc_efx/base/ef10_nic.c        |   98 +-
> >>>>  drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
> >>>>  drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
> >>>>  drivers/common/sfc_efx/base/efx.h             |   98 +-
> >>>>  drivers/common/sfc_efx/base/efx_check.h       |   24 +-
> >>>>  drivers/common/sfc_efx/base/efx_ev.c          |    6 +
> >>>>  drivers/common/sfc_efx/base/efx_filter.c      |    6 +
> >>>>  drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
> >>>>  drivers/common/sfc_efx/base/efx_intr.c        |    6 +
> >>>>  drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
> >>>>  drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
> >>>>  drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
> >>>>  drivers/common/sfc_efx/base/efx_nic.c         |   60 +
> >>>>  drivers/common/sfc_efx/base/efx_np.c          | 1625 +++++
> >>>>  drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
> >>>>  drivers/common/sfc_efx/base/efx_port.c        |    1 +
> >>>>  drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
> >>>>  drivers/common/sfc_efx/base/efx_rx.c          |    6 +
> >>>>  drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
> >>>>  drivers/common/sfc_efx/base/efx_tx.c          |   33 +
> >>>>  drivers/common/sfc_efx/base/medford4_impl.h   |  110 +
> >>>>  drivers/common/sfc_efx/base/medford4_mac.c    |  299 +
> >>>>  drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
> >>>>  drivers/common/sfc_efx/base/meson.build       |    3 +
> >>>>  drivers/common/sfc_efx/efsys.h                |    2 +
> >>>>  drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
> >>>>  drivers/net/sfc/sfc.c                         |    5 +-
> >>>>  drivers/net/sfc/sfc.h                         |    4 +
> >>>>  drivers/net/sfc/sfc_dp_tx.h                   |    3 +
> >>>>  drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
> >>>>  drivers/net/sfc/sfc_ethdev.c                  |  186 +-
> >>>>  drivers/net/sfc/sfc_ev.c                      |   51 +-
> >>>>  drivers/net/sfc/sfc_port.c                    |   27 +-
> >>>>  drivers/net/sfc/sfc_repr.c                    |    7 +-
> >>>>  drivers/net/sfc/sfc_repr.h                    |    1 +
> >>>>  drivers/net/sfc/sfc_tx.c                      |    2 +
> >>>>  41 files changed, 9000 insertions(+), 125 deletions(-)
> >>>>  create mode 100644 drivers/common/sfc_efx/base/efx_np.c
> >>>>  create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
> >>>>  create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
> >>>>  create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c
> >>>>  
> >>>
> >>> Overall looks good but:
> >>>  - need to fix build on FreeBSD, you are using an errno not available there.
> >>>  - can you address some of the checkpatch warnings in the base code.
> >>>  
> >>
> >> I can fix the errno, yes. Thanks for catching this.
> >>
> >> As for the checkpatch warnings in the base code -- unfortunately, that part does
> >> not follow DPDK style in general and has always triggered such warnings in DPDK.
> >> Should I try to fix some anyway? Which, for instance?  
> >
> > Mostly it is the use of BSD style parens on returns that clutters the warnings.
> > I.e
> > 	return (0);  
> 
> I see. Unfortunately, this, as well as space character in 'sizeof ()', follows
> the base driver's own style and it has been so for a long time. May be it is
> acceptable to retain it. But I do care to comply with DPDK conventions in the
> SFC driver itself. So shall I fix ENODATA->ENODEV and send v2?

As long as isn't too weird, base code can follow a slightly different set
of rules. Please send v2 and do a test build on FreeBSD (in a vm is fine).

Re: [PATCH 00/46] Support AMD Solarflare X45xx adaptors

[Andrew Rybchenko]

On 4/16/25 16:59, Ivan Malov wrote:
> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
> supports multiple network engine types. This series provides support
> only for the Medford2-alike, 'full-feature' (FF) network engine. This
> shall not be confused with the concept of 'datapath FW variants': the
> FF network engine supports both 'full-feature' and 'ultra-low-latency'
> datapath FW variants, with corresponding Medford2-alike feature sets.
> 
> The first part of the series provides general support for the adaptors,
> whilst the second one adds support for the new management controller
> interface for configuration of network port features (netport MCDI).
> 
> For now, only support for physical functions (PFs) is concerned. There
> is a small number of TODO and FIXME markings in the code. Those are
> normal at this development stage and will be removed by future patches
> when VF support has fleshed out.

In fact number of TODO and FIXME is frightening. But it is up to you.

Other than that, there are few nits in patches.
Overall looks good.

> Andy Moreton (3):
>    common/sfc_efx/base: update X4 BAR layout and PCI IDs
>    net/sfc: add Medford4 with only full feature datapath engine
>    common/sfc_efx/base: add port mode for 8 port hardware
> 
> Denis Pryazhennikov (15):
>    common/sfc_efx/base: add Medford4 PCI IDs to common code
>    common/sfc_efx/base: add efsys option for Medford4
>    common/sfc_efx/base: add Medford4 support to NIC module
>    common/sfc_efx/base: add Medford4 support to EV module
>    common/sfc_efx/base: add Medford4 support to FILTER module
>    common/sfc_efx/base: add Medford4 support to INTR module
>    common/sfc_efx/base: add Medford4 support to MAC module
>    common/sfc_efx/base: add Medford4 support to PHY module
>    common/sfc_efx/base: add Medford4 support to TUNNEL module
>    common/sfc_efx/base: add Medford4 support to MCDI module
>    common/sfc_efx/base: add Medford4 support to Rx module
>    common/sfc_efx/base: add Medford4 support to Tx module
>    drivers: enable support for AMD Solarflare X4 adapter family
>    common/sfc_efx/base: add new X4 port mode
>    common/sfc_efx/base: extend list of supported X4 port modes
> 
> Ivan Malov (28):
>    common/sfc_efx/base: update MCDI headers

Hm, bug here. End column is not aligned :)

>    common/sfc_efx/base: provide a stub for basic netport attach
>    common/sfc_efx/base: provide defaults on netport attach path
>    common/sfc_efx/base: obtain assigned netport handle from NIC
>    common/sfc_efx/base: allow for const in MCDI struct accessor
>    common/sfc_efx/base: get netport fixed capabilities on probe
>    common/sfc_efx/base: decode netport link state on probe path
>    common/sfc_efx/base: fill in loopback modes on netport probe
>    common/sfc_efx/base: introduce Medford4 stub for PHY methods
>    common/sfc_efx/base: refactor EF10 link mode decoding helper
>    common/sfc_efx/base: provide PHY link get method on Medford4
>    common/sfc_efx/base: implement PHY link control for Medford4
>    common/sfc_efx/base: introduce Medford4 stub for MAC methods
>    common/sfc_efx/base: add MAC reconfigure method for Medford4
>    common/sfc_efx/base: fill in software LUT for MAC statistics
>    common/sfc_efx/base: fill in MAC statistics mask on Medford4
>    common/sfc_efx/base: support MAC statistics on Medford4 NICs
>    common/sfc_efx/base: implement MAC PDU controls for Medford4
>    common/sfc_efx/base: correct MAC PDU calculation on Medford4
>    net/sfc: make use of generic EFX MAC PDU calculation helpers
>    common/sfc_efx/base: ignore legacy link events on new boards
>    common/sfc_efx/base: add link event processing on new boards
>    net/sfc: query link status on link change events on new NICs
>    common/sfc_efx/base: subscribe to netport link change events
>    net/sfc: offer support for 200G link ability on new adaptors
>    common/sfc_efx/base: support controls for netport lane count
>    net/sfc: add support for control of physical port lane count
>    doc: advertise support for AMD Solarflare X45xx adapters

Same here

[PATCH v2 00/45] Support AMD Solarflare X45xx adaptors

[Ivan Malov]

New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
supports multiple network engine types. This series provides support
only for the Medford2-alike, 'full-feature' (FF) network engine. This
shall not be confused with the concept of 'datapath FW variants': the
FF network engine supports both 'full-feature' and 'ultra-low-latency'
datapath FW variants, with corresponding Medford2-alike feature sets.

The first part of the series provides general support for the adaptors,
whilst the second one adds support for the new management controller
interface for configuration of network port features (netport MCDI).

For now, only support for physical functions (PFs) is concerned. There
is a small number of TODO and FIXME markings in the code. Those are
normal at this development stage and will be removed by future patches
when VF support has fleshed out.

v2:
- squashed respective parts of commit [1] into commits [2] and [3]
- dropped irrelevant TODO and FIXME markings from the patches
- applied review notes and tested build in FreeBSD14-64

[1] https://mails.dpdk.org/archives/dev/2025-April/317109.html
[2] https://mails.dpdk.org/archives/dev/2025-April/317096.html
[3] https://mails.dpdk.org/archives/dev/2025-April/317098.html


Andy Moreton (2):
  net/sfc: add Medford4 with only full feature datapath engine
  common/sfc_efx/base: add port mode for 8 port hardware

Denis Pryazhennikov (15):
  common/sfc_efx/base: add Medford4 PCI IDs to common code
  common/sfc_efx/base: add efsys option for Medford4
  common/sfc_efx/base: add Medford4 support to NIC module
  common/sfc_efx/base: add Medford4 support to EV module
  common/sfc_efx/base: add Medford4 support to FILTER module
  common/sfc_efx/base: add Medford4 support to INTR module
  common/sfc_efx/base: add Medford4 support to MAC module
  common/sfc_efx/base: add Medford4 support to PHY module
  common/sfc_efx/base: add Medford4 support to TUNNEL module
  common/sfc_efx/base: add Medford4 support to MCDI module
  common/sfc_efx/base: add Medford4 support to Rx module
  common/sfc_efx/base: add Medford4 support to Tx module
  drivers: enable support for AMD Solarflare X4 adapter family
  common/sfc_efx/base: add new X4 port mode
  common/sfc_efx/base: extend list of supported X4 port modes

Ivan Malov (28):
  common/sfc_efx/base: update MCDI headers
  common/sfc_efx/base: provide a stub for basic netport attach
  common/sfc_efx/base: provide defaults on netport attach path
  common/sfc_efx/base: obtain assigned netport handle from NIC
  common/sfc_efx/base: allow for const in MCDI struct accessor
  common/sfc_efx/base: get netport fixed capabilities on probe
  common/sfc_efx/base: decode netport link state on probe path
  common/sfc_efx/base: fill in loopback modes on netport probe
  common/sfc_efx/base: introduce Medford4 stub for PHY methods
  common/sfc_efx/base: refactor EF10 link mode decoding helper
  common/sfc_efx/base: provide PHY link get method on Medford4
  common/sfc_efx/base: implement PHY link control for Medford4
  common/sfc_efx/base: introduce Medford4 stub for MAC methods
  common/sfc_efx/base: add MAC reconfigure method for Medford4
  common/sfc_efx/base: fill in software LUT for MAC statistics
  common/sfc_efx/base: fill in MAC statistics mask on Medford4
  common/sfc_efx/base: support MAC statistics on Medford4 NICs
  common/sfc_efx/base: implement MAC PDU controls for Medford4
  common/sfc_efx/base: correct MAC PDU calculation on Medford4
  net/sfc: make use of generic EFX MAC PDU calculation helpers
  common/sfc_efx/base: ignore legacy link events on new boards
  common/sfc_efx/base: add link event processing on new boards
  net/sfc: query link status on link change events on new NICs
  common/sfc_efx/base: subscribe to netport link change events
  net/sfc: offer support for 200G link ability on new adaptors
  common/sfc_efx/base: support controls for netport lane count
  net/sfc: add support for control of physical port lane count
  doc: advertise support for AMD Solarflare X45xx adapters

 .mailmap                                      |    3 +-
 doc/guides/nics/sfc_efx.rst                   |    9 +-
 doc/guides/rel_notes/release_25_07.rst        |    4 +
 drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
 drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
 drivers/common/sfc_efx/base/ef10_nic.c        |   93 +-
 drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
 drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
 drivers/common/sfc_efx/base/efx.h             |   98 +-
 drivers/common/sfc_efx/base/efx_check.h       |   25 +-
 drivers/common/sfc_efx/base/efx_ev.c          |    6 +
 drivers/common/sfc_efx/base/efx_filter.c      |    6 +
 drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
 drivers/common/sfc_efx/base/efx_intr.c        |    6 +
 drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
 drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
 drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
 drivers/common/sfc_efx/base/efx_nic.c         |   60 +
 drivers/common/sfc_efx/base/efx_np.c          | 1591 +++++
 drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
 drivers/common/sfc_efx/base/efx_port.c        |    1 +
 drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
 drivers/common/sfc_efx/base/efx_rx.c          |    6 +
 drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
 drivers/common/sfc_efx/base/efx_tx.c          |   33 +
 drivers/common/sfc_efx/base/medford4_impl.h   |  105 +
 drivers/common/sfc_efx/base/medford4_mac.c    |  286 +
 drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
 drivers/common/sfc_efx/base/meson.build       |    3 +
 drivers/common/sfc_efx/efsys.h                |    2 +
 drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
 drivers/net/sfc/sfc.c                         |    5 +-
 drivers/net/sfc/sfc.h                         |    4 +
 drivers/net/sfc/sfc_dp_tx.h                   |    3 +
 drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
 drivers/net/sfc/sfc_ethdev.c                  |  186 +-
 drivers/net/sfc/sfc_ev.c                      |   51 +-
 drivers/net/sfc/sfc_port.c                    |   27 +-
 drivers/net/sfc/sfc_repr.c                    |    7 +-
 drivers/net/sfc/sfc_repr.h                    |    1 +
 drivers/net/sfc/sfc_tx.c                      |    2 +
 41 files changed, 8944 insertions(+), 125 deletions(-)
 create mode 100644 drivers/common/sfc_efx/base/efx_np.c
 create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
 create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
 create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c

-- 
2.39.5

[PATCH v2 01/45] common/sfc_efx/base: add Medford4 PCI IDs to common code

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Later patches will use this to implement support for Medford4.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Signed-off-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 5773cb00b3..635b44ab37 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -64,6 +64,7 @@ typedef enum efx_family_e {
 	EFX_FAMILY_MEDFORD,
 	EFX_FAMILY_MEDFORD2,
 	EFX_FAMILY_RIVERHEAD,
+	EFX_FAMILY_MEDFORD4,
 	EFX_FAMILY_NTYPES
 } efx_family_t;
 
@@ -172,6 +173,16 @@ efx_family_probe_bar(
 #define	EFX_PCI_DEVID_RIVERHEAD			0x0100
 #define	EFX_PCI_DEVID_RIVERHEAD_VF		0x1100
 
+/*
+ * Medford4 has low latency (LL) and full feature (FF) datapath engines.
+ * Some Medford4 functions have FF and LL datapath, others only have FF.
+ */
+#define	EFX_PCI_DEVID_MEDFORD4_PF_UNINIT	0x0C13
+#define	EFX_PCI_DEVID_MEDFORD4			0x0C03	/* X4 PF, FF+LL */
+#define	EFX_PCI_DEVID_MEDFORD4_VF		0x1C03	/* X4 VF, FF+LL */
+#define	EFX_PCI_DEVID_MEDFORD4_NO_LL		0x2C03	/* X4 PF, FF only */
+#define	EFX_PCI_DEVID_MEDFORD4_NO_LL_VF		0x3C03	/* X4 VF, FF only */
+
 #define	EFX_MEM_BAR_SIENA			2
 
 #define	EFX_MEM_BAR_HUNTINGTON_PF		2
-- 
2.39.5

[PATCH v2 02/45] common/sfc_efx/base: add efsys option for Medford4

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Later patches will use this to implement support for Medford4.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_check.h | 25 ++++++++++++++-----------
 drivers/common/sfc_efx/efsys.h          |  2 ++
 2 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_check.h b/drivers/common/sfc_efx/base/efx_check.h
index 66b38eeae0..0035ff732b 100644
--- a/drivers/common/sfc_efx/base/efx_check.h
+++ b/drivers/common/sfc_efx/base/efx_check.h
@@ -32,7 +32,8 @@
 
 /* Check family options for EF10 architecture controllers. */
 #define	EFX_OPTS_EF10()	\
-	(EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
+	(EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
+	EFSYS_OPT_MEDFORD4)
 
 #ifdef EFSYS_OPT_FALCON
 # error "FALCON is obsolete and is not supported."
@@ -197,8 +198,8 @@
 
 #if EFSYS_OPT_IMAGE_LAYOUT
 /* Support signed image layout handling */
-# if !(EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
-#  error "IMAGE_LAYOUT requires MEDFORD or MEDFORD2"
+# if !(EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
+#  error "IMAGE_LAYOUT requires MEDFORD or MEDFORD2 or MEDFORD4"
 # endif
 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
 
@@ -338,8 +339,9 @@
 
 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
 /* Support adapters with missing static config (for factory use only) */
-# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
-#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2"
+# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
+	EFSYS_OPT_MEDFORD4)
+#  error "ALLOW_UNCONFIGURED_NIC requires RIVERHEAD or MEDFORD or MEDFORD2 or MEDFORD4"
 # endif
 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
 
@@ -352,22 +354,23 @@
 
 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 /* Support equal stride super-buffer mode */
-# if !(EFSYS_OPT_MEDFORD2)
-#  error "ES_SUPER_BUFFER requires MEDFORD2"
+# if !(EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
+#  error "ES_SUPER_BUFFER requires MEDFORD2 or MEDFORD4"
 # endif
 #endif
 
 /* Support hardware assistance for tunnels */
 #if EFSYS_OPT_TUNNEL
-# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
-#  error "TUNNEL requires RIVERHEAD or MEDFORD or MEDFORD2"
+# if !(EFSYS_OPT_RIVERHEAD || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || \
+	EFSYS_OPT_MEDFORD4)
+#  error "TUNNEL requires RIVERHEAD or MEDFORD or MEDFORD2 or MEDFORD4"
 # endif
 #endif /* EFSYS_OPT_TUNNEL */
 
 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
 /* Advertise that the driver is firmware subvariant aware */
-# if !(EFSYS_OPT_MEDFORD2)
-#  error "FW_SUBVARIANT_AWARE requires MEDFORD2"
+# if !(EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4)
+#  error "FW_SUBVARIANT_AWARE requires MEDFORD2 or MEDFORD4"
 # endif
 #endif
 
diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h
index 41fa3da762..e63cbdbe8f 100644
--- a/drivers/common/sfc_efx/efsys.h
+++ b/drivers/common/sfc_efx/efsys.h
@@ -125,6 +125,8 @@ prefetch_read_once(const volatile void *addr)
 #define EFSYS_OPT_MEDFORD2 1
 /* Enable Riverhead support */
 #define EFSYS_OPT_RIVERHEAD 1
+/* Disable Medford4 support (not supported yet) */
+#define EFSYS_OPT_MEDFORD4 0
 
 #ifdef RTE_DEBUG_COMMON_SFC_EFX
 #define EFSYS_OPT_CHECK_REG 1
-- 
2.39.5

[PATCH v2 03/45] common/sfc_efx/base: add Medford4 support to NIC module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Implement NIC family discovery and minimum probe support.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Signed-off-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/ef10_nic.c | 32 +++++++++++++++-
 drivers/common/sfc_efx/base/efx.h      |  1 +
 drivers/common/sfc_efx/base/efx_impl.h |  7 +++-
 drivers/common/sfc_efx/base/efx_nic.c  | 52 ++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 79d596b5ef..9bff68f054 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1422,7 +1422,7 @@ ef10_get_datapath_caps(
 
 	/*
 	 * Check if firmware reports the VI window mode.
-	 * Medford2 has a variable VI window size (8K, 16K or 64K).
+	 * Medford2 and Medford4 have a variable VI window size (8K, 16K or 64K).
 	 * Medford and Huntington have a fixed 8K VI window size.
 	 */
 	if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
@@ -1479,6 +1479,7 @@ ef10_get_datapath_caps(
 
 		switch (enp->en_family) {
 		case EFX_FAMILY_MEDFORD2:
+		case EFX_FAMILY_MEDFORD4:
 			encp->enc_rx_scale_hash_alg_mask =
 			    (1U << EFX_RX_HASHALG_TOEPLITZ);
 			break;
@@ -1922,6 +1923,35 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_1x1_1x1),			/* mode 2 */
 		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Medford4 allocate 2 adjacent port numbers to cage 1
+	 * and the rest to cage 2.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 1
+	 *	port 2 -> cage 2
+	 *	port 3 -> cage 2
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_2x1_2x1) |			/* mode 5 */
+		(1U << TLV_PORT_MODE_2x1_1x4) |			/* mode 7 */
+		(1U << TLV_PORT_MODE_2x2_NA) |			/* mode 13 */
+		(1U << TLV_PORT_MODE_2x1_1x2),			/* mode 18 */
+		{ 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
+	/*
+	 * Modes that on Medford4 allocate up to 4 adjacent port numbers
+	 * to cage 1.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 1
+	 *	port 2 -> cage 1
+	 *	port 3 -> cage 1
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_4x1_NA),			/* mode 4 */
+		{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
 };
 
 static	__checkReturn	efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 635b44ab37..a9ed3f423f 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -196,6 +196,7 @@ efx_family_probe_bar(
 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
 #define	EFX_MEM_BAR_RIVERHEAD			2
 
+#define	EFX_MEM_BAR_MEDFORD4			2
 
 /* Error codes */
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 662a21e90c..9d1f361c5d 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -972,7 +972,8 @@ struct efx_nic_s {
 };
 
 #define	EFX_FAMILY_IS_EF10(_enp) \
-	((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
+	((_enp)->en_family == EFX_FAMILY_MEDFORD4 || \
+	 (_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 	 (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 	 (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 
@@ -1128,6 +1129,10 @@ struct efx_txq_s {
 			rev = 'G';					\
 			break;						\
 									\
+		case EFX_FAMILY_MEDFORD4:				\
+			rev = 'H';					\
+			break;						\
+									\
 		default:						\
 			rev = '?';					\
 			break;						\
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 172488e083..1ec684da40 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -79,6 +79,21 @@ efx_family(
 			return (0);
 #endif /* EFSYS_OPT_MEDFORD2 */
 
+#if EFSYS_OPT_MEDFORD4
+		case EFX_PCI_DEVID_MEDFORD4_PF_UNINIT:
+			/*
+			 * Hardware default for PF0 of uninitialised Medford4.
+			 * manftest must be able to cope with this device id.
+			 */
+		case EFX_PCI_DEVID_MEDFORD4:
+		case EFX_PCI_DEVID_MEDFORD4_VF:
+		case EFX_PCI_DEVID_MEDFORD4_NO_LL:
+		case EFX_PCI_DEVID_MEDFORD4_NO_LL_VF:
+			*efp = EFX_FAMILY_MEDFORD4;
+			*membarp = EFX_MEM_BAR_MEDFORD4;
+			return (0);
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 		case EFX_PCI_DEVID_FALCON:	/* Obsolete, not supported */
 		default:
 			break;
@@ -251,6 +266,27 @@ static const efx_nic_ops_t	__efx_nic_riverhead_ops = {
 
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+
+static const efx_nic_ops_t	__efx_nic_medford4_ops = {
+	ef10_nic_probe,			/* eno_probe */
+	medford2_board_cfg,		/* eno_board_cfg */
+	ef10_nic_set_drv_limits,	/* eno_set_drv_limits */
+	ef10_nic_reset,			/* eno_reset */
+	ef10_nic_init,			/* eno_init */
+	ef10_nic_get_vi_pool,		/* eno_get_vi_pool */
+	ef10_nic_get_bar_region,	/* eno_get_bar_region */
+	ef10_nic_hw_unavailable,	/* eno_hw_unavailable */
+	ef10_nic_set_hw_unavailable,	/* eno_set_hw_unavailable */
+#if EFSYS_OPT_DIAG
+	ef10_nic_register_test,		/* eno_register_test */
+#endif	/* EFSYS_OPT_DIAG */
+	ef10_nic_fini,			/* eno_fini */
+	ef10_nic_unprobe,		/* eno_unprobe */
+};
+
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 
 	__checkReturn	efx_rc_t
 efx_nic_create(
@@ -363,6 +399,22 @@ efx_nic_create(
 		break;
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		enp->en_enop = &__efx_nic_medford4_ops;
+		enp->en_features =
+		    EFX_FEATURE_IPV6 |
+		    EFX_FEATURE_LINK_EVENTS |
+		    EFX_FEATURE_PERIODIC_MAC_STATS |
+		    EFX_FEATURE_MCDI |
+		    EFX_FEATURE_MAC_HEADER_FILTERS |
+		    EFX_FEATURE_MCDI_DMA |
+		    EFX_FEATURE_FW_ASSISTED_TSO_V2 |
+		    EFX_FEATURE_PACKED_STREAM |
+		    EFX_FEATURE_TXQ_CKSUM_OP_DESC;
+		break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		rc = ENOTSUP;
 		goto fail2;
-- 
2.39.5

[PATCH v2 04/45] common/sfc_efx/base: add Medford4 support to EV module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_ev.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_ev.c b/drivers/common/sfc_efx/base/efx_ev.c
index 4808f8ddfc..13159a10f4 100644
--- a/drivers/common/sfc_efx/base/efx_ev.c
+++ b/drivers/common/sfc_efx/base/efx_ev.c
@@ -173,6 +173,12 @@ efx_ev_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		eevop = &__efx_ev_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH v2 05/45] common/sfc_efx/base: add Medford4 support to FILTER module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_filter.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_filter.c b/drivers/common/sfc_efx/base/efx_filter.c
index 2c8c7bdc33..551db58fdd 100644
--- a/drivers/common/sfc_efx/base/efx_filter.c
+++ b/drivers/common/sfc_efx/base/efx_filter.c
@@ -201,6 +201,12 @@ efx_filter_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		efop = &__efx_filter_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH v2 06/45] common/sfc_efx/base: add Medford4 support to INTR module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_intr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_intr.c b/drivers/common/sfc_efx/base/efx_intr.c
index 792302f540..8fdef839db 100644
--- a/drivers/common/sfc_efx/base/efx_intr.c
+++ b/drivers/common/sfc_efx/base/efx_intr.c
@@ -158,6 +158,12 @@ efx_intr_init(
 		break;
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		eiop = &__efx_intr_ef10_ops;
+		break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(B_FALSE);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH v2 07/45] common/sfc_efx/base: add Medford4 support to MAC module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h | 1 +
 drivers/common/sfc_efx/base/efx_mac.c  | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 9d1f361c5d..89b7e0292e 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -79,6 +79,7 @@ typedef enum efx_mac_type_e {
 	EFX_MAC_MEDFORD,
 	EFX_MAC_MEDFORD2,
 	EFX_MAC_RIVERHEAD,
+	EFX_MAC_MEDFORD4,
 	EFX_MAC_NTYPES
 } efx_mac_type_t;
 
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 13cac5a751..a2cbf02b46 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -953,6 +953,13 @@ efx_mac_select(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		emop = &__efx_mac_ef10_ops;
+		type = EFX_MAC_MEDFORD4;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		rc = EINVAL;
 		goto fail1;
-- 
2.39.5

[PATCH v2 08/45] common/sfc_efx/base: add Medford4 support to PHY module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_phy.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index d55becae18..3d792f20b8 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -114,6 +114,12 @@ efx_phy_probe(
 		break;
 #endif	/* EFSYS_OPT_MEDFORD2 */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		epop = &__efx_phy_ef10_ops;
+	break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		rc = ENOTSUP;
 		goto fail1;
-- 
2.39.5

Re: [PATCH v2 08/45] common/sfc_efx/base: add Medford4 support to PHY module

[Andrew Rybchenko]

On 4/23/25 18:59, Ivan Malov wrote:
> From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
> 
> Use common EF10 method table for that.
> 
> Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
> Reviewed-by: Andy Moreton <andy.moreton@amd.com>
> ---
>   drivers/common/sfc_efx/base/efx_phy.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
> index d55becae18..3d792f20b8 100644
> --- a/drivers/common/sfc_efx/base/efx_phy.c
> +++ b/drivers/common/sfc_efx/base/efx_phy.c
> @@ -114,6 +114,12 @@ efx_phy_probe(
>   		break;
>   #endif	/* EFSYS_OPT_MEDFORD2 */
>   
> +#if EFSYS_OPT_MEDFORD4
> +	case EFX_FAMILY_MEDFORD4:
> +		epop = &__efx_phy_ef10_ops;
> +	break;

Strange location of break

> +#endif	/* EFSYS_OPT_MEDFORD4 */
> +
>   	default:
>   		rc = ENOTSUP;
>   		goto fail1;

[PATCH v2 09/45] common/sfc_efx/base: add Medford4 support to TUNNEL module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_tunnel.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_tunnel.c b/drivers/common/sfc_efx/base/efx_tunnel.c
index d63f9176e4..75968a0b4f 100644
--- a/drivers/common/sfc_efx/base/efx_tunnel.c
+++ b/drivers/common/sfc_efx/base/efx_tunnel.c
@@ -47,7 +47,7 @@
 
 #if EFSYS_OPT_TUNNEL
 
-#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4
 static	__checkReturn	boolean_t
 ef10_udp_encap_supported(
 	__in		efx_nic_t *enp);
@@ -59,7 +59,7 @@ ef10_tunnel_reconfigure(
 static			void
 ef10_tunnel_fini(
 	__in		efx_nic_t *enp);
-#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4 */
 
 #if EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON
 static const efx_tunnel_ops_t	__efx_tunnel_dummy_ops = {
@@ -68,12 +68,12 @@ static const efx_tunnel_ops_t	__efx_tunnel_dummy_ops = {
 };
 #endif /* EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON */
 
-#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4
 static const efx_tunnel_ops_t	__efx_tunnel_ef10_ops = {
 	ef10_tunnel_reconfigure,	/* eto_reconfigure */
 	ef10_tunnel_fini,		/* eto_fini */
 };
-#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4 */
 
 #if EFSYS_OPT_RIVERHEAD
 static const efx_tunnel_ops_t	__efx_tunnel_rhead_ops = {
@@ -254,6 +254,12 @@ efx_tunnel_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		etop = &__efx_tunnel_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
@@ -637,7 +643,7 @@ efx_tunnel_reconfigure(
 	return (rc);
 }
 
-#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4
 static	__checkReturn		boolean_t
 ef10_udp_encap_supported(
 	__in		efx_nic_t *enp)
@@ -724,6 +730,6 @@ ef10_tunnel_fini(
 		    &resetting);
 	}
 }
-#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 || EFSYS_OPT_MEDFORD4 */
 
 #endif /* EFSYS_OPT_TUNNEL */
-- 
2.39.5

[PATCH v2 10/45] common/sfc_efx/base: add Medford4 support to MCDI module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_mcdi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c
index acf7f02246..0bd56dd84d 100644
--- a/drivers/common/sfc_efx/base/efx_mcdi.c
+++ b/drivers/common/sfc_efx/base/efx_mcdi.c
@@ -119,6 +119,12 @@ efx_mcdi_init(
 		break;
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		emcop = &__efx_mcdi_ef10_ops;
+		break;
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH v2 11/45] common/sfc_efx/base: add Medford4 support to Rx module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Use common EF10 method table for that.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_rx.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c
index dce9ada55d..86dfc89ba4 100644
--- a/drivers/common/sfc_efx/base/efx_rx.c
+++ b/drivers/common/sfc_efx/base/efx_rx.c
@@ -261,6 +261,12 @@ efx_rx_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		erxop = &__efx_rx_ef10_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH v2 12/45] common/sfc_efx/base: add Medford4 support to Tx module

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Define and use Medford4 specific method table.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/base/efx_tx.c | 33 ++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_tx.c b/drivers/common/sfc_efx/base/efx_tx.c
index 6f61f937a1..d1021dea82 100644
--- a/drivers/common/sfc_efx/base/efx_tx.c
+++ b/drivers/common/sfc_efx/base/efx_tx.c
@@ -233,6 +233,33 @@ static const efx_tx_ops_t	__efx_tx_rhead_ops = {
 #endif /* EFSYS_OPT_RIVERHEAD */
 
 
+#if EFSYS_OPT_MEDFORD4
+static const efx_tx_ops_t	__efx_tx_medford4_ops = {
+	ef10_tx_init,				/* etxo_init */
+	ef10_tx_fini,				/* etxo_fini */
+	ef10_tx_qcreate,			/* etxo_qcreate */
+	ef10_tx_qdestroy,			/* etxo_qdestroy */
+	ef10_tx_qpost,				/* etxo_qpost */
+	ef10_tx_qpush,				/* etxo_qpush */
+	ef10_tx_qpace,				/* etxo_qpace */
+	ef10_tx_qflush,				/* etxo_qflush */
+	ef10_tx_qenable,			/* etxo_qenable */
+	NULL,					/* etxo_qpio_enable */
+	NULL,					/* etxo_qpio_disable */
+	NULL,					/* etxo_qpio_write */
+	NULL,					/* etxo_qpio_post */
+	ef10_tx_qdesc_post,			/* etxo_qdesc_post */
+	ef10_tx_qdesc_dma_create,		/* etxo_qdesc_dma_create */
+	NULL,					/* etxo_qdesc_tso_create */
+	ef10_tx_qdesc_tso2_create,		/* etxo_qdesc_tso2_create */
+	ef10_tx_qdesc_vlantci_create,		/* etxo_qdesc_vlantci_create */
+	ef10_tx_qdesc_checksum_create,		/* etxo_qdesc_checksum_create */
+#if EFSYS_OPT_QSTATS
+	ef10_tx_qstats_update,			/* etxo_qstats_update */
+#endif
+};
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	__checkReturn	efx_rc_t
 efx_tx_init(
 	__in		efx_nic_t *enp)
@@ -284,6 +311,12 @@ efx_tx_init(
 		break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+	case EFX_FAMILY_MEDFORD4:
+		etxop = &__efx_tx_medford4_ops;
+		break;
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
-- 
2.39.5

[PATCH v2 13/45] drivers: enable support for AMD Solarflare X4 adapter family

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Enable support for Medford4 (X4) adapters X4522 and X4542.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
---
 drivers/common/sfc_efx/efsys.h | 4 ++--
 drivers/net/sfc/sfc_ethdev.c   | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h
index e63cbdbe8f..ea68d3bd1a 100644
--- a/drivers/common/sfc_efx/efsys.h
+++ b/drivers/common/sfc_efx/efsys.h
@@ -125,8 +125,8 @@ prefetch_read_once(const volatile void *addr)
 #define EFSYS_OPT_MEDFORD2 1
 /* Enable Riverhead support */
 #define EFSYS_OPT_RIVERHEAD 1
-/* Disable Medford4 support (not supported yet) */
-#define EFSYS_OPT_MEDFORD4 0
+/* Enable Medford4 support */
+#define EFSYS_OPT_MEDFORD4 1
 
 #ifdef RTE_DEBUG_COMMON_SFC_EFX
 #define EFSYS_OPT_CHECK_REG 1
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 82fbdbae9c..3e57c902df 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -2829,6 +2829,7 @@ sfc_eth_dev_set_ops(struct rte_eth_dev *dev)
 	case EFX_FAMILY_HUNTINGTON:
 	case EFX_FAMILY_MEDFORD:
 	case EFX_FAMILY_MEDFORD2:
+	case EFX_FAMILY_MEDFORD4:
 		avail_caps |= SFC_DP_HW_FW_CAP_EF10;
 		avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX;
 		avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX;
@@ -3301,6 +3302,8 @@ static const struct rte_pci_id pci_id_sfc_efx_map[] = {
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) },
 	{ .vendor_id = 0 /* sentinel */ }
-- 
2.39.5

[PATCH v2 14/45] net/sfc: add Medford4 with only full feature datapath engine

[Ivan Malov]

From: Andy Moreton <andy.moreton@amd.com>

Add PCI IDs for Medford4 functions that only have the full feature
datapath engine (no support for low latency datapath engine).

Signed-off-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/net/sfc/sfc_ethdev.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 3e57c902df..05194918f9 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -3304,6 +3304,8 @@ static const struct rte_pci_id pci_id_sfc_efx_map[] = {
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_VF) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_NO_LL) },
+	{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD4_NO_LL_VF) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) },
 	{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) },
 	{ .vendor_id = 0 /* sentinel */ }
-- 
2.39.5

[PATCH v2 15/45] common/sfc_efx/base: add port mode for 8 port hardware

[Ivan Malov]

From: Andy Moreton <andy.moreton@amd.com>

Add support for 8 port mode and adjust the bus bandwidth
computation and external port mapping table.

Signed-off-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/common/sfc_efx/base/ef10_nic.c        | 20 +++++++++++++++++++
 drivers/common/sfc_efx/base/ef10_tlv_layout.h |  9 ++++++---
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 9bff68f054..afad167dcb 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -176,6 +176,9 @@ ef10_nic_get_port_mode_bandwidth(
 	case TLV_PORT_MODE_2x1_2x1:			/* mode 5 */
 		bandwidth = (2 * single_lane) + (2 * single_lane);
 		break;
+	case TLV_PORT_MODE_4x1_4x1:			/* mode 26 */
+		bandwidth = (4 * single_lane) + (4 * single_lane);
+		break;
 	case TLV_PORT_MODE_1x2_1x2:			/* mode 12 */
 		bandwidth = dual_lane + dual_lane;
 		break;
@@ -1952,6 +1955,23 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_4x1_NA),			/* mode 4 */
 		{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Medford4 allocate up to 4 adjacent port numbers
+	 * to cage 1 and 4 port numbers to cage 2.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 1
+	 *	port 2 -> cage 1
+	 *	port 3 -> cage 1
+	 *	port 4 -> cage 2
+	 *	port 5 -> cage 2
+	 *	port 6 -> cage 2
+	 *	port 7 -> cage 2
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_4x1_4x1),			/* mode 26 */
+		{ 0, 4, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
 };
 
 static	__checkReturn	efx_rc_t
diff --git a/drivers/common/sfc_efx/base/ef10_tlv_layout.h b/drivers/common/sfc_efx/base/ef10_tlv_layout.h
index 9ac50f1df6..712a1c7d26 100644
--- a/drivers/common/sfc_efx/base/ef10_tlv_layout.h
+++ b/drivers/common/sfc_efx/base/ef10_tlv_layout.h
@@ -7,7 +7,7 @@
 /*
  * This is NOT the original source file. Do NOT edit it.
  * To update the tlv layout, please edit the copy in
- * the sfregistry repo and then, in that repo,
+ * the smartnic_registry repo and then, in that repo,
  * "make tlv_headers" or "make export" to
  * regenerate and export all types of headers.
  */
@@ -635,7 +635,10 @@ struct tlv_global_port_mode {
 #define TLV_PORT_MODE_1x1_NA_LL                  (23) /* Single 10G/25G on mdi0, low-latency PCS */
 #define TLV_PORT_MODE_1x1_1x1_LL                 (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE        (9) /* bug63720: Do not use */
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
+
+/* X4 */
+
+#define TLV_PORT_MODE_4x1_4x1                    (25) /* Quad 10G/25G on mdi0, quad 10G/25G on mdi1 */
 
 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
 #define TLV_PORT_MODE_10G_10G_10G_10G_Q          (5)
@@ -643,7 +646,7 @@ struct tlv_global_port_mode {
 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2         (8)
 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2      (9)
 
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_4x1_4x1
 };
 
 /* Type of the v-switch created implicitly by the firmware */
-- 
2.39.5

[PATCH v2 16/45] common/sfc_efx/base: add new X4 port mode

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Add handling for the port mode in the Medford4 driver logic,
enabling support for two single network ports.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Richard Houldsworth <richard.houldsworth@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 .mailmap                               |  2 +-
 drivers/common/sfc_efx/base/ef10_nic.c | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index 624aef9083..baad1ebaf1 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1295,7 +1295,7 @@ Ricardo Salveti <ricardo.salveti@linaro.org>
 Richael Zhuang <richael.zhuang@arm.com>
 Richard Donkin <richard.donkin@corigine.com>
 Richard Eklycke <richard.eklycke@ericsson.com>
-Richard Houldsworth <rhouldsw@xilinx.com> <rhouldsworth@solarflare.com>
+Richard Houldsworth <richard.houldsworth@amd.com> <rhouldsw@xilinx.com> <rhouldsworth@solarflare.com>
 Richard Walsh <richard.walsh@intel.com>
 Rich Lane <rich.lane@bigswitch.com>
 Ricky Li <ricky.li@intel.com>
diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index afad167dcb..199e605d88 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1972,6 +1972,16 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_4x1_4x1),			/* mode 26 */
 		{ 0, 4, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Medford4 allocate each port number to a separate cage.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 2
+	 */
+	{
+		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_1x4_1x4),			/* mode 3 */
+		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
 };
 
 static	__checkReturn	efx_rc_t
-- 
2.39.5

[PATCH v2 17/45] common/sfc_efx/base: extend list of supported X4 port modes

[Ivan Malov]

From: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>

Add X4 port mode that allocates two 10G/25G/50G ports
to separate cages.

Signed-off-by: Denis Pryazhennikov <denis.pryazhennikov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Richard Houldsworth <richard.houldsworth@amd.com>
Reviewed-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 drivers/common/sfc_efx/base/ef10_nic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 199e605d88..bce9df0aa6 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1979,6 +1979,7 @@ static struct ef10_external_port_map_s {
 	 */
 	{
 		EFX_FAMILY_MEDFORD4,
+		(1U << TLV_PORT_MODE_1x1_1x1) |			/* mode 2 */
 		(1U << TLV_PORT_MODE_1x4_1x4),			/* mode 3 */
 		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
-- 
2.39.5

[PATCH v2 18/45] common/sfc_efx/base: update MCDI headers

[Ivan Malov]

Pick up new X4 network port MCDI defines.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 .mailmap                                    |    1 +
 drivers/common/sfc_efx/base/efx_regs_mcdi.h | 5868 ++++++++++++++++++-
 2 files changed, 5816 insertions(+), 53 deletions(-)

diff --git a/.mailmap b/.mailmap
index baad1ebaf1..52f3a197ac 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1208,6 +1208,7 @@ Phil Yang <phil.yang@arm.com>
 Philip Prindeville <philipp@redfish-solutions.com>
 Pier Damouny <pdamouny@nvidia.com>
 Pierre Pfister <ppfister@cisco.com>
+Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
 Piotr Azarewicz <piotr.azarewicz@intel.com> <piotrx.t.azarewicz@intel.com>
 Piotr Bartosiewicz <piotr.bartosiewicz@atendesoftware.pl>
 Piotr Bronowski <piotrx.bronowski@intel.com>
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
index 41751344b4..a981d0be5e 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
@@ -408,6 +408,12 @@
  */
 #define	MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
 
+/* PORT_DIRECTION enum: Traffic direction for the port configuration APIs. */
+/* enum: Receive */
+#define	PORT_DIRECTION_RX 0x0
+/* enum: Transmit */
+#define	PORT_DIRECTION_TX 0x1
+
 /* MC_CMD_RESOURCE_SPECIFIER enum */
 /* enum: Any */
 #define	MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
@@ -445,6 +451,14 @@
  * an on-NIC ARM module is expected to be connected.
  */
 #define	PCIE_INTERFACE_NIC_EMBEDDED 0x1
+/* enum: The PCIe logical interface 0. It is an alias for HOST_PRIMARY. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_0 0x0
+/* enum: The PCIe logical interface 1. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_1 0x2
+/* enum: The PCIe logical interface 2. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_2 0x3
+/* enum: The PCIe logical interface 3. */
+#define	PCIE_INTERFACE_PCIE_HOST_INTF_3 0x4
 /* enum: For MCDI commands issued over a PCIe interface, this value is
  * translated into the interface over which the command was issued. Not
  * meaningful for other MCDI transports.
@@ -682,6 +696,53 @@
  */
 #define	MAE_COUNTER_ID_NULL 0xffffffff
 
+/* PR_METADATA_ITEM_CATEGORY enum: Meta-data item category */
+/* enum: A XCLBIN meta-data section */
+#define	PR_METADATA_ITEM_CATEGORY_SECTION 0x0
+/* enum: The active XCLBIN's UUID (axlf_header::uuid) */
+#define	PR_METADATA_ITEM_CATEGORY_UUID 0x1
+/* enum: The active XCLBIN's timestamp (axlf_header::m_timeStamp) */
+#define	PR_METADATA_ITEM_CATEGORY_TIMESTAMP 0x2
+/* enum: The active XCLBIN's signature (the last axlf::m_signature_length bytes
+ * of the XCLBIN data)
+ */
+#define	PR_METADATA_ITEM_CATEGORY_SIGNATURE 0x3
+
+/* PR_METADATA_ITEM_SUBCATEGORY enum: Meta-data item sub-category. For the
+ * SECTION category the subcategory matches AXLF section type identifiers (enum
+ * axlf_section_kind) and each subcategory contains an array of items as the
+ * AXLF container format supports multiple sections of the same type. Other
+ * categories (UUID, TIMESTAMP and SIGNATURE) do not currently use
+ * subcategories and must be 0 (NONE).
+ */
+#define	PR_METADATA_ITEM_SUBCATEGORY_NONE 0x0 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BITSTREAM 0x0 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_CLEARING_BITSTREAM 0x1 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_EMBEDDED_METADATA 0x2 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_FIRMWARE 0x3 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DEBUG_DATA 0x4 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_SCHED_FIRMWARE 0x5 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_MEM_TOPOLOGY 0x6 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_CONNECTIVITY 0x7 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_IP_LAYOUT 0x8 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DEBUG_IP_LAYOUT 0x9 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DESIGN_CHECK_POINT 0xa /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_CLOCK_FREQ_TOPOLOGY 0xb /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_MCS 0xc /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BMC 0xd /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BUILD_METADATA 0xe /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_KEYVALUE_METADATA 0xf /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_USER_METADATA 0x10 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_DNA_CERTIFICATE 0x11 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_PDI 0x12 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_BITSTREAM_PARTIAL_PDI 0x13 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_PARTITION_METADATA 0x14 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_EMULATION_DATA 0x15 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_SYSTEM_METADATA 0x16 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_SOFT_KERNEL 0x17 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_ASK_FLASH 0x18 /* enum */
+#define	PR_METADATA_ITEM_SUBCATEGORY_AIE_METADATA 0x19 /* enum */
+
 /* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
  * structured with bits [31:24] reserved (0), [23:16] indicating which major
  * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
@@ -1241,10 +1302,7 @@
 #define	TABLE_FIELD_ID_CRC_REFOUT 0x3f4
 /* enum: If set, invert every bit of the output value. */
 #define	TABLE_FIELD_ID_CRC_INVOUT 0x3f5
-/* enum: The CRC polynomial to use for checksumming, in normal form. See
- * https://en.wikipedia.org/wiki/Cyclic_redundancy_check#Specification for a
- * description of normal form.
- */
+/* enum: The CRC polynomial to use for checksumming, in normal form. */
 #define	TABLE_FIELD_ID_CRC_POLY 0x3f6
 /* enum: Operation for the checksum engine to perform - see DPU_CSUM_OP enum.
  */
@@ -1335,6 +1393,24 @@
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
+#define	MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_LBN 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_WIDTH 24
+#define	MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_LBN 24
+#define	MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_WIDTH 7
+#define	MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_LBN 31
+#define	MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_WIDTH 1
+#define	MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_LBN 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_WIDTH 24
+#define	MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_LBN 24
+#define	MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_WIDTH 7
+#define	MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_LBN 31
+#define	MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_WIDTH 1
 #define	MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
 #define	MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
 #define	MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
@@ -1709,6 +1785,25 @@
  * VI ID.
  */
 #define	MCDI_EVENT_CODE_DESC_PROXY_FUNC_QUEUE_START 0x28
+/* enum: Notification of a change in link state and/or link speed of a network
+ * port link. This event applies to a network port identified by a handle,
+ * PORT_HANDLE, which is discovered by the driver using the MC_CMD_ENUM_PORTS
+ * command.
+ */
+#define	MCDI_EVENT_CODE_PORT_LINKCHANGE 0x29
+/* enum: Notification of a change in the state of an MDI (external connector)
+ * of a network port. This typically corresponds to module plug/unplug for
+ * modular interfaces (e.g., SFP/QSFP and similar) or cable connect/disconnect.
+ * This event applies to a network port identified by a handle, PORT_HANDLE,
+ * which is discovered by the driver using the MC_CMD_ENUM_PORTS command.
+ */
+#define	MCDI_EVENT_CODE_PORT_MODULECHANGE 0x2a
+/* enum: Notification that the port enumeration journal has changed since it
+ * was last read and updates can be read using the MC_CMD_ENUM_PORTS command.
+ * The firmware may moderate the events so that an event is not sent for every
+ * change to the journal.
+ */
+#define	MCDI_EVENT_CODE_ENUM_PORTS_CHANGE 0x2b
 /* enum: Artificial event generated by host and posted via MC for test
  * purposes.
  */
@@ -1721,6 +1816,14 @@
 #define	MCDI_EVENT_LINKCHANGE_DATA_LEN 4
 #define	MCDI_EVENT_LINKCHANGE_DATA_LBN 0
 #define	MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_OFST 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_LEN 4
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_LBN 0
+#define	MCDI_EVENT_PORT_LINKCHANGE_DATA_WIDTH 32
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_OFST 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_LEN 4
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_LBN 0
+#define	MCDI_EVENT_PORT_MODULECHANGE_DATA_WIDTH 32
 #define	MCDI_EVENT_SENSOREVT_DATA_OFST 0
 #define	MCDI_EVENT_SENSOREVT_DATA_LEN 4
 #define	MCDI_EVENT_SENSOREVT_DATA_LBN 0
@@ -3302,8 +3405,11 @@
  * subscribers.
  */
 #define	MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
-/* enum: Above this for future use. */
-#define	MC_CMD_PTP_OP_MAX 0x1c
+/* enum: X4 and later adapters should use this instead of
+ * PTP_OP_TIME_EVENT_SUBSCRIBE. Subscribe to receive periodic time events
+ * indicating the current NIC time
+ */
+#define	MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE_V2 0x1c
 
 /* MC_CMD_PTP_IN_ENABLE msgrequest */
 #define	MC_CMD_PTP_IN_ENABLE_LEN 16
@@ -3744,6 +3850,22 @@
 #define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
 #define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
 
+/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2 msgrequest */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_LEN 16
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_CMD_LEN 4 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
+/* Event queue ID */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_OFST 8
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_LEN 4
+/* Space for flags. */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_OFST 12
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_LEN 4
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_OFST 12
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_LBN 31
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_WIDTH 1
+
 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
 #define	MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
@@ -6262,13 +6384,837 @@
 #define	FEC_TYPE_TYPE_LEN 4
 /* enum: No FEC */
 #define	MC_CMD_FEC_NONE 0x0
-/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
+/* enum: IEEE 802.3, Clause 74 BASE-R FEC (a.k.a Firecode) */
 #define	MC_CMD_FEC_BASER 0x1
-/* enum: Clause 91/Clause 108 Reed-Solomon FEC */
+/* enum: IEEE 802.3, Clause 91/Clause 108 Reed-Solomon FEC */
 #define	MC_CMD_FEC_RS 0x2
+/* enum: IEEE 802.3, Clause 161, interleaved RS-FEC sublayer for 100GBASE-R
+ * PHYs
+ */
+#define	MC_CMD_FEC_IEEE_RS_INT 0x3
+/* enum: Ethernet Consortium, Low Latency RS-FEC. RS(272, 258). Replaces FEC
+ * specified in Clause 119 for 100/200G PHY. Replaces FEC specified in Clause
+ * 134 for 50G PHY.
+ */
+#define	MC_CMD_FEC_ETCS_RS_LL 0x4
+/* enum: FEC mode selected automatically */
+#define	MC_CMD_FEC_AUTO 0x5
 #define	FEC_TYPE_TYPE_LBN 0
 #define	FEC_TYPE_TYPE_WIDTH 32
 
+/* MC_CMD_ETH_TECH structuredef: Ethernet technology as defined by IEEE802.3,
+ * Ethernet Technology Consortium, proprietary technologies. The driver must
+ * not use technologies labelled NONE and AUTO.
+ */
+#define	MC_CMD_ETH_TECH_LEN 16
+/* The enums in this field can be used either as bitwise indices into a tech
+ * mask (e.g. see MC_CMD_ETH_AN_FIELDS/TECH_MASK for example) or as regular
+ * enums (e.g. see MC_CMD_LINK_CTRL_IN/ADVERTISED_TECH_ABILITIES_MASK). This
+ * structure must be updated to add new technologies when projects that need
+ * them arise. An incomplete list of possible expansion in the future include:
+ * 100GBASE_KP4, 800GBASE_CR8, 800GBASE_KR8, 800GBASE_DR8, 800GBASE_SR8
+ * 800GBASE_VR8
+ */
+#define	MC_CMD_ETH_TECH_TECH_OFST 0
+#define	MC_CMD_ETH_TECH_TECH_LEN 16
+/* enum: 1000BASE-KX - 1000BASE-X PCS/PMA over an electrical backplane PMD. See
+ * IEEE 802.3 Clause 70
+ */
+#define	MC_CMD_ETH_TECH_1000BASEKX 0x0
+/* enum: 10GBASE-R - PCS/PMA over an electrical backplane PMD. Refer to IEEE
+ * 802.3 Clause 72
+ */
+#define	MC_CMD_ETH_TECH_10GBASE_KR 0x1
+/* enum: 40GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 84.
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_KR4 0x2
+/* enum: 40GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
+ * IEEE 802.3 Clause 85
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_CR4 0x3
+/* enum: 40GBASE-R PCS/PMA over 4 lane multimode fiber PMD as specified in
+ * Clause 86
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_SR4 0x4
+/* enum: 40GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD with long
+ * reach. See IEEE 802.3 Clause 87
+ */
+#define	MC_CMD_ETH_TECH_40GBASE_LR4 0x5
+/* enum: 25GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
+ * 802.3 Clause 110
+ */
+#define	MC_CMD_ETH_TECH_25GBASE_CR 0x6
+/* enum: 25GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 111
+ */
+#define	MC_CMD_ETH_TECH_25GBASE_KR 0x7
+/* enum: 25GBASE-R PCS/PMA over multimode fiber PMD. Refer to IEEE 802.3 Clause
+ * 112
+ */
+#define	MC_CMD_ETH_TECH_25GBASE_SR 0x8
+/* enum: An Ethernet Physical layer operating at 50 Gb/s on twin-axial copper
+ * cable. Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_CR2 0x9
+/* enum: An Ethernet Physical layer operating at 50 Gb/s on copper backplane.
+ * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_KR2 0xa
+/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 93
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_KR4 0xb
+/* enum: 100GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
+ * Clause 95
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_SR4 0xc
+/* enum: 100GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
+ * IEEE 802.3 Clause 92
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR4 0xd
+/* enum: 100GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD, with
+ * long/extended reach,. See IEEE 802.3 Clause 88
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_LR4_ER4 0xe
+/* enum: An Ethernet Physical layer operating at 50 Gb/s on short reach fiber.
+ * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_SR2 0xf
+/* enum: 1000BASEX PCS/PMA. See IEEE 802.3 Clause 36 over undefined PMD, duplex
+ * mode unknown
+ */
+#define	MC_CMD_ETH_TECH_1000BASEX 0x10
+/* enum: Non-standardised. 10G direct attach */
+#define	MC_CMD_ETH_TECH_10GBASE_CR 0x11
+/* enum: 10GBASE-SR fiber over 850nm optics. See IEEE 802.3 Clause 52 */
+#define	MC_CMD_ETH_TECH_10GBASE_SR 0x12
+/* enum: 10GBASE-LR fiber over 1310nm optics. See IEEE 802.3 Clause 52 */
+#define	MC_CMD_ETH_TECH_10GBASE_LR 0x13
+/* enum: 10GBASE-LRM fiber over 1310 nm optics. See IEEE 802.3 Clause 68 */
+#define	MC_CMD_ETH_TECH_10GBASE_LRM 0x14
+/* enum: 10GBASE-ER fiber over 1550nm optics. See IEEE 802.3 Clause 52 */
+#define	MC_CMD_ETH_TECH_10GBASE_ER 0x15
+/* enum: 50GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 137
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_KR 0x16
+/* enum: 50GBASE-SR PCS/PMA over multimode fiber PMD as specified in Clause 138
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_SR 0x17
+/* enum: 50GBASE-CR PCS/PMA over shielded copper balanced cable PMD. See IEEE
+ * 802.3 Clause 136
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_CR 0x18
+/* enum: 50GBASE-R PCS/PMA over single mode fiber PMD as specified in Clause
+ * 139.
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_LR_ER_FR 0x19
+/* enum: 100 Gb/s PHY using 100GBASE-R encoding over single-mode fiber with
+ * reach up to at least 500 m (see IEEE 802.3 Clause 140)
+ */
+#define	MC_CMD_ETH_TECH_50GBASE_DR 0x1a
+/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 137
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_KR2 0x1b
+/* enum: 100GBASE-R PCS/PMA over 2 lane multimode fiber PMD. See IEEE 802.3
+ * Clause 138
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_SR2 0x1c
+/* enum: 100GBASE-R PCS/PMA over 2 lane shielded copper balanced cable PMD. See
+ * IEEE 802.3 Clause 136
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR2 0x1d
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2 0x1e
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_100GBASE_DR2 0x1f
+/* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 137
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_KR4 0x20
+/* enum: 200GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
+ * Clause 138
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_SR4 0x21
+/* enum: 200GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD as specified
+ * in Clause 122
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4 0x22
+/* enum: 200GBASE-R PCS/PMA over 4-lane single-mode fiber PMD. See IEEE 802.3
+ * Clause 121
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_DR4 0x23
+/* enum: 200GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD as
+ * specified in Clause 136
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_CR4 0x24
+/* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-KR8 PMD uses
+ * 802.3 Clause 137, but the number PMD lanes is 8.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_KR8 0x25
+/* enum: 400GBASE-R PCS/PMA over 8-lane multimode fiber PMD. See IEEE 802.3
+ * Clause 138
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_SR8 0x26
+/* enum: 400GBASE-R PCS/PMA over 8 WDM lane single-mode fiber PMD. See IEEE
+ * 802.3 Clause 122
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_LR8_ER8_FR8 0x27
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_400GBASE_DR8 0x28
+/* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-CR8 PMD uses
+ * IEEE 802.3 Clause 136, but the number PMD lanes is 8.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_CR8 0x29
+/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3ck
+ * Clause 163.
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_KR 0x2a
+/* enum: IEEE 802.3ck. 100G PHY with PMD as specified in Clause 167 over short
+ * reach fiber
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_SR 0x2b
+/* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
+ * 140
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_LR_ER_FR 0x2c
+/* enum: 100GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
+ * 802.3 in Clause 162 IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR 0x2d
+/* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
+ * 140
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_DR 0x2e
+/* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD as specified in
+ * Clause 163 IEEE 802.3ck
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_KR2 0x2f
+/* enum: 200G PHY with PMD as specified in Clause 167 over short reach fiber
+ * IEEE 802.3ck
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_SR2 0x30
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2 0x31
+/* enum: Unknown source */
+#define	MC_CMD_ETH_TECH_200GBASE_DR2 0x32
+/* enum: 200GBASE-R PCS/PMA over 2 lane shielded balanced copper cable PMD as
+ * specified in Clause 162 IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_200GBASE_CR2 0x33
+/* enum: 400GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
+ * Clause 163 IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_KR4 0x34
+/* enum: 400G PHY with PMD over short reach fiber. See Clause 167 of IEEE
+ * 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_SR4 0x35
+/* enum: 400GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD. See IEEE
+ * 802.3 Clause 151
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_LR4_ER4_FR4 0x36
+/* enum: 400GBASE-R PCS/PMA over 4-lane single-mode fiber PMD as specified in
+ * Clause 124
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_DR4 0x37
+/* enum: 400GBASE-R PCS/PMA over 4 lane shielded balanced copper cable PMD as
+ * specified in Clause 162 of IEEE 802.3ck.
+ */
+#define	MC_CMD_ETH_TECH_400GBASE_CR4 0x38
+/* enum: Automatic tech mode. The driver must not use this. */
+#define	MC_CMD_ETH_TECH_AUTO 0x39
+/* enum: See IEEE 802.3cc-2017 Clause 114 */
+#define	MC_CMD_ETH_TECH_25GBASE_LR_ER 0x3a
+/* enum: Up to 7 m over twinaxial copper cable assembly (10 lanes, 10 Gbit/s
+ * each) See IEEE 802.3ba-2010 Clause 85
+ */
+#define	MC_CMD_ETH_TECH_100GBASE_CR10 0x3b
+/* enum: Invalid tech mode. The driver must not use this. */
+#define	MC_CMD_ETH_TECH_NONE 0x7f
+#define	MC_CMD_ETH_TECH_TECH_LBN 0
+#define	MC_CMD_ETH_TECH_TECH_WIDTH 128
+
+/* MC_CMD_LINK_STATUS_FLAGS structuredef */
+#define	MC_CMD_LINK_STATUS_FLAGS_LEN 8
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: bitshift */
+/* enum: Whether we have overall link up */
+#define	MC_CMD_LINK_STATUS_FLAGS_LINK_UP 0x0
+/* enum: If set, the PHY has no external RX link synchronisation */
+#define	MC_CMD_LINK_STATUS_FLAGS_NO_PHY_LINK 0x1
+/* enum: If set, PMD/MDI is not connected (e.g. cable disconnected, module cage
+ * empty)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_MDI_DISCONNECTED 0x2
+/* enum: Set on error while decoding module data (e.g. module EEPROM does not
+ * contain valid values, has checksum errors, etc.)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_BAD 0x3
+/* enum: Set when module unsupported (e.g. unsupported link rate or link
+ * technology)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_UNSUPPORTED 0x4
+/* enum: Set on error while communicating with the module (e.g. I2C errors
+ * while reading EEPROM)
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_COMMS_FAULT 0x5
+/* enum: Set on module overcurrent/overvoltage condition */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_POWER_FAULT 0x6
+/* enum: Set on module overtemperature condition */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_THERMAL_FAULT 0x7
+/* enum: If set, the module is indicating Loss of Signal */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMD_LOS 0x8
+/* enum: If set, PMA is indicating loss of CDR lock (clock sync) */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMA_NO_CDR_LOCK 0x9
+/* enum: If set, PMA is indicating loss of analog signal */
+#define	MC_CMD_LINK_STATUS_FLAGS_PMA_LOS 0xa
+/* enum: If set, PCS is indicating loss of block lock */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_NO_BLOCK_LOCK 0xb
+/* enum: If set, PCS is indicating loss of alignment marker lock on one or more
+ * lanes
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_NO_AM_LOCK 0xc
+/* enum: If set, PCS is indicating loss of overall alignment lock */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_NO_ALIGN_LOCK 0xd
+/* enum: If set, PCS is indicating high bit error rate condition. */
+#define	MC_CMD_LINK_STATUS_FLAGS_PCS_HI_BER 0xe
+/* enum: If set, FEC is indicating loss of FEC lock */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_NO_LOCK 0xf
+/* enum: If set, indicates that the number of symbol errors in a 8192-codeword
+ * window has exceeded the threshold K (417).
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_HI_SER 0x10
+/* enum: If set, the receiver has detected the local FEC has degraded. */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_LOCAL_DEGRADED 0x11
+/* enum: If set, the receiver has detected the remote FEC has degraded. */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_RM_DEGRADED 0x12
+/* enum: If set, the number of symbol errors is over an internal threshold. */
+#define	MC_CMD_LINK_STATUS_FLAGS_FEC_DEGRADED_SER 0x13
+/* enum: If set, autonegotiation has detected an auto-negotiation capable link
+ * partner
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_ABLE 0x14
+/* enum: If set, autonegotiation base page exchange has failed */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_BP_FAILED 0x15
+/* enum: If set, autonegotiation next page exchange has failed */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_NP_FAILED 0x16
+/* enum: If set, autonegotiation has failed to negotiate a common set of
+ * capabilities
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_AN_NO_HCD 0x17
+/* enum: If set, local end link training has failed to establish link training
+ * frame lock on one or more lanes
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_LT_NO_LOCAL_FRAME_LOCK 0x18
+/* enum: If set, remote end link training has failed to establish link training
+ * frame lock on one or more lanes
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_LT_NO_RM_FRAME_LOCK 0x19
+/* enum: If set, remote end has failed to assert Receiver Ready (link training
+ * success) within the designated timeout
+ */
+#define	MC_CMD_LINK_STATUS_FLAGS_LT_NO_RX_READY 0x1a
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LBN 0
+#define	MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_WIDTH 64
+
+/* MC_CMD_PAUSE_MODE structuredef */
+#define	MC_CMD_PAUSE_MODE_LEN 1
+#define	MC_CMD_PAUSE_MODE_TYPE_OFST 0
+#define	MC_CMD_PAUSE_MODE_TYPE_LEN 1
+/* enum: See IEEE 802.3 Clause 73.6.6 */
+#define	MC_CMD_PAUSE_MODE_AN_PAUSE 0x0
+/* enum: See IEEE 802.3 Clause 73.6.6 */
+#define	MC_CMD_PAUSE_MODE_AN_ASYM_DIR 0x1
+#define	MC_CMD_PAUSE_MODE_TYPE_LBN 0
+#define	MC_CMD_PAUSE_MODE_TYPE_WIDTH 8
+
+/* MC_CMD_ETH_AN_FIELDS structuredef: Fields used for IEEE 802.3 Clause 73
+ * Auto-Negotiation. Warning - This is fixed size and cannot be extended. This
+ * structure is used to define autonegotiable abilities (advertised, link
+ * partner and supported abilities).
+ */
+#define	MC_CMD_ETH_AN_FIELDS_LEN 25
+/* Mask of Ethernet technologies. The bit indices in this mask are taken from
+ * the TECH field in the MC_CMD_ETH_TECH structure.
+ */
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_OFST 0
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_LEN 16
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_LBN 0
+#define	MC_CMD_ETH_AN_FIELDS_TECH_MASK_WIDTH 128
+/* Mask of supported FEC modes */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_OFST 16
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_LBN 128
+#define	MC_CMD_ETH_AN_FIELDS_FEC_MASK_WIDTH 32
+/* Mask of requested FEC modes */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_OFST 20
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_LBN 160
+#define	MC_CMD_ETH_AN_FIELDS_FEC_REQ_WIDTH 32
+/* Bitmask of negotiated pause modes */
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_OFST 24
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LBN 192
+#define	MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_WIDTH 8
+
+/* MC_CMD_LOOPBACK_V2 structuredef: Loopback modes for use with the new
+ * MC_CMD_LINK_CTRL and MC_CMD_LINK_STATE. These loopback modes are not
+ * supported in other getlink/setlink commands.
+ */
+#define	MC_CMD_LOOPBACK_V2_LEN 4
+#define	MC_CMD_LOOPBACK_V2_MODE_OFST 0
+#define	MC_CMD_LOOPBACK_V2_MODE_LEN 4
+/* enum: No loopback */
+#define	MC_CMD_LOOPBACK_V2_NONE 0x0
+/* enum: Let firmware choose a supported loopback mode */
+#define	MC_CMD_LOOPBACK_V2_AUTO 0x1
+/* enum: Loopback after the MAC */
+#define	MC_CMD_LOOPBACK_V2_POST_MAC 0x2
+/* enum: Loopback after the PCS */
+#define	MC_CMD_LOOPBACK_V2_POST_PCS 0x3
+/* enum: Loopback after the PMA */
+#define	MC_CMD_LOOPBACK_V2_POST_PMA 0x4
+/* enum: Loopback after the MDI Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_MDI_WS 0x5
+/* enum: Loopback after the PMA Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_PMA_WS 0x6
+/* enum: Loopback after the PCS Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_PCS_WS 0x7
+/* enum: Loopback after the MAC Wireside */
+#define	MC_CMD_LOOPBACK_V2_POST_MAC_WS 0x8
+/* enum: Loopback after the MAC FIFOs (before the MAC) */
+#define	MC_CMD_LOOPBACK_V2_PRE_MAC 0x9
+#define	MC_CMD_LOOPBACK_V2_MODE_LBN 0
+#define	MC_CMD_LOOPBACK_V2_MODE_WIDTH 32
+
+/* MC_CMD_FCNTL structuredef */
+#define	MC_CMD_FCNTL_LEN 4
+#define	MC_CMD_FCNTL_MASK_OFST 0
+#define	MC_CMD_FCNTL_MASK_LEN 4
+/* enum: Flow control is off. */
+#define	MC_CMD_FCNTL_OFF 0x0
+/* enum: Respond to flow control. */
+#define	MC_CMD_FCNTL_RESPOND 0x1
+/* enum: Respond to and Issue flow control. */
+#define	MC_CMD_FCNTL_BIDIR 0x2
+/* enum: Auto negotiate flow control. */
+#define	MC_CMD_FCNTL_AUTO 0x3
+/* enum: Priority flow control. This is only supported on KSB. */
+#define	MC_CMD_FCNTL_QBB 0x4
+/* enum: Issue flow control. */
+#define	MC_CMD_FCNTL_GENERATE 0x5
+#define	MC_CMD_FCNTL_MASK_LBN 0
+#define	MC_CMD_FCNTL_MASK_WIDTH 32
+
+/* MC_CMD_LINK_FLAGS structuredef */
+#define	MC_CMD_LINK_FLAGS_LEN 4
+/* The enums defined in this field are used as indices into the
+ * MC_CMD_LINK_FLAGS bitmask.
+ */
+#define	MC_CMD_LINK_FLAGS_MASK_OFST 0
+#define	MC_CMD_LINK_FLAGS_MASK_LEN 4
+/* enum property: bitshift */
+/* enum: Enable auto-negotiation. If AN is enabled, link technology and FEC
+ * mode are determined by advertised capabilities and requested FEC modes,
+ * combined with link partner capabilities. If AN is disabled, link technology
+ * is forced to LINK_TECHNOLOGY and FEC mode is forced to FEC_MODE. Not valid
+ * if loopback is enabled
+ */
+#define	MC_CMD_LINK_FLAGS_AUTONEG_EN 0x0
+/* enum: Enable parallel detect. In addition to AN, try to sense partner forced
+ * speed/FEC mode (when partner AN disabled). Only valid if AN is enabled.
+ */
+#define	MC_CMD_LINK_FLAGS_PARALLEL_DETECT_EN 0x1
+/* enum: Force link down, in electrical idle. */
+#define	MC_CMD_LINK_FLAGS_LINK_DISABLE 0x2
+/* enum: Ignore the sequence number and always apply. */
+#define	MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ 0x3
+#define	MC_CMD_LINK_FLAGS_MASK_LBN 0
+#define	MC_CMD_LINK_FLAGS_MASK_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_LINK_CTRL
+ * Write the unified MAC/PHY link configuration. Locks required: None. Return
+ * code: 0, EINVAL, ETIME, EAGAIN
+ */
+#define	MC_CMD_LINK_CTRL 0x6b
+#define	MC_CMD_LINK_CTRL_MSGSET 0x6b
+#undef	MC_CMD_0x6b_PRIVILEGE_CTG
+
+#define	MC_CMD_0x6b_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_LINK_CTRL_IN msgrequest */
+#define	MC_CMD_LINK_CTRL_IN_LEN 40
+/* Handle to the port to set link state for. */
+#define	MC_CMD_LINK_CTRL_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_LINK_CTRL_IN_PORT_HANDLE_LEN 4
+/* Control flags */
+#define	MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_OFST 4
+#define	MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Reserved for future expansion, and included to provide padding for alignment
+ * purposes.
+ */
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_OFST 8
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LEN 8
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_OFST 8
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_LEN 4
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_LBN 64
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_LO_WIDTH 32
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_OFST 12
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_LEN 4
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_LBN 96
+#define	MC_CMD_LINK_CTRL_IN_RESERVED_HI_WIDTH 32
+/* Technology abilities to advertise during auto-negotiation */
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_OFST 16
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_LEN 16
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Pause abilities to advertise during auto-negotiation. Valid when auto-
+ * negotation is enabled and MC_CMD_SET_MAC_IN/FCTL is set to
+ * MC_CMD_FCNTL_AUTO. If auto-negotiation is disabled the driver must
+ * explicitly configure pause mode with MC_CMD_SET_MAC.
+ */
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_OFST 32
+#define	MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* When auto-negotiation is enabled, this is the FEC mode to request. Note that
+ * a weaker FEC mode may get negotiated, depending on what the link partner
+ * supports. The driver should subsequently use MC_CMD_GET_LINK to check the
+ * actual negotiated FEC mode. When auto-negotiation is disabled, this is the
+ * forced FEC mode.
+ */
+#define	MC_CMD_LINK_CTRL_IN_FEC_MODE_OFST 33
+#define	MC_CMD_LINK_CTRL_IN_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* This is only to be used when auto-negotiation is disabled (forced speed or
+ * loopback mode). If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_OFST 36
+#define	MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* The sequence number of the last MODULECHANGE event. If this doesn't match,
+ * fail with EAGAIN.
+ */
+#define	MC_CMD_LINK_CTRL_IN_MODULE_SEQ_OFST 38
+#define	MC_CMD_LINK_CTRL_IN_MODULE_SEQ_LEN 1
+/* Loopback Mode. Only valid when auto-negotiation is disabled. */
+#define	MC_CMD_LINK_CTRL_IN_LOOPBACK_OFST 39
+#define	MC_CMD_LINK_CTRL_IN_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+
+/* MC_CMD_LINK_CTRL_OUT msgresponse */
+#define	MC_CMD_LINK_CTRL_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_LINK_STATE
+ */
+#define	MC_CMD_LINK_STATE 0x6c
+#define	MC_CMD_LINK_STATE_MSGSET 0x6c
+#undef	MC_CMD_0x6c_PRIVILEGE_CTG
+
+#define	MC_CMD_0x6c_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_LINK_STATE_IN msgrequest */
+#define	MC_CMD_LINK_STATE_IN_LEN 4
+/* Handle to the port to get link state for. */
+#define	MC_CMD_LINK_STATE_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_LINK_STATE_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_LINK_STATE_OUT msgresponse */
+#define	MC_CMD_LINK_STATE_OUT_LEN 114
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+/* Configured technology. If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_OFST 8
+#define	MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Configured FEC mode */
+#define	MC_CMD_LINK_STATE_OUT_FEC_MODE_OFST 10
+#define	MC_CMD_LINK_STATE_OUT_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* Bitmask of auto-negotiated pause modes */
+#define	MC_CMD_LINK_STATE_OUT_PAUSE_MASK_OFST 11
+#define	MC_CMD_LINK_STATE_OUT_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* Configured loopback mode */
+#define	MC_CMD_LINK_STATE_OUT_LOOPBACK_OFST 12
+#define	MC_CMD_LINK_STATE_OUT_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* Abilities requested by the driver to advertise during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_LEN 32
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_OFST 32
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_OFST 36
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_OFST 40
+#define	MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_LEN 1
+/* Abilities advertised by the link partner during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_LEN 32
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_OFST 64
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_OFST 68
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_OFST 72
+#define	MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_LEN 1
+/* Abilities supported by the local device (including cable abilities) For
+ * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
+ */
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_LEN 28
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_OFST 96
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_OFST 100
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_OFST 104
+#define	MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_LEN 1
+/* Control flags */
+#define	MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_OFST 108
+#define	MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Sequence number to synchronize link change events */
+#define	MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_OFST 112
+#define	MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_LEN 1
+/* Sequence number to synchronize module change events */
+#define	MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 113
+#define	MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+
+/* MC_CMD_LINK_STATE_OUT_V2 msgresponse: Updated LINK_STATE_OUT with
+ * LOCAL_AN_SUPPORT
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_LEN 120
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+/* Configured technology. If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_OFST 8
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Configured FEC mode */
+#define	MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_OFST 10
+#define	MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* Bitmask of auto-negotiated pause modes */
+#define	MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_OFST 11
+#define	MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* Configured loopback mode */
+#define	MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_OFST 12
+#define	MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* Abilities requested by the driver to advertise during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_LEN 32
+/* Abilities advertised by the link partner during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_LEN 32
+/* Abilities supported by the local device (including cable abilities) For
+ * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_LEN 28
+/* Control flags */
+#define	MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_OFST 108
+#define	MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Sequence number to synchronize link change events */
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_OFST 112
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_LEN 1
+/* Sequence number to synchronize module change events */
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_OFST 113
+#define	MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+/* Reports the auto-negotiation supported by the local device. This depends on
+ * the port and module properties.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_OFST 116
+#define	MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_LEN 4
+/*            Enum values, see field(s): */
+/*               AN_TYPE/TYPE */
+
+/* MC_CMD_LINK_STATE_OUT_V3 msgresponse: Updated LINK_STATE_OUT_V2 for explicit
+ * reporting of the link speed and duplex mode.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LEN 128
+/* Flags used to report the current configuration/state of the link. */
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_OFST 0
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_OFST 4
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LBN 32
+#define	MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+/* Configured technology. If the specified value does not align with the values
+ * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_OFST 8
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_LEN 2
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Configured FEC mode */
+#define	MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_OFST 10
+#define	MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* Bitmask of auto-negotiated pause modes */
+#define	MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_OFST 11
+#define	MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_PAUSE_MODE/TYPE */
+/* Configured loopback mode */
+#define	MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_OFST 12
+#define	MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_LEN 1
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* Abilities requested by the driver to advertise during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_OFST 16
+#define	MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_LEN 32
+/* Abilities advertised by the link partner during auto-negotiation */
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_OFST 48
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_LEN 32
+/* Abilities supported by the local device (including cable abilities) For
+ * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_OFST 80
+#define	MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_LEN 28
+/* Control flags */
+#define	MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_OFST 108
+#define	MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_FLAGS/MASK */
+/* Sequence number to synchronize link change events */
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_OFST 112
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_LEN 1
+/* Sequence number to synchronize module change events */
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_OFST 113
+#define	MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+/* Reports the auto-negotiation supported by the local device. This depends on
+ * the port and module properties.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_OFST 116
+#define	MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_LEN 4
+/*            Enum values, see field(s): */
+/*               AN_TYPE/TYPE */
+/* Autonegotiated speed in mbit/s. The link may still be down even if this
+ * reads non-zero. LINK_SPEED field is intended to be used by drivers without
+ * the most up-to-date MCDI definitions, unable to deduce the link speed from
+ * the reported LINK_TECHNOLOGY field.
+ */
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_OFST 120
+#define	MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_FLAGS_OFST 124
+#define	MC_CMD_LINK_STATE_OUT_V3_FLAGS_LEN 4
+#define	MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_OFST 124
+#define	MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN 0
+#define	MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_WIDTH 1
+
 
 /***********************************/
 /* MC_CMD_GET_LINK
@@ -6383,6 +7329,7 @@
 /* This returns the negotiated flow control value. */
 #define	MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
 #define	MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
+/* enum property: value */
 /*            Enum values, see field(s): */
 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
 #define	MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
@@ -6451,6 +7398,7 @@
 /* This returns the negotiated flow control value. */
 #define	MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
 #define	MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
+/* enum property: value */
 /*            Enum values, see field(s): */
 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
 #define	MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
@@ -6764,17 +7712,17 @@
 #define	MC_CMD_SET_MAC_IN_FCNTL_OFST 20
 #define	MC_CMD_SET_MAC_IN_FCNTL_LEN 4
 /* enum: Flow control is off. */
-#define	MC_CMD_FCNTL_OFF 0x0
+/*               MC_CMD_FCNTL_OFF 0x0 */
 /* enum: Respond to flow control. */
-#define	MC_CMD_FCNTL_RESPOND 0x1
+/*               MC_CMD_FCNTL_RESPOND 0x1 */
 /* enum: Respond to and Issue flow control. */
-#define	MC_CMD_FCNTL_BIDIR 0x2
-/* enum: Auto neg flow control. */
-#define	MC_CMD_FCNTL_AUTO 0x3
-/* enum: Priority flow control (eftest builds only). */
-#define	MC_CMD_FCNTL_QBB 0x4
+/*               MC_CMD_FCNTL_BIDIR 0x2 */
+/* enum: Auto negotiate flow control. */
+/*               MC_CMD_FCNTL_AUTO 0x3 */
+/* enum: Priority flow control. This is only supported on KSB. */
+/*               MC_CMD_FCNTL_QBB 0x4 */
 /* enum: Issue flow control. */
-#define	MC_CMD_FCNTL_GENERATE 0x5
+/*               MC_CMD_FCNTL_GENERATE 0x5 */
 #define	MC_CMD_SET_MAC_IN_FLAGS_OFST 24
 #define	MC_CMD_SET_MAC_IN_FLAGS_LEN 4
 #define	MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
@@ -6816,9 +7764,9 @@
 /*               MC_CMD_FCNTL_RESPOND 0x1 */
 /* enum: Respond to and Issue flow control. */
 /*               MC_CMD_FCNTL_BIDIR 0x2 */
-/* enum: Auto neg flow control. */
+/* enum: Auto negotiate flow control. */
 /*               MC_CMD_FCNTL_AUTO 0x3 */
-/* enum: Priority flow control (eftest builds only). */
+/* enum: Priority flow control. This is only supported on KSB. */
 /*               MC_CMD_FCNTL_QBB 0x4 */
 /* enum: Issue flow control. */
 /*               MC_CMD_FCNTL_GENERATE 0x5 */
@@ -6885,9 +7833,9 @@
 /*               MC_CMD_FCNTL_RESPOND 0x1 */
 /* enum: Respond to and Issue flow control. */
 /*               MC_CMD_FCNTL_BIDIR 0x2 */
-/* enum: Auto neg flow control. */
+/* enum: Auto negotiate flow control. */
 /*               MC_CMD_FCNTL_AUTO 0x3 */
-/* enum: Priority flow control (eftest builds only). */
+/* enum: Priority flow control. This is only supported on KSB. */
 /*               MC_CMD_FCNTL_QBB 0x4 */
 /* enum: Issue flow control. */
 /*               MC_CMD_FCNTL_GENERATE 0x5 */
@@ -7542,6 +8490,36 @@
 /*            Other enum values, see field(s): */
 /*               MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
 
+/* MC_CMD_MAC_STATS_V5_OUT_DMA msgresponse */
+#define	MC_CMD_MAC_STATS_V5_OUT_DMA_LEN 0
+
+/* MC_CMD_MAC_STATS_V5_OUT_NO_DMA msgresponse */
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V5*64))>>3)
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_OFST 0
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LEN 8
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
+#define	MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V5
+/* enum property: index */
+/* enum: Start of V5 stats buffer space */
+#define	MC_CMD_MAC_V5_DMABUF_START 0x7c
+/* enum: Link toggle counter: Number of times the link has toggled between
+ * up/down and down/up
+ */
+#define	MC_CMD_MAC_LINK_TOGGLES 0x7c
+/* enum: This includes the space at offset 125 which is the final
+ * GENERATION_END in a MAC_STATS_V5 response and otherwise unused.
+ */
+#define	MC_CMD_MAC_NSTATS_V5 0x7e
+/*            Other enum values, see field(s): */
+/*               MC_CMD_MAC_STATS_V4_OUT_NO_DMA/STATISTICS */
+
 
 /***********************************/
 /* MC_CMD_SRIOV
@@ -9410,6 +10388,28 @@
 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
 #define	MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
 
+/* MC_CMD_GET_RESOURCE_LIMITS_IN_V2 msgrequest */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_LEN 8
+/* What type of allocation to count. */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_REQUEST_TYPE_OFST 0
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_REQUEST_TYPE_LEN 4
+/* enum: Command returns the number of each resource that the function has
+ * currently allocated.
+ */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_ALLOCATED 0x0
+/* enum: Command returns the maximum number of each resource that it could be
+ * possible for the function to allocate (ie assuming that other functions have
+ * nothing allocated beyond their minimum reservations (if any).
+ */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_MAX_POSSIBLE 0x1
+/* What type of resource to count. */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_RESOURCE_TYPE_OFST 4
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_RESOURCE_TYPE_LEN 4
+/* enum: Count full-featured (X2-style) queues */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_FULL_FEATURED_QUEUE 0x0
+/* enum: Count low-latency (X3-style) queues */
+#define	MC_CMD_GET_RESOURCE_LIMITS_IN_V2_LOW_LATENCY_QUEUE 0x1
+
 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
@@ -10515,7 +11515,7 @@
 /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
  * Get descriptions for a set of sensors, specified as an array of sensor
  * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. Any handles which do not
- * correspond to a sensor currently managed by the MC will be dropped from
+ * correspond to a sensor currently managed by the MC will be dropped from from
  * the response. This may happen when a sensor table update is in progress, and
  * effectively means the set of usable sensors is the intersection between the
  * sets of sensors known to the driver and the MC. On Riverhead this command is
@@ -10562,7 +11562,7 @@
  * broken sensor, then the state of the response's MC_CMD_DYNAMIC_SENSORS_VALUE
  * entry will be set to BROKEN, and any value provided should be treated as
  * erroneous. Any handles which do not correspond to a sensor currently managed
- * by the MC will be dropped from the response. This may happen when a
+ * by the MC will be dropped from from the response. This may happen when a
  * sensor table update is in progress, and effectively means the set of usable
  * sensors is the intersection between the sets of sensors known to the driver
  * and the MC. On Riverhead this command is implemented as a wrapper for
@@ -10641,6 +11641,2644 @@
 /* MC_CMD_EVENT_CTRL_OUT msgrequest */
 #define	MC_CMD_EVENT_CTRL_OUT_LEN 0
 
+/* HNIC_FIFO_SIZE_PARAMS structuredef: HNIC FIFO size parameters */
+#define	HNIC_FIFO_SIZE_PARAMS_LEN 12
+/* FIFO handle */
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_SIZE_PARAMS_FIFO_HANDLE_WIDTH 32
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_OFST 4
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_LEN 4
+#define	HNIC_FIFO_SIZE_PARAMS_ENABLED_OFST 4
+#define	HNIC_FIFO_SIZE_PARAMS_ENABLED_LBN 0
+#define	HNIC_FIFO_SIZE_PARAMS_ENABLED_WIDTH 1
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_LBN 32
+#define	HNIC_FIFO_SIZE_PARAMS_FLAGS_WIDTH 32
+/* Bytes allocated to this FIFO */
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_OFST 8
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_LEN 4
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_LBN 64
+#define	HNIC_FIFO_SIZE_PARAMS_ALLOC_SIZE_WIDTH 32
+
+/* HNIC_FIFO_DELAY_PARAMS structuredef: HNIC FIFO delay parameters */
+#define	HNIC_FIFO_DELAY_PARAMS_LEN 16
+/* FIFO handle */
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_DELAY_PARAMS_FIFO_HANDLE_WIDTH 32
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_OFST 4
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_OVERRIDE_OFST 4
+#define	HNIC_FIFO_DELAY_PARAMS_OVERRIDE_LBN 0
+#define	HNIC_FIFO_DELAY_PARAMS_OVERRIDE_WIDTH 1
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_LBN 32
+#define	HNIC_FIFO_DELAY_PARAMS_FLAGS_WIDTH 32
+/* XOFF threshold Only applies if the OVERRIDE flag is set. Represented in
+ * bytes
+ */
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_OFST 8
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_LBN 64
+#define	HNIC_FIFO_DELAY_PARAMS_XOFF_THRESHOLD_WIDTH 32
+/* XON threshold Only applies if the OVERRIDE flag is set. Represented in bytes
+ */
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_OFST 12
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_LEN 4
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_LBN 96
+#define	HNIC_FIFO_DELAY_PARAMS_XON_THRESHOLD_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_CONFIG
+ * Query the static HNIC port configuration for a physical port. Returns ENODEV
+ * if the target does not correspond to a physical port, or EPERM if the caller
+ * does not have permission to administer it. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_CONFIG instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG 0x1d6
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_MSGSET 0x1d6
+#undef	MC_CMD_0x1d6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_CONFIG_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_CONFIG_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LENMIN 12
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LENMAX 252
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_LEN(num) (12+4*(num))
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_NUM(len) (((len)-12)/4)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_REGION_SIZE_LEN 4
+/* Allocation granularity, in bytes. All partitioning of the buffer region must
+ * be in multiples of this value.
+ */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_LEN 4
+/* Array of FIFO handles, NUM_FIFOS items long. */
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_OFST 12
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MINNUM 0
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM 60
+#define	MC_CMD_GET_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM_MCDI2 252
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_FIFO_SIZING
+ * Returns the current state of the FIFO sizing configuration for all of the
+ * FIFOs assigned to a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING 0x1d7
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_MSGSET 0x1d7
+#undef	MC_CMD_0x1d7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LENMIN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LENMAX 248
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_LEN(num) (8+12*(num))
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_NUM(len) (((len)-8)/12)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM 20
+#define	MC_CMD_GET_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 84
+
+
+/***********************************/
+/* MC_CMD_SET_HNIC_PORT_FIFO_SIZING
+ * Sets the FIFO sizing configuration for a physical port. This is disruptive
+ * to port operation and will cause the link to drop while the port is
+ * reconfigured. Returns ENODEV if the target does not correspond to a physical
+ * port, or EPERM if the caller does not have permission to administer it, or
+ * EINVAL if the sizing parameters are invalid. This command is deprecated. Use
+ * MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING instead.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING 0x1d8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_MSGSET 0x1d8
+#undef	MC_CMD_0x1d8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LENMIN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LENMAX 244
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LENMAX_MCDI2 1012
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_LEN(num) (16+12*(num))
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_NUM(len) (((len)-16)/12)
+/* Target port to configure. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies
+ * the port by MAE port and link end, but this must correspond to a physical
+ * port to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current size configuration.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_OFST 12
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_OFST 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM 19
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 83
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_SIZING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_PRIO_MAPPING
+ * Returns the current state of the 802.1Q priority to FIFO mapping
+ * configuration for a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING 0x1d9
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1d9
+#undef	MC_CMD_0x1d9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1d9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_LEN 32
+/* FIFO handle for each Priority Code Point(PCP), in order from 0 to 7. */
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_NUM 8
+
+
+/***********************************/
+/* MC_CMD_SET_HNIC_PORT_PRIO_MAPPING
+ * Sets the PCP priority to FIFO mapping configuration for a physical port.
+ * Returns ENODEV if the target does not correspond to a physical port, or
+ * EPERM if the caller does not have permission to administer it, or EINVAL if
+ * any of the FIFO handles are invalid in some way. This command is deprecated.
+ * Use MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING instead.
+ */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING 0x1da
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1da
+#undef	MC_CMD_0x1da_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1da_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_LEN 44
+/* Target port to configure. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies
+ * the port by MAE port and link end, but this must correspond to a physical
+ * port to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 8
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* FIFO handle for each PCP value, in order from 0 to 7. */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_OFST 12
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_NUM 8
+
+/* MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_SET_HNIC_PORT_PRIO_MAPPING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Returns the current state of the FIFO delay parameters configuration for all
+ * of the FIFOs assigned to a physical port. Returns ENODEV if the target does
+ * not correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it. This command is deprecated. Use
+ * MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS instead.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS 0x1db
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1db
+#undef	MC_CMD_0x1db_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1db_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN 12
+/* Target port to query. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies the
+ * port by MAE port and link end, but this must correspond to a physical port
+ * to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 8
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMIN 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX 244
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX_MCDI2 1012
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN(num) (4+16*(num))
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_NUM(len) (((len)-4)/16)
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_OFST 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_OFST 4
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM 15
+#define	MC_CMD_GET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 63
+
+
+/***********************************/
+/* MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Sets the FIFO delay parameters configuration for a physical port. This is
+ * not disruptive to port operation. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it, or EINVAL if the sizing parameters are invalid.
+ * This command is deprecated. Use MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS
+ * instead
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS 0x1dc
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1dc
+#undef	MC_CMD_0x1dc_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1dc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMIN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX 240
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX_MCDI2 1008
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN(num) (16+16*(num))
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_NUM(len) (((len)-16)/16)
+/* Target port to configure. Uses MAE_LINK_ENDPOINT_SELECTOR which identifies
+ * the port by MAE port and link end, but this must correspond to a physical
+ * port to be valid. See the structure definition for more details.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_HI_WIDTH 32
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_TARGET_FLAT_HI_WIDTH 32
+/* Traffic direction to query. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 8
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current delay
+ * configuration.
+ */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_OFST 12
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_OFST 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM 14
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 62
+
+/* MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_SET_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN 0
+
+/* MC_CMD_MAC_FLAGS structuredef */
+#define	MC_CMD_MAC_FLAGS_LEN 4
+/* The enums defined in this field are used as indices into the
+ * MC_CMD_MAC_FLAGS bitmask.
+ */
+#define	MC_CMD_MAC_FLAGS_MASK_OFST 0
+#define	MC_CMD_MAC_FLAGS_MASK_LEN 4
+/* enum property: bitshift */
+/* enum: Include the FCS in the packet data delivered to the host. Ignored if
+ * RX_INCLUDE_FCS not set in capabilities.
+ */
+#define	MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS 0x0
+#define	MC_CMD_MAC_FLAGS_MASK_LBN 0
+#define	MC_CMD_MAC_FLAGS_MASK_WIDTH 32
+
+/* MC_CMD_TRANSMISSION_MODE structuredef */
+#define	MC_CMD_TRANSMISSION_MODE_LEN 4
+#define	MC_CMD_TRANSMISSION_MODE_MASK_OFST 0
+#define	MC_CMD_TRANSMISSION_MODE_MASK_LEN 4
+/* enum property: value */
+#define	MC_CMD_TRANSMISSION_MODE_PROMSC_MODE 0x0 /* enum */
+#define	MC_CMD_TRANSMISSION_MODE_UNCST_MODE 0x1 /* enum */
+#define	MC_CMD_TRANSMISSION_MODE_BRDCST_MODE 0x2 /* enum */
+#define	MC_CMD_TRANSMISSION_MODE_MASK_LBN 0
+#define	MC_CMD_TRANSMISSION_MODE_MASK_WIDTH 32
+
+/* MC_CMD_MAC_CONFIG_OPTIONS structuredef */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_LEN 4
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_OFST 0
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_LEN 4
+/* enum property: bitmask */
+/* enum: Configure the MAC address. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_ADDR 0x0
+/* enum: Configure the maximum frame length. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN 0x1
+/* enum: Configure flow control. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL 0x2
+/* enum: Configure the transmission mode. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_TRANSMISSION_MODE 0x3
+/* enum: Configure FCS. */
+#define	MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS 0x4
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_LBN 0
+#define	MC_CMD_MAC_CONFIG_OPTIONS_MASK_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_MAC_CTRL
+ * Set MAC configuration. Return code: 0, EINVAL, ENOTSUP
+ */
+#define	MC_CMD_MAC_CTRL 0x1df
+#define	MC_CMD_MAC_CTRL_MSGSET 0x1df
+#undef	MC_CMD_0x1df_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1df_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_MAC_CTRL_IN msgrequest */
+#define	MC_CMD_MAC_CTRL_IN_LEN 32
+/* Handle for selected network port. */
+#define	MC_CMD_MAC_CTRL_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_CTRL_IN_PORT_HANDLE_LEN 4
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set.
+ */
+#define	MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_OFST 4
+#define	MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_CONFIG_OPTIONS/MASK */
+/* MAC address of the device. */
+#define	MC_CMD_MAC_CTRL_IN_ADDR_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LEN 8
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_CTRL_IN_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_CTRL_IN_ADDR_HI_WIDTH 32
+/* Includes the ethernet header, optional VLAN tags, payload and FCS. */
+#define	MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_OFST 16
+#define	MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_LEN 4
+/* Settings for flow control. */
+#define	MC_CMD_MAC_CTRL_IN_FCNTL_OFST 20
+#define	MC_CMD_MAC_CTRL_IN_FCNTL_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_FCNTL/MASK */
+/* Configure the MAC to transmit in one of promiscuous, unicast or broadcast
+ * mode.
+ */
+#define	MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_OFST 24
+#define	MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_TRANSMISSION_MODE/MASK */
+/* Flags to control and expand the configuration of the MAC. */
+#define	MC_CMD_MAC_CTRL_IN_FLAGS_OFST 28
+#define	MC_CMD_MAC_CTRL_IN_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_FLAGS/MASK */
+
+/* MC_CMD_MAC_CTRL_IN_V2 msgrequest: Updated MAC_CTRL with QBB mask */
+#define	MC_CMD_MAC_CTRL_IN_V2_LEN 33
+/* Handle for selected network port. */
+#define	MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_LEN 4
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set.
+ */
+#define	MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_OFST 4
+#define	MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_CONFIG_OPTIONS/MASK */
+/* MAC address of the device. */
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LEN 8
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_WIDTH 32
+/* Includes the ethernet header, optional VLAN tags, payload and FCS. */
+#define	MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_OFST 16
+#define	MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_LEN 4
+/* Settings for flow control. */
+#define	MC_CMD_MAC_CTRL_IN_V2_FCNTL_OFST 20
+#define	MC_CMD_MAC_CTRL_IN_V2_FCNTL_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_FCNTL/MASK */
+/* Configure the MAC to transmit in one of promiscuous, unicast or broadcast
+ * mode.
+ */
+#define	MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_OFST 24
+#define	MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_TRANSMISSION_MODE/MASK */
+/* Flags to control and expand the configuration of the MAC. */
+#define	MC_CMD_MAC_CTRL_IN_V2_FLAGS_OFST 28
+#define	MC_CMD_MAC_CTRL_IN_V2_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_FLAGS/MASK */
+/* Priority-based flow control mask (QBB). PRIO7 corresponds to the highest
+ * priority, and PRIO0 to the lowest. This field is only used when CFG_FCNTL is
+ * set and FCNTL is QBB
+ */
+#define	MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_OFST 32
+#define	MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_LEN 1
+/* enum property: bitmask */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO0 0x0 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO1 0x1 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO2 0x2 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO3 0x3 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO4 0x4 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO5 0x5 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO6 0x6 /* enum */
+#define	MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO7 0x7 /* enum */
+
+/* MC_CMD_MAC_CTRL_OUT msgresponse */
+#define	MC_CMD_MAC_CTRL_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_MAC_STATE
+ * Read the MAC state. Return code: 0, ETIME.
+ */
+#define	MC_CMD_MAC_STATE 0x1e0
+#define	MC_CMD_MAC_STATE_MSGSET 0x1e0
+#undef	MC_CMD_0x1e0_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e0_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_MAC_STATE_IN msgrequest */
+#define	MC_CMD_MAC_STATE_IN_LEN 4
+/* Handle for selected network port. */
+#define	MC_CMD_MAC_STATE_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_STATE_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_MAC_STATE_OUT msgresponse */
+#define	MC_CMD_MAC_STATE_OUT_LEN 32
+/* The configured maximum frame length of the MAC. */
+#define	MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_OFST 0
+#define	MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_LEN 4
+/* This returns the negotiated flow control value. */
+#define	MC_CMD_MAC_STATE_OUT_FCNTL_OFST 4
+#define	MC_CMD_MAC_STATE_OUT_FCNTL_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_FCNTL/MASK */
+/* MAC address of the device. */
+#define	MC_CMD_MAC_STATE_OUT_ADDR_OFST 8
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LEN 8
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_STATE_OUT_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_STATE_OUT_ADDR_HI_WIDTH 32
+/* Flags indicating MAC faults. */
+#define	MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_OFST 16
+#define	MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_LEN 4
+/* enum property: bitshift */
+/* enum: Indicates a local MAC fault. */
+#define	MC_CMD_MAC_STATE_OUT_LOCAL 0x0
+/* enum: Indicates a remote MAC fault. */
+#define	MC_CMD_MAC_STATE_OUT_REMOTE 0x1
+/* enum: Indicates a pending reconfiguration of the MAC. */
+#define	MC_CMD_MAC_STATE_OUT_PENDING_RECONFIG 0x2
+/* The flags that were used to configure the MAC. This is a copy of the FLAGS
+ * field in the MC_CMD_MAC_CTRL_IN command.
+ */
+#define	MC_CMD_MAC_STATE_OUT_FLAGS_OFST 20
+#define	MC_CMD_MAC_STATE_OUT_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_FLAGS/MASK */
+/* The transmission mode that was used to configure the MAC. This is a copy of
+ * the TRANSMISSION_MODE field in the MC_CMD_MAC_CTRL_IN command.
+ */
+#define	MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_OFST 24
+#define	MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_LEN 4
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_TRANSMISSION_MODE/MASK */
+/* The control flags that were used to configure the MAC. This is a copy of the
+ * CONTROL field in the MC_CMD_MAC_CTRL_IN command.
+ */
+#define	MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_OFST 28
+#define	MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_MAC_CONFIG_OPTIONS/MASK */
+
+
+/***********************************/
+/* MC_CMD_GET_MPORT_HANDLE
+ * Obtain a handle to an mport identified by the provided target. Return code:
+ * 0, ENOENT
+ */
+#define	MC_CMD_GET_MPORT_HANDLE 0x1e1
+#define	MC_CMD_GET_MPORT_HANDLE_MSGSET 0x1e1
+#undef	MC_CMD_0x1e1_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e1_PRIVILEGE_CTG SRIOV_CTG_MAE
+
+/* MC_CMD_GET_MPORT_HANDLE_IN msgrequest */
+#define	MC_CMD_GET_MPORT_HANDLE_IN_LEN 4
+/* Virtual port to get handle for. This uses the MAE_LINK_ENDPOINT_SELECTOR
+ * which identifies a real or virtual network port by MAE port and link end.
+ */
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_LEN 4
+/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 3
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_LINK_END_OFST 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_LINK_END_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LEN 8
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_LBN 0
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_LO_WIDTH 32
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_OFST 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_LEN 4
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_LBN 32
+#define	MC_CMD_GET_MPORT_HANDLE_IN_TARGET_FLAT_HI_WIDTH 32
+
+/* MC_CMD_GET_MPORT_HANDLE_OUT msgresponse */
+#define	MC_CMD_GET_MPORT_HANDLE_OUT_LEN 4
+/* Handle for selected mport. */
+#define	MC_CMD_GET_MPORT_HANDLE_OUT_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_MPORT_HANDLE_OUT_PORT_HANDLE_LEN 4
+
+
+/***********************************/
+/* MC_CMD_GET_ASSIGNED_PORT_HANDLE
+ * Obtain a handle that can be operated on to configure and query the status of
+ * the link. ENOENT is returned when no port is assigned to the client. Return
+ * code: 0, ENOENT
+ */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE 0x1e2
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_MSGSET 0x1e2
+#undef	MC_CMD_0x1e2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN msgrequest */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN 0
+
+/* MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT msgresponse */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN 4
+/* Handle for assigned port. */
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_LEN 4
+
+/* MC_CMD_STAT_ID structuredef */
+#define	MC_CMD_STAT_ID_LEN 4
+#define	MC_CMD_STAT_ID_SOURCE_ID_OFST 0
+#define	MC_CMD_STAT_ID_SOURCE_ID_LEN 2
+/* enum property: index */
+/* enum: Internal markers (generation start and end markers) */
+#define	MC_CMD_STAT_ID_MARKER 0x1
+/* enum: Network port MAC statistics. */
+#define	MC_CMD_STAT_ID_MAC 0x2
+/* enum: Network port PHY statistics. */
+#define	MC_CMD_STAT_ID_PHY 0x3
+#define	MC_CMD_STAT_ID_SOURCE_ID_LBN 0
+#define	MC_CMD_STAT_ID_SOURCE_ID_WIDTH 16
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_OFST 2
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_LEN 2
+/* enum property: index */
+/* enum: This value is used to mark the start of a generation of statistics for
+ * DMA synchronization. It is incremented whenever a new set of statistics is
+ * transferred. Always the first entry in the DMA buffer.
+ */
+#define	MC_CMD_STAT_ID_GENERATION_START 0x1
+/* enum: This value is used to mark the end of a generation of statistics for
+ * DMA synchronizaion. Always the last entry in the DMA buffer and set to the
+ * same value as GENERATION_START. The host driver must compare the
+ * GENERATION_START and GENERATION_END values to verify that the DMA buffer is
+ * consistent upon copying the the DMA buffer. If they do not match, it means
+ * that new DMA transfer has started while the host driver was copying the DMA
+ * buffer. In this case, the host driver must repeat the copy operation.
+ */
+#define	MC_CMD_STAT_ID_GENERATION_END 0x2
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_LBN 16
+#define	MC_CMD_STAT_ID_MARKER_STAT_ID_WIDTH 16
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_OFST 2
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_LEN 2
+/* enum property: index */
+/* enum: Total number of packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_PKTS 0x1
+/* enum: Pause frames transmitted. */
+#define	MC_CMD_STAT_ID_TX_PAUSE_PKTS 0x2
+/* enum: Control frames transmitted. */
+#define	MC_CMD_STAT_ID_TX_CONTROL_PKTS 0x3
+/* enum: Unicast packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_UNICAST_PKTS 0x4
+/* enum: Multicast packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_MULTICAST_PKTS 0x5
+/* enum: Broadcast packets transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_BROADCAST_PKTS 0x6
+/* enum: Bytes transmitted (includes pause frames). */
+#define	MC_CMD_STAT_ID_TX_BYTES 0x7
+/* enum: Bytes transmitted with bad CRC. */
+#define	MC_CMD_STAT_ID_TX_BAD_BYTES 0x8
+/* enum: Bytes transmitted with good CRC. */
+#define	MC_CMD_STAT_ID_TX_GOOD_BYTES 0x9
+/* enum: Packets transmitted with length less than 64 bytes. */
+#define	MC_CMD_STAT_ID_TX_LT64_PKTS 0xa
+/* enum: Packets transmitted with length equal to 64 bytes. */
+#define	MC_CMD_STAT_ID_TX_64_PKTS 0xb
+/* enum: Packets transmitted with length between 65 and 127 bytes. */
+#define	MC_CMD_STAT_ID_TX_65_TO_127_PKTS 0xc
+/* enum: Packets transmitted with length between 128 and 255 bytes. */
+#define	MC_CMD_STAT_ID_TX_128_TO_255_PKTS 0xd
+/* enum: Packets transmitted with length between 256 and 511 bytes. */
+#define	MC_CMD_STAT_ID_TX_256_TO_511_PKTS 0xe
+/* enum: Packets transmitted with length between 512 and 1023 bytes. */
+#define	MC_CMD_STAT_ID_TX_512_TO_1023_PKTS 0xf
+/* enum: Packets transmitted with length between 1024 and 1518 bytes. */
+#define	MC_CMD_STAT_ID_TX_1024_TO_15XX_PKTS 0x10
+/* enum: Packets transmitted with length between 1519 and 9216 bytes. */
+#define	MC_CMD_STAT_ID_TX_15XX_TO_JUMBO_PKTS 0x11
+/* enum: Packets transmitted with length greater than 9216 bytes. */
+#define	MC_CMD_STAT_ID_TX_GTJUMBO_PKTS 0x12
+/* enum: Packets transmitted with bad FCS. */
+#define	MC_CMD_STAT_ID_TX_BAD_FCS_PKTS 0x13
+/* enum: Packets transmitted with good FCS. */
+#define	MC_CMD_STAT_ID_TX_GOOD_FCS_PKTS 0x14
+/* enum: Packets received. */
+#define	MC_CMD_STAT_ID_RX_PKTS 0x15
+/* enum: Pause frames received. */
+#define	MC_CMD_STAT_ID_RX_PAUSE_PKTS 0x16
+/* enum: Total number of good packets received. */
+#define	MC_CMD_STAT_ID_RX_GOOD_PKTS 0x17
+/* enum: Total number of BAD packets received. */
+#define	MC_CMD_STAT_ID_RX_BAD_PKTS 0x18
+/* enum: Total number of control frames received. */
+#define	MC_CMD_STAT_ID_RX_CONTROL_PKTS 0x19
+/* enum: Total number of unicast packets received. */
+#define	MC_CMD_STAT_ID_RX_UNICAST_PKTS 0x1a
+/* enum: Total number of multicast packets received. */
+#define	MC_CMD_STAT_ID_RX_MULTICAST_PKTS 0x1b
+/* enum: Total number of broadcast packets received. */
+#define	MC_CMD_STAT_ID_RX_BROADCAST_PKTS 0x1c
+/* enum: Total number of bytes received. */
+#define	MC_CMD_STAT_ID_RX_BYTES 0x1d
+/* enum: Total number of bytes received with bad CRC. */
+#define	MC_CMD_STAT_ID_RX_BAD_BYTES 0x1e
+/* enum: Total number of bytes received with GOOD CRC. */
+#define	MC_CMD_STAT_ID_RX_GOOD_BYTES 0x1f
+/* enum: Packets received with length equal to 64 bytes. */
+#define	MC_CMD_STAT_ID_RX_64_PKTS 0x20
+/* enum: Packets received with length between 65 and 127 bytes. */
+#define	MC_CMD_STAT_ID_RX_65_TO_127_PKTS 0x21
+/* enum: Packets received with length between 128 and 255 bytes. */
+#define	MC_CMD_STAT_ID_RX_128_TO_255_PKTS 0x22
+/* enum: Packets received with length between 256 and 511 bytes. */
+#define	MC_CMD_STAT_ID_RX_256_TO_511_PKTS 0x23
+/* enum: Packets received with length between 512 and 1023 bytes. */
+#define	MC_CMD_STAT_ID_RX_512_TO_1023_PKTS 0x24
+/* enum: Packets received with length between 1024 and 1518 bytes. */
+#define	MC_CMD_STAT_ID_RX_1024_TO_15XX_PKTS 0x25
+/* enum: Packets received with length between 1519 and 9216 bytes. */
+#define	MC_CMD_STAT_ID_RX_15XX_TO_JUMBO_PKTS 0x26
+/* enum: Packets received with length greater than 9216 bytes. */
+#define	MC_CMD_STAT_ID_RX_GTJUMBO_PKTS 0x27
+/* enum: Packets received with length less than 64 bytes. */
+#define	MC_CMD_STAT_ID_RX_UNDERSIZE_PKTS 0x28
+/* enum: Packets received with bad FCS. */
+#define	MC_CMD_STAT_ID_RX_BAD_FCS_PKTS 0x29
+/* enum: Packets received with GOOD FCS. */
+#define	MC_CMD_STAT_ID_RX_GOOD_FCS_PKTS 0x2a
+/* enum: Packets received with overflow. */
+#define	MC_CMD_STAT_ID_RX_OVERFLOW_PKTS 0x2b
+/* enum: Packets received with symbol error. */
+#define	MC_CMD_STAT_ID_RX_SYMBOL_ERROR_PKTS 0x2c
+/* enum: Packets received with alignment error. */
+#define	MC_CMD_STAT_ID_RX_ALIGN_ERROR_PKTS 0x2d
+/* enum: Packets received with length error. */
+#define	MC_CMD_STAT_ID_RX_LENGTH_ERROR_PKTS 0x2e
+/* enum: Packets received with internal error. */
+#define	MC_CMD_STAT_ID_RX_INTERNAL_ERROR_PKTS 0x2f
+/* enum: Packets received with jabber. These packets are larger than the
+ * allowed maximum receive unit (MRU). This indicates that a packet either has
+ * a bad CRC or has an RX error.
+ */
+#define	MC_CMD_STAT_ID_RX_JABBER_PKTS 0x30
+/* enum: Packets dropped due to having no descriptor. This is a datapath stat
+ */
+#define	MC_CMD_STAT_ID_RX_NODESC_DROPS 0x31
+/* enum: Packets received with lanes 0 and 1 character error. */
+#define	MC_CMD_STAT_ID_RX_LANES01_CHAR_ERR 0x32
+/* enum: Packets received with lanes 2 and 3 character error. */
+#define	MC_CMD_STAT_ID_RX_LANES23_CHAR_ERR 0x33
+/* enum: Packets received with lanes 0 and 1 disparity error. */
+#define	MC_CMD_STAT_ID_RX_LANES01_DISP_ERR 0x34
+/* enum: Packets received with lanes 2 and 3 disparity error. */
+#define	MC_CMD_STAT_ID_RX_LANES23_DISP_ERR 0x35
+/* enum: Packets received with match fault. */
+#define	MC_CMD_STAT_ID_RX_MATCH_FAULT 0x36
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_LBN 16
+#define	MC_CMD_STAT_ID_MAC_STAT_ID_WIDTH 16
+/* Include FEC stats. */
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_OFST 2
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_LEN 2
+/* enum property: index */
+/* enum: Number of uncorrected FEC codewords on link (RS-FEC only from Medford2
+ * onwards)
+ */
+#define	MC_CMD_STAT_ID_FEC_UNCORRECTED_ERRORS 0x1
+/* enum: Number of corrected FEC codewords on link (RS-FEC only from Medford2
+ * onwards)
+ */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_ERRORS 0x2
+/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE0 0x3
+/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE1 0x4
+/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE2 0x5
+/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
+#define	MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE3 0x6
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_LBN 16
+#define	MC_CMD_STAT_ID_PHY_STAT_ID_WIDTH 16
+
+/* MC_CMD_STAT_DESC structuredef: Structure describing the layout and size of
+ * the stats DMA buffer descriptor.
+ */
+#define	MC_CMD_STAT_DESC_LEN 8
+/* Unique identifier of the statistic. Formatted as MC_CMD_STAT_ID */
+#define	MC_CMD_STAT_DESC_STAT_ID_OFST 0
+#define	MC_CMD_STAT_DESC_STAT_ID_LEN 4
+#define	MC_CMD_STAT_DESC_STAT_ID_LBN 0
+#define	MC_CMD_STAT_DESC_STAT_ID_WIDTH 32
+/* See structuredef: MC_CMD_STAT_ID */
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_OFST 0
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LBN 0
+#define	MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_WIDTH 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_OFST 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LBN 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_WIDTH 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_OFST 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LBN 16
+#define	MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_WIDTH 16
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_OFST 2
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LBN 16
+#define	MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_WIDTH 16
+/* Index of the statistic in the DMA buffer. */
+#define	MC_CMD_STAT_DESC_STAT_INDEX_OFST 4
+#define	MC_CMD_STAT_DESC_STAT_INDEX_LEN 2
+#define	MC_CMD_STAT_DESC_STAT_INDEX_LBN 32
+#define	MC_CMD_STAT_DESC_STAT_INDEX_WIDTH 16
+/* Reserved for future extension (e.g. flags field) - currently always 0. */
+#define	MC_CMD_STAT_DESC_RESERVED_OFST 6
+#define	MC_CMD_STAT_DESC_RESERVED_LEN 2
+#define	MC_CMD_STAT_DESC_RESERVED_LBN 48
+#define	MC_CMD_STAT_DESC_RESERVED_WIDTH 16
+
+
+/***********************************/
+/* MC_CMD_MAC_STATISTICS_DESCRIPTOR
+ * Get a list of descriptors that describe the layout and size of the stats
+ * buffer required for retrieving statistics for a given port. Each entry in
+ * the list is formatted as MC_CMD_STAT_DESC and provides the ID of each stat
+ * and its location and size in the buffer. It also gives the overall minimum
+ * size of the DMA buffer required when DMA mode is used. Note that the first
+ * and last entries in the list are reserved for the generation start
+ * (MC_CMD_MARKER_STAT_GENERATION_START) and end
+ * (MC_CMD_MARKER_STAT_GENERATION_END) markers respectively, to be used for DMA
+ * synchronisation as described in the documentation for the relevant enum
+ * entries. The entries are present in the buffer even if DMA mode is not used.
+ * Provisions are made (but currently unused) for extending the size of the
+ * descriptors, extending the size of the list beyond the maximum MCDI response
+ * size, as well as the dynamic runtime updates of the list. Returns: 0 on
+ * success, ENOENT on non-existent port handle
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR 0x1e3
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_MSGSET 0x1e3
+#undef	MC_CMD_0x1e3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN msgrequest */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN 8
+/* Handle of port to get MAC statitstics descriptors for. */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_LEN 4
+/* Offset of the first entry to return, for cases where not all entries fit in
+ * the MCDI response. Should be set to 0 on initial request, and on subsequent
+ * requests updated by the number of entries already returned, as long as the
+ * MORE_ENTRIES flag is set.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_OFST 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_LEN 4
+
+/* MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT msgresponse */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMIN 28
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX 252
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LEN(num) (20+8*(num))
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(len) (((len)-20)/8)
+/* Generation number of the stats buffer. This is incremented each time the
+ * buffer is updated, and is used to verify the consistency of the buffer
+ * contents. Reserved for future extension (dynamic list updates). Currently
+ * always set to 0.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_OFST 0
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_LEN 4
+/* Minimum size of the DMA buffer required to retrieve all statistics for the
+ * port. This is the sum of the sizes of all the statistics, plus the size of
+ * the generation markers. Minimum buffer size in bytes required to fit all
+ * statistics. Drivers will typically round up this value to the granularity of
+ * the host DMA allocation units.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_OFST 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_OFST 8
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_OFST 8
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_LBN 0
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_WIDTH 1
+/* Size of the individual descriptor entry in the list. Determines the entry
+ * stride in the list. Currently always set to size of MC_CMD_STAT_DESC, larger
+ * values can be used in the future for extending the descriptor, by appending
+ * new data to the end of the existing structure.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_OFST 12
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_LEN 4
+/* Number of entries returned in the descriptor list. */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_OFST 16
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_LEN 4
+/* List of descriptors. Each entry is formatted as MC_CMD_STAT_DESC and
+ * provides the ID of each stat and its location and size in the buffer. The
+ * first and last entries are reserved for the generation start and end markers
+ * respectively.
+ */
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_OFST 20
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LEN 8
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_OFST 20
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LBN 160
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_WIDTH 32
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_OFST 24
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LEN 4
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LBN 192
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_WIDTH 32
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MINNUM 1
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM 29
+#define	MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM_MCDI2 125
+
+
+/***********************************/
+/* MC_CMD_MAC_STATISTICS
+ * Get generic MAC statistics. This call retrieves unified statistics managed
+ * by the MC. The MC will populate and provide all supported statistics in the
+ * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the
+ * aforementioned command for the format and contents of the stats DMA buffer.
+ * To ensure consistent and accurate results, it is essential for the driver to
+ * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
+ * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
+ * handle, and EINVAL on invalid parameters (DMA buffer too small)
+ */
+#define	MC_CMD_MAC_STATISTICS 0x1e4
+#define	MC_CMD_MAC_STATISTICS_MSGSET 0x1e4
+#undef	MC_CMD_0x1e4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_MAC_STATISTICS_IN msgrequest */
+#define	MC_CMD_MAC_STATISTICS_IN_LEN 20
+/* Handle of port to get MAC statistics for. */
+#define	MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_LEN 4
+/* Contains options for querying the MAC statistics. */
+#define	MC_CMD_MAC_STATISTICS_IN_CMD_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_CMD_LEN 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_LBN 0
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_CLEAR_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_CLEAR_LBN 1
+#define	MC_CMD_MAC_STATISTICS_IN_CLEAR_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_LBN 2
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_LBN 3
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1
+#define	MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_OFST 4
+#define	MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_LBN 16
+#define	MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_WIDTH 16
+/* This is the address of the DMA buffer to use for transfer of the statistics.
+ * Only valid if the DMA flag is set to 1.
+ */
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_OFST 8
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LEN 8
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_OFST 8
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LEN 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LBN 64
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_OFST 12
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LEN 4
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LBN 96
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32
+/* This is the length of the DMA buffer to use for the transfer of the
+ * statistics. The buffer should be at least DMA_BUFFER_SIZE long, as returned
+ * by MC_CMD_MAC_STATISTICS_DESCRIPTOR. If the supplied buffer is too small,
+ * the command will fail with EINVAL. Only valid if the DMA flag is set to 1.
+ */
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_LEN_OFST 16
+#define	MC_CMD_MAC_STATISTICS_IN_DMA_LEN_LEN 4
+
+/* MC_CMD_MAC_STATISTICS_OUT msgresponse */
+#define	MC_CMD_MAC_STATISTICS_OUT_LENMIN 5
+#define	MC_CMD_MAC_STATISTICS_OUT_LENMAX 252
+#define	MC_CMD_MAC_STATISTICS_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_MAC_STATISTICS_OUT_LEN(num) (4+1*(num))
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_NUM(len) (((len)-4)/1)
+/* length of the data in bytes */
+#define	MC_CMD_MAC_STATISTICS_OUT_DATALEN_OFST 0
+#define	MC_CMD_MAC_STATISTICS_OUT_DATALEN_LEN 4
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_OFST 4
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_LEN 1
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_MINNUM 1
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM 248
+#define	MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM_MCDI2 1016
+
+/* NET_PORT_HANDLE_DESC structuredef: Network port descriptor containing a port
+ * handle and attributes used, for example, in MC_CMD_ENUM_PORTS.
+ */
+#define	NET_PORT_HANDLE_DESC_LEN 53
+/* The handle to identify the port */
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_OFST 0
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_LEN 4
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_LBN 0
+#define	NET_PORT_HANDLE_DESC_PORT_HANDLE_WIDTH 32
+/* Includes the type of port e.g. physical, virtual or MAE MPORT and other
+ * properties relevant to the port.
+ */
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_OFST 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LEN 8
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_OFST 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LEN 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LBN 32
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_WIDTH 32
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_OFST 8
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LEN 4
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LBN 64
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_WIDTH 32
+#define	NET_PORT_HANDLE_DESC_PORT_TYPE_OFST 4
+#define	NET_PORT_HANDLE_DESC_PORT_TYPE_LBN 0
+#define	NET_PORT_HANDLE_DESC_PORT_TYPE_WIDTH 3
+#define	NET_PORT_HANDLE_DESC_PHYSICAL 0x0 /* enum */
+#define	NET_PORT_HANDLE_DESC_VIRTUAL 0x1 /* enum */
+#define	NET_PORT_HANDLE_DESC_MPORT 0x2 /* enum */
+#define	NET_PORT_HANDLE_DESC_IS_ZOMBIE_OFST 4
+#define	NET_PORT_HANDLE_DESC_IS_ZOMBIE_LBN 8
+#define	NET_PORT_HANDLE_DESC_IS_ZOMBIE_WIDTH 1
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LBN 32
+#define	NET_PORT_HANDLE_DESC_PORT_PROPERTIES_WIDTH 64
+/* The dynamic change that led to the port enumeration */
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_OFST 12
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_LEN 1
+/* enum: Indicates that the ENTRY_SRC field has not been initialized. */
+#define	NET_PORT_HANDLE_DESC_UNKNOWN 0x0
+/* enum: The port was enumerated at start of day. */
+#define	NET_PORT_HANDLE_DESC_PRESENT 0x1
+/* enum: The port was dynamically added. */
+#define	NET_PORT_HANDLE_DESC_ADDED 0x2
+/* enum: The port was dynamically deleted. */
+#define	NET_PORT_HANDLE_DESC_DELETED 0x3
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_LBN 96
+#define	NET_PORT_HANDLE_DESC_ENTRY_SRC_WIDTH 8
+/* This is an opaque 40 byte label exposed to users as a unique identifier of
+ * the port. It is represented as a zero-terminated ASCII string and assigned
+ * by the port administrator which is typically either the firmware for a
+ * physical port or the host software responsible for creating the virtual
+ * port. The label is conveyed to the driver after assignment, which, unlike
+ * the port administrator, does not need to know how to interpret the label.
+ */
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_OFST 13
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_LEN 40
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_LBN 104
+#define	NET_PORT_HANDLE_DESC_PORT_LABEL_WIDTH 320
+
+
+/***********************************/
+/* MC_CMD_ENUM_PORTS
+ * This command returns handles for all ports present in the system. The PCIe
+ * function type of each port (either physical or virtual) is also reported.
+ * After a start-of-day port enumeration, firmware keeps track of all available
+ * ports upon creation or deletion and updates the ports if there is a change.
+ * This command is cleared after a control interface reset (e.g. FLR,
+ * ENTITY_RESET), in which case it must be called again to reenumerate the
+ * ports. The command is also clear-on-read and repeated calls will drain the
+ * buffer.
+ */
+#define	MC_CMD_ENUM_PORTS 0x1e5
+#define	MC_CMD_ENUM_PORTS_MSGSET 0x1e5
+#undef	MC_CMD_0x1e5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e5_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_ENUM_PORTS_IN msgrequest */
+#define	MC_CMD_ENUM_PORTS_IN_LEN 0
+
+/* MC_CMD_ENUM_PORTS_OUT msgresponse */
+#define	MC_CMD_ENUM_PORTS_OUT_LENMIN 12
+#define	MC_CMD_ENUM_PORTS_OUT_LENMAX 252
+#define	MC_CMD_ENUM_PORTS_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_ENUM_PORTS_OUT_LEN(num) (12+1*(num))
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_NUM(len) (((len)-12)/1)
+/* Any unused flags are reserved and must be ignored. */
+#define	MC_CMD_ENUM_PORTS_OUT_FLAGS_OFST 0
+#define	MC_CMD_ENUM_PORTS_OUT_FLAGS_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_MORE_OFST 0
+#define	MC_CMD_ENUM_PORTS_OUT_MORE_LBN 0
+#define	MC_CMD_ENUM_PORTS_OUT_MORE_WIDTH 1
+/* The number of NET_PORT_HANDLE_DESC structures in PORT_HANDLES. */
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_OFST 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_OFST 8
+#define	MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_LEN 4
+/* Array of NET_PORT_HANDLE_DESC structures. Callers must use must use the
+ * SIZEOF_NET_PORT_HANDLE_DESC field field as the array stride between entries.
+ * This may also allow for tail padding for alignment. Fields beyond
+ * SIZEOF_NET_PORT_HANDLE_DESC are not present.
+ */
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_OFST 12
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_LEN 1
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MINNUM 0
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM 240
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM_MCDI2 1008
+/* See structuredef: NET_PORT_HANDLE_DESC */
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_OFST 12
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_OFST 16
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LEN 8
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_OFST 16
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LBN 128
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_WIDTH 32
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_OFST 20
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LEN 4
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LBN 160
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_WIDTH 32
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_LBN 128
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_WIDTH 3
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_LBN 136
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_WIDTH 1
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_OFST 24
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_LEN 1
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_OFST 25
+#define	MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_LEN 40
+
+
+/***********************************/
+/* MC_CMD_GET_TRANSCEIVER_PROPERTIES
+ * Read properties of the transceiver associated with the port. Can be either
+ * for a fixed onboard transceiver or an inserted module. The returned data is
+ * interpreted from the transceiver hardware and may be fixed up by the
+ * firmware. Use MC_CMD_GET_MODULE_DATA to get raw undecoded data.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES 0x1e6
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_MSGSET 0x1e6
+#undef	MC_CMD_0x1e6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e6_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN msgrequest */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_LEN 4
+/* Handle to port to get transceiver properties from. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT msgresponse */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LEN 89
+/* Supported technology abilities. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_OFST 0
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_LEN 16
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_ETH_TECH/TECH */
+/* Reserved for future expansion to accommodate future Ethernet technology
+ * expansion.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_OFST 16
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_LEN 16
+/* Preferred FEC modes. This is a function of the cable type and length. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_OFST 32
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               FEC_TYPE/TYPE */
+/* SFF-8042 code reported by the module. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_OFST 36
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_LEN 2
+/* Medium. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_OFST 38
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_LEN 1
+/* enum property: value */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 /* enum */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_COPPER 0x1 /* enum */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_OPTICAL 0x2 /* enum */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BACKPLANE 0x3 /* enum */
+/* Identifies the tech */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_OFST 39
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_LEN 1
+/* enum property: value */
+/*               MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 */
+/* enum: Ethernet over twisted-pair copper cables for distances up to 100
+ * meters.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASET 0x1
+/* enum: Ethernet over twin-axial, balanced copper cable. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CR 0x2
+/* enum: Ethernet over backplane for connections on the same board. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KX 0x3
+/* enum: Ethernet over a single backplane lane for connections between
+ * different boards.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KR 0x4
+/* enum: Ethernet over copper backplane. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KP 0x5
+/* enum: Ethernet over fiber optic. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASEX 0x6
+/* enum: Short range ethernet over multimode fiber optic (See IEEE 802.3 Clause
+ * 49 and 52).
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SR 0x7
+/* enum: Long range, extended range or far reach ethernet used with single mode
+ * fiber optics.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LR_ER_FR 0x8
+/* enum: Long reach multimode ethernet over multimode optical fiber. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LRM 0x9
+/* enum: Very short reach PAM4 ethernet over multimode optical fiber (see IEEE
+ * 802.3db).
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VR 0xa
+/* enum: BASE-R encoding and PAM4 over single-mode fiber with reach up to at
+ * least 500 meters (803.2 Clause 121 and 124)
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_DR 0xb
+/* String of the vendor name as intepreted by NMC firmware. NMC firmware
+ * applies workarounds for known buggy transceivers. The vendor name is
+ * presented as 16 bytes of ASCII characters padded with spaces. It can also be
+ * represented as 16 bytes of zeros if the field is unspecified for the
+ * connected module. See SFF-8472/CMIS specifications for details.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_OFST 40
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_LEN 1
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_NUM 16
+/* The vendor part number as intepreted by NMC firmware. The field is presented
+ * as 16 bytes of ASCII chars padded with spaces. It can also be 16 bytes of
+ * zeros if the field is unspecified for the connected module.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_OFST 56
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_LEN 1
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_NUM 16
+/* Serial number of the module presented as 16 bytes of ASCII characters padded
+ * with spaces. It can also be 16 bytes of zeros if the field is unspecified
+ * for the connected module. See SFF-8472/CMIS specifications for details.
+ */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_OFST 72
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_LEN 1
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_NUM 16
+/* This reports the number of module changes detected by the NMC firmware. */
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 88
+#define	MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1
+
+
+/***********************************/
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES 0x1e7
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_MSGSET 0x1e7
+#undef	MC_CMD_0x1e7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e7_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES_IN msgrequest: In this context, the port
+ * consists of the MAC and the PHY, and excludes any modules inserted into the
+ * cage. This information is fixed for a given board but not for a given ASIC.
+ * This command reports properties for the port as it is currently configured,
+ * and not its hardware capabilities, which can be better than the current
+ * configuration.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN 4
+/* Handle to the port to from which to retreive properties */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT msgresponse */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LEN 36
+/* Supported capabilities of the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_LEN 25
+/* See structuredef: MC_CMD_ETH_AN_FIELDS */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_LEN 16
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_OFST 16
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_OFST 20
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_OFST 24
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_LEN 1
+/* Number of lanes supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_OFST 25
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_LEN 1
+/* Bitmask of supported loopback modes. Where the response to this command
+ * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in
+ * preference to ensure that all available loopback modes are seen.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_OFST 26
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* This field serves as a cage index that uniquely identifies the cage to which
+ * the module is connected. This is useful when splitter cables that have
+ * multiple ports on a single cage are used.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_OFST 27
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_LEN 1
+/* This bitmask is used to specify the lanes within the cage identified by
+ * MDI_INDEX that are allocated to the port.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_OFST 28
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_LEN 1
+/* Maximum frame length supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_OFST 32
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_LEN 4
+
+/* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2 msgresponse */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN 48
+/* Supported capabilities of the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_OFST 0
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_LEN 25
+/* Number of lanes supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_OFST 25
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_LEN 1
+/* Bitmask of supported loopback modes. Where the response to this command
+ * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in
+ * preference to ensure that all available loopback modes are seen.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_OFST 26
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_LEN 1
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+/* This field serves as a cage index that uniquely identifies the cage to which
+ * the module is connected. This is useful when splitter cables that have
+ * multiple ports on a single cage are used.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_OFST 27
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_LEN 1
+/* This bitmask is used to specify the lanes within the cage identified by
+ * MDI_INDEX that are allocated to the port.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_OFST 28
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_LEN 1
+/* Maximum frame length supported by the port in its current configuration. */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_OFST 32
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_LEN 4
+/* Bitmask of supported loopback modes. This field replaces the
+ * LOOPBACK_MODES_MASK field which is defined under version 1 of this command.
+ */
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_OFST 40
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LEN 8
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_OFST 40
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LBN 320
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_WIDTH 32
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_OFST 44
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LEN 4
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LBN 352
+#define	MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_WIDTH 32
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LOOPBACK_V2/MODE */
+
+
+/***********************************/
+/* MC_CMD_GET_MODULE_DATA
+ * Read media-specific data from the PHY (e.g. SFP/SFP+ module ID information
+ * for SFP+ PHYs). This command returns raw data from the module's EEPROM and
+ * it is not interpreted by the MC. Use MC_CMD_GET_TRANSCEIVER_PROPERTIES to
+ * get interpreted data. Return code: 0, ENOENT
+ */
+#define	MC_CMD_GET_MODULE_DATA 0x1e8
+#define	MC_CMD_GET_MODULE_DATA_MSGSET 0x1e8
+#undef	MC_CMD_0x1e8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e8_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_MODULE_DATA_IN msgrequest */
+#define	MC_CMD_GET_MODULE_DATA_IN_LEN 16
+/* Handle to identify the port from which to request module properties. */
+#define	MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_LEN 4
+/* 7 bit I2C address of the device. DEPRECATED: This field is replaced by
+ * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier
+ * access.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_DEVADDR_LBN 32
+#define	MC_CMD_GET_MODULE_DATA_IN_DEVADDR_WIDTH 7
+/* 0 if the page does not support banked access, non-zero otherwise. Non-zero
+ * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
+ * region.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_BANK_OFST 6
+#define	MC_CMD_GET_MODULE_DATA_IN_BANK_LEN 2
+/* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
+ * valid if OFFSET is in the range 80h - ffh.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_PAGE_OFST 8
+#define	MC_CMD_GET_MODULE_DATA_IN_PAGE_LEN 2
+/* Offset in the range 00h - 7fh to access lower memory. Offset in the range
+ * 80h - ffh to access upper memory
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_OFFSET_OFST 10
+#define	MC_CMD_GET_MODULE_DATA_IN_OFFSET_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_IN_LENGTH_OFST 12
+#define	MC_CMD_GET_MODULE_DATA_IN_LENGTH_LEN 4
+
+/* MC_CMD_GET_MODULE_DATA_IN_V2 msgrequest: Updated MC_CMD_GET_MODULE_DATA with
+ * 8-bit wide ADDRESSING field. This new field provides a correctly aligned
+ * container for the 7-bit DEVADDR field from V1, now renamed MODULE_ADDR, to
+ * ensure proper alignment.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_LEN 16
+/* Handle to identify the port from which to request module properties. */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_LEN 4
+/* 7 bit I2C address of the device. DEPRECATED: This field is replaced by
+ * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier
+ * access.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_LBN 32
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_WIDTH 7
+/* 0 if the page does not support banked access, non-zero otherwise. Non-zero
+ * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
+ * region.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_BANK_OFST 6
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_BANK_LEN 2
+/* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
+ * valid if OFFSET is in the range 80h - ffh.
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_OFST 8
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_LEN 2
+/* Offset in the range 00h - 7fh to access lower memory. Offset in the range
+ * 80h - ffh to access upper memory
+ */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_OFST 10
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_OFST 12
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_LEN 4
+/* Container for 7 bit I2C addresses. */
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_OFST 4
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_OFST 4
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_LBN 0
+#define	MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_WIDTH 7
+
+/* MC_CMD_GET_MODULE_DATA_OUT msgresponse */
+#define	MC_CMD_GET_MODULE_DATA_OUT_LENMIN 5
+#define	MC_CMD_GET_MODULE_DATA_OUT_LENMAX 252
+#define	MC_CMD_GET_MODULE_DATA_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_GET_MODULE_DATA_OUT_LEN(num) (4+1*(num))
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_NUM(len) (((len)-4)/1)
+/* length of the data in bytes */
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATALEN_OFST 0
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATALEN_LEN 4
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_OFST 4
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_LEN 1
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_MINNUM 1
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM 248
+#define	MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM_MCDI2 1016
+
+/* EVENT_MASK structuredef */
+#define	EVENT_MASK_LEN 4
+#define	EVENT_MASK_TYPE_OFST 0
+#define	EVENT_MASK_TYPE_LEN 4
+/* enum: PORT_LINKCHANGE event is enabled */
+#define	EVENT_MASK_PORT_LINKCHANGE 0x0
+/* enum: PORT_MODULECHANGE event is enabled */
+#define	EVENT_MASK_PORT_MODULECHANGE 0x1
+#define	EVENT_MASK_TYPE_LBN 0
+#define	EVENT_MASK_TYPE_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_SET_NETPORT_EVENTS_MASK
+ */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK 0x1e9
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_MSGSET 0x1e9
+#undef	MC_CMD_0x1e9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1e9_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_SET_NETPORT_EVENTS_MASK_IN msgrequest: Enable or disable delivery of
+ * specified network port events for a given port identified by PORT_HANDLE. At
+ * start of day, or after any control interface reset (FLR, ENTITY_RESET,
+ * etc.), all event delivery is disabled for all ports associated with the
+ * control interface.
+ */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN 8
+/* Handle to port to set event delivery mask. */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
+/* Bitmask of events to enable. Event delivery is enabled when corresponding
+ * bit is 1, disabled when 0.
+ */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_OFST 4
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               EVENT_MASK/TYPE */
+
+/* MC_CMD_SET_NETPORT_EVENTS_MASK_OUT msgresponse */
+#define	MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_NETPORT_EVENTS_MASK
+ */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK 0x1ea
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_MSGSET 0x1ea
+#undef	MC_CMD_0x1ea_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ea_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_NETPORT_EVENTS_MASK_IN msgrequest: Get event delivery mask a
+ * given port identified by PORT_HANDLE.
+ */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_IN_LEN 4
+/* Handle to port to get event deliver mask for. */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_GET_NETPORT_EVENTS_MASK_OUT msgresponse */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_LEN 4
+/* Bitmask of events enabled. Event delivery is enabled when corresponding bit
+ * is 1, disabled when 0.
+ */
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_OFST 0
+#define	MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               EVENT_MASK/TYPE */
+
+
+/***********************************/
+/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS
+ */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS 0x1eb
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_MSGSET 0x1eb
+#undef	MC_CMD_0x1eb_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1eb_PRIVILEGE_CTG SRIOV_CTG_LINK
+
+/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN msgrequest: Get network port events
+ * supported by the platform. Information returned is fixed for a given NIC
+ * platform.
+ */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN_LEN 0
+
+/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT msgresponse */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_LEN 4
+/* Bitmask of events enabled. Event delivery is enabled when corresponding bit
+ * is 1, disabled when 0.
+ */
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_OFST 0
+#define	MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_LEN 4
+/* enum property: bitshift */
+/*            Enum values, see field(s): */
+/*               EVENT_MASK/TYPE */
+
+/* LINK_CHANGE_LOG structuredef */
+#define	LINK_CHANGE_LOG_LEN 16
+/* Bitmask of flags that describe the state of the link. */
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_OFST 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LEN 8
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_OFST 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_LEN 4
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_LBN 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LO_WIDTH 32
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_OFST 4
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_LEN 4
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_LBN 32
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_HI_WIDTH 32
+/* enum property: value */
+/*            Enum values, see field(s): */
+/*               MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_LBN 0
+#define	LINK_CHANGE_LOG_STATUS_FLAGS_WIDTH 64
+/* This is the time elapsed in milliseconds since the last event occurred. */
+#define	LINK_CHANGE_LOG_TIME_STAMP_OFST 8
+#define	LINK_CHANGE_LOG_TIME_STAMP_LEN 4
+#define	LINK_CHANGE_LOG_TIME_STAMP_LBN 64
+#define	LINK_CHANGE_LOG_TIME_STAMP_WIDTH 32
+/* Speed of the link. 0 if the link is down. */
+#define	LINK_CHANGE_LOG_LINK_SPEED_OFST 12
+#define	LINK_CHANGE_LOG_LINK_SPEED_LEN 4
+#define	LINK_CHANGE_LOG_LINK_SPEED_LBN 96
+#define	LINK_CHANGE_LOG_LINK_SPEED_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_LINK_LOG
+ * This command retrieves the history log of link state changes and reports the
+ * timestamp, reason for link state change and new link state. This command is
+ * clear-on-read.
+ */
+#define	MC_CMD_LINK_LOG 0x1ec
+#define	MC_CMD_LINK_LOG_MSGSET 0x1ec
+#undef	MC_CMD_0x1ec_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_LINK_LOG_IN msgrequest */
+#define	MC_CMD_LINK_LOG_IN_LEN 4
+/* A handle to identify the port on which to query the link log. */
+#define	MC_CMD_LINK_LOG_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_LINK_LOG_IN_PORT_HANDLE_LEN 4
+
+/* MC_CMD_LINK_LOG_OUT msgresponse */
+#define	MC_CMD_LINK_LOG_OUT_LENMIN 8
+#define	MC_CMD_LINK_LOG_OUT_LENMAX 248
+#define	MC_CMD_LINK_LOG_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_LINK_LOG_OUT_LEN(num) (8+16*(num))
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_NUM(len) (((len)-8)/16)
+/* Number of valid transitions of type LINK_CHANGE_LOG structures in the
+ * LINK_LOG_ARRAY
+ */
+#define	MC_CMD_LINK_LOG_OUT_NUM_LOG_ENTRIES_OFST 0
+#define	MC_CMD_LINK_LOG_OUT_NUM_LOG_ENTRIES_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_MORE_OFST 0
+#define	MC_CMD_LINK_LOG_OUT_MORE_LBN 0
+#define	MC_CMD_LINK_LOG_OUT_MORE_WIDTH 1
+/* Contains additional flags or control information related to the log
+ * response. The specific bits, e.g. MORE_ENTRIES, are described below.
+ */
+#define	MC_CMD_LINK_LOG_OUT_FLAGS_OFST 4
+#define	MC_CMD_LINK_LOG_OUT_FLAGS_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_MORE_ENTRIES_OFST 4
+#define	MC_CMD_LINK_LOG_OUT_MORE_ENTRIES_LBN 0
+#define	MC_CMD_LINK_LOG_OUT_MORE_ENTRIES_WIDTH 1
+/* Array of LINK_CHANGE_LOG structures */
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_OFST 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_LEN 16
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_MINNUM 0
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_MAXNUM 15
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_MAXNUM_MCDI2 63
+/* See structuredef: LINK_CHANGE_LOG */
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_OFST 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LEN 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_OFST 8
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_LBN 64
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_LO_WIDTH 32
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_OFST 12
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_LBN 96
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_STATUS_FLAGS_HI_WIDTH 32
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_TIME_STAMP_OFST 16
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_TIME_STAMP_LEN 4
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_LINK_SPEED_OFST 20
+#define	MC_CMD_LINK_LOG_OUT_LINK_LOG_ARRAY_LINK_SPEED_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CSR_INST_READ32
+ * Read 32bit words from an MCPU indirect memory map specified by its
+ * MAP_INDEX.
+ */
+#define	MC_CMD_CSR_INST_READ32 0x1ee
+#define	MC_CMD_CSR_INST_READ32_MSGSET 0x1ee
+#undef	MC_CMD_0x1ee_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ee_PRIVILEGE_CTG SRIOV_CTG_INSECURE
+
+/* MC_CMD_CSR_INST_READ32_IN msgrequest */
+#define	MC_CMD_CSR_INST_READ32_IN_LEN 24
+/* Address */
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_OFST 0
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LEN 8
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_OFST 0
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_LEN 4
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_LBN 0
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_LO_WIDTH 32
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_OFST 4
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_LEN 4
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_LBN 32
+#define	MC_CMD_CSR_INST_READ32_IN_ADDR_HI_WIDTH 32
+/* Step value between register addresses */
+#define	MC_CMD_CSR_INST_READ32_IN_STEP_OFST 8
+#define	MC_CMD_CSR_INST_READ32_IN_STEP_LEN 4
+/* Map index of indirect memory map */
+#define	MC_CMD_CSR_INST_READ32_IN_MAP_INDEX_OFST 12
+#define	MC_CMD_CSR_INST_READ32_IN_MAP_INDEX_LEN 4
+/* Number of words to read */
+#define	MC_CMD_CSR_INST_READ32_IN_NUM_WORDS_OFST 20
+#define	MC_CMD_CSR_INST_READ32_IN_NUM_WORDS_LEN 4
+
+/* MC_CMD_CSR_INST_READ32_OUT msgresponse */
+#define	MC_CMD_CSR_INST_READ32_OUT_LENMIN 4
+#define	MC_CMD_CSR_INST_READ32_OUT_LENMAX 252
+#define	MC_CMD_CSR_INST_READ32_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_CSR_INST_READ32_OUT_LEN(num) (4+4*(num))
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_NUM(len) (((len)-4)/4)
+/* Status response from register reads by firmware */
+#define	MC_CMD_CSR_INST_READ32_OUT_STATUS_OFST 0
+#define	MC_CMD_CSR_INST_READ32_OUT_STATUS_LEN 4
+/* Read data */
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_OFST 4
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_LEN 4
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_MINNUM 0
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_MAXNUM 62
+#define	MC_CMD_CSR_INST_READ32_OUT_BUFFER_MAXNUM_MCDI2 254
+
+
+/***********************************/
+/* MC_CMD_CSR_INST_WRITE32
+ * Write 32bit dwords to an MCPU indirect memory map specified by its
+ * MAP_INDEX.
+ */
+#define	MC_CMD_CSR_INST_WRITE32 0x1ef
+#define	MC_CMD_CSR_INST_WRITE32_MSGSET 0x1ef
+#undef	MC_CMD_0x1ef_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ef_PRIVILEGE_CTG SRIOV_CTG_INSECURE
+
+/* MC_CMD_CSR_INST_WRITE32_IN msgrequest */
+#define	MC_CMD_CSR_INST_WRITE32_IN_LENMIN 24
+#define	MC_CMD_CSR_INST_WRITE32_IN_LENMAX 252
+#define	MC_CMD_CSR_INST_WRITE32_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_CSR_INST_WRITE32_IN_LEN(num) (20+4*(num))
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_NUM(len) (((len)-20)/4)
+/* Address */
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_OFST 0
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LEN 8
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_OFST 0
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_LEN 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_LBN 0
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_LO_WIDTH 32
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_OFST 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_LEN 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_LBN 32
+#define	MC_CMD_CSR_INST_WRITE32_IN_ADDR_HI_WIDTH 32
+/* Step value between register addresses */
+#define	MC_CMD_CSR_INST_WRITE32_IN_STEP_OFST 8
+#define	MC_CMD_CSR_INST_WRITE32_IN_STEP_LEN 4
+/* Map index of indirect memory map */
+#define	MC_CMD_CSR_INST_WRITE32_IN_MAP_INDEX_OFST 12
+#define	MC_CMD_CSR_INST_WRITE32_IN_MAP_INDEX_LEN 4
+/* Write data */
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_OFST 20
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_LEN 4
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_MINNUM 1
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_MAXNUM 58
+#define	MC_CMD_CSR_INST_WRITE32_IN_BUFFER_MAXNUM_MCDI2 250
+
+/* MC_CMD_CSR_INST_WRITE32_OUT msgresponse */
+#define	MC_CMD_CSR_INST_WRITE32_OUT_LEN 4
+/* Status response from register writes by firmware */
+#define	MC_CMD_CSR_INST_WRITE32_OUT_STATUS_OFST 0
+#define	MC_CMD_CSR_INST_WRITE32_OUT_STATUS_LEN 4
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_CONFIG
+ * Query the static HNIC port configuration for a physical port. Returns ENODEV
+ * if the target does not correspond to a physical port, or EPERM if the caller
+ * does not have permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG 0x1f0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_MSGSET 0x1f0
+#undef	MC_CMD_0x1f0_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_CONFIG_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LENMIN 12
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LENMAX 252
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_LEN(num) (12+4*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_NUM(len) (((len)-12)/4)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_REGION_SIZE_LEN 4
+/* Allocation granularity, in bytes. All partitioning of the buffer region must
+ * be in multiples of this value.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_ALLOC_GRANULARITY_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_NUM_FIFOS_LEN 4
+/* Array of FIFO handles, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_OFST 12
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MINNUM 0
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM 60
+#define	MC_CMD_FETCH_HNIC_PORT_CONFIG_OUT_FIFO_HANDLE_MAXNUM_MCDI2 252
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING
+ * Returns the current state of the FIFO sizing configuration for all of the
+ * FIFOs assigned to a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING 0x1f1
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_MSGSET 0x1f1
+#undef	MC_CMD_0x1f1_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LENMIN 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LENMAX 248
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_LEN(num) (8+12*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_NUM(len) (((len)-8)/12)
+/* Total size of buffer region assigned to this port, in bytes. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_REGION_SIZE_LEN 4
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM 20
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_SIZING_OUT_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 84
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING
+ * Sets the FIFO sizing configuration for a physical port. This is disruptive
+ * to port operation and will cause the link to drop while the port is
+ * reconfigured. Returns ENODEV if the target does not correspond to a physical
+ * port, or EPERM if the caller does not have permission to administer it, or
+ * EINVAL if the sizing parameters are invalid.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING 0x1f2
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_MSGSET 0x1f2
+#undef	MC_CMD_0x1f2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LENMIN 12
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LENMAX 252
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_LEN(num) (12+12*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_NUM(len) (((len)-12)/12)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current size configuration.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_SIZE_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_OFST 12
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_LEN 12
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MINNUM 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM 20
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_IN_FIFO_SIZE_PARAMS_MAXNUM_MCDI2 84
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_SIZING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING
+ * Returns the current state of the 802.1Q priority to FIFO mapping
+ * configuration for a physical port. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING 0x1f3
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1f3
+#undef	MC_CMD_0x1f3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_LEN 32
+/* FIFO handle for each Priority Code Point(PCP), in order from 0 to 7. */
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_PRIO_MAPPING_OUT_FIFO_HANDLE_NUM 8
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING
+ * Sets the PCP priority to FIFO mapping configuration for a physical port.
+ * Returns ENODEV if the target does not correspond to a physical port, or
+ * EPERM if the caller does not have permission to administer it, or EINVAL if
+ * any of the FIFO handles are invalid in some way.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING 0x1f4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_MSGSET 0x1f4
+#undef	MC_CMD_0x1f4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_LEN 40
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* FIFO handle for each PCP value, in order from 0 to 7. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_LEN 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_IN_FIFO_HANDLE_NUM 8
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_PRIO_MAPPING_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Returns the current state of the FIFO delay parameters configuration for all
+ * of the FIFOs assigned to a physical port. Returns ENODEV if the target does
+ * not correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS 0x1f5
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1f5
+#undef	MC_CMD_0x1f5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMIN 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX 244
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LENMAX_MCDI2 1012
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN(num) (4+16*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_NUM(len) (((len)-4)/16)
+/* The number of independent FIFOs assigned to this port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM 15
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 63
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS
+ * Sets the FIFO delay parameters configuration for a physical port. This is
+ * not disruptive to port operation. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it, or EINVAL if the sizing parameters are invalid.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS 0x1f6
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_MSGSET 0x1f6
+#undef	MC_CMD_0x1f6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMIN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX 240
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LENMAX_MCDI2 1008
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_LEN(num) (16+16*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_NUM(len) (((len)-16)/16)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. FIFOs assigned to the port but not
+ * included in the list are assumed to retain their current delay
+ * configuration.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DELAY_PARAMS structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_LEN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MINNUM 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM 14
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_IN_FIFO_DELAY_PARAMS_MAXNUM_MCDI2 62
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DELAY_PARAMS_OUT_LEN 0
+
+/* HNIC_FIFO_DRAIN structuredef: HNIC FIFO drain parameters */
+#define	HNIC_FIFO_DRAIN_LEN 8
+/* Handle to identify the fifo to be drained. The FIFO_HANDLE should be treated
+ * as an opaque value.
+ */
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_DRAIN_FIFO_HANDLE_WIDTH 32
+#define	HNIC_FIFO_DRAIN_FLAGS_OFST 4
+#define	HNIC_FIFO_DRAIN_FLAGS_LEN 4
+#define	HNIC_FIFO_DRAIN_DRAIN_EN_OFST 4
+#define	HNIC_FIFO_DRAIN_DRAIN_EN_LBN 0
+#define	HNIC_FIFO_DRAIN_DRAIN_EN_WIDTH 1
+#define	HNIC_FIFO_DRAIN_FLAGS_LBN 32
+#define	HNIC_FIFO_DRAIN_FLAGS_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN
+ * This command configures an HNIC TX FIFO to be flushed for a physical port.
+ * This is not disruptive to port operation. Returns ENODEV if the target does
+ * not correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it. or ENOTSUP if the requested direction is RX.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN 0x1f7
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_MSGSET 0x1f7
+#undef	MC_CMD_0x1f7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LENMIN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LENMAX 240
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LENMAX_MCDI2 1008
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_LEN(num) (16+16*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_NUM(len) (((len)-16)/16)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to query. Flushing fifos is only allowed in the TX
+ * direction.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured for flushing. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_DRAIN structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_LEN 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_MINNUM 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_MAXNUM 14
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_IN_FIFO_DRAIN_MAXNUM_MCDI2 62
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_DRAIN_OUT_LEN 0
+
+/* HNIC_FIFO_WEIGHT structuredef: HNIC FIFO weights used in the scheduler's
+ * round robin algorithm.
+ */
+#define	HNIC_FIFO_WEIGHT_LEN 8
+/* FIFO handle */
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_OFST 0
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_LEN 4
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_LBN 0
+#define	HNIC_FIFO_WEIGHT_FIFO_HANDLE_WIDTH 32
+/* Weight value expressed in units of 0.001 (i.e. value 1000 corresponds to a
+ * weight=1). Allowed values for this field are [1000-4000]
+ */
+#define	HNIC_FIFO_WEIGHT_WEIGHT_OFST 4
+#define	HNIC_FIFO_WEIGHT_WEIGHT_LEN 4
+#define	HNIC_FIFO_WEIGHT_WEIGHT_LBN 32
+#define	HNIC_FIFO_WEIGHT_WEIGHT_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS
+ * Retrieves the FIFO weights for the scheduler's round robin algorithm.
+ * Returns ENODEV if the target does not correspond to a physical port, or
+ * EPERM if the caller does not have permission to administer it.
+ */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS 0x1f8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_MSGSET 0x1f8
+#undef	MC_CMD_0x1f8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN msgrequest */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_LEN 8
+/* Port handle to the target network port. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to operate on. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_OFST 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+
+/* MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT msgresponse */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LENMIN 16
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LENMAX 248
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_LEN(num) (8+8*(num))
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_NUM(len) (((len)-8)/8)
+/* Total number of configured FIFOs. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_NUM_FIFOS_OFST 0
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_WEIGHT structures, NUM_FIFOS items long. */
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LEN 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_OFST 8
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_LBN 64
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_LO_WIDTH 32
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_OFST 12
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_LEN 4
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_LBN 96
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_HI_WIDTH 32
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_MINNUM 1
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_MAXNUM 30
+#define	MC_CMD_FETCH_HNIC_PORT_FIFO_WEIGHTS_OUT_FIFO_WEIGHTS_MAXNUM_MCDI2 126
+
+
+/***********************************/
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS
+ * Configures the FIFO weights for the scheduler's round robin algorithm. This
+ * is not disruptive to port operation. Returns ENODEV if the target does not
+ * correspond to a physical port, or EPERM if the caller does not have
+ * permission to administer it or EINVAL if provided argument are not valid.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS 0x1f9
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_MSGSET 0x1f9
+#undef	MC_CMD_0x1f9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1f9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN msgrequest */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LENMIN 24
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LENMAX 248
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LENMAX_MCDI2 1016
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_LEN(num) (16+8*(num))
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_NUM(len) (((len)-16)/8)
+/* Port handle to the target network port. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_PORT_HANDLE_LEN 4
+/* Traffic direction to operate on. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_OFST 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_DIRECTION_LEN 4
+/*            Enum values, see field(s): */
+/*               PORT_DIRECTION */
+/* The number of FIFOs being configured. At least one FIFO needs to be
+ * specified.
+ */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_NUM_FIFOS_OFST 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_NUM_FIFOS_LEN 4
+/* Array of HNIC_FIFO_WEIGHT structures, NUM_FIFOS items long. */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LEN 8
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_OFST 16
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_LEN 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_LBN 128
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_LO_WIDTH 32
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_OFST 20
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_LEN 4
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_LBN 160
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_HI_WIDTH 32
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_MINNUM 1
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_MAXNUM 29
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_IN_FIFO_WEIGHTS_MAXNUM_MCDI2 125
+
+/* MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_OUT msgresponse */
+#define	MC_CMD_CONFIGURE_HNIC_PORT_FIFO_WEIGHTS_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_NETPORT_STATISTICS
+ * Get generic MAC statistics. This call retrieves unified statistics managed
+ * by the MC. The MC will populate and provide all supported statistics in the
+ * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the
+ * aforementioned command for the format and contents of the stats DMA buffer.
+ * To ensure consistent and accurate results, it is essential for the driver to
+ * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
+ * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
+ * handle, and EINVAL on invalid parameters (DMA buffer too small)
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS 0x1fa
+#define	MC_CMD_GET_NETPORT_STATISTICS_MSGSET 0x1fa
+#undef	MC_CMD_0x1fa_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1fa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_NETPORT_STATISTICS_IN msgrequest */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_LEN 20
+/* Handle of port to get MAC statistics for. */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_OFST 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_LEN 4
+/* Contains options for querying the MAC statistics. */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LBN 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_LBN 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_LBN 2
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_LBN 3
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_LBN 15
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_WIDTH 17
+/* Specifies the physical address of the DMA buffer to use for statistics
+ * transfer. This field must contain a valid address under either of these
+ * conditions: 1. DMA flag is set (immediate DMA requested) 2. Both
+ * PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured)
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_OFST 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LEN 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_OFST 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LBN 64
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_OFST 12
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LBN 96
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32
+/* Specifies the length of the DMA buffer in bytes for statistics transfer. The
+ * buffer size must be at least DMA_BUFFER_SIZE bytes (as returned by
+ * MC_CMD_MAC_STATISTICS_DESCRIPTOR). Providing an insufficient buffer size
+ * will result in an EINVAL error. This field must contain a valid length under
+ * either of these conditions: 1. DMA flag is set (immediate DMA requested) 2.
+ * Both PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured)
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_OFST 16
+#define	MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_LEN 4
+
+/* MC_CMD_GET_NETPORT_STATISTICS_OUT msgresponse */
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX 248
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX_MCDI2 1016
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_LEN(num) (0+8*(num))
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_NUM(len) (((len)-0)/8)
+/* Statistics buffer. Zero-length if DMA mode is used. The statistics buffer is
+ * an array of 8-byte counter values, containing the generation start marker,
+ * stats counters, and generation end marker. The index of each counter in the
+ * array is reported by the MAC_STATISTICS_DESCRIPTOR command. The same layout
+ * is used for the DMA buffer for DMA mode stats.
+ */
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_OFST 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LEN 8
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_OFST 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LBN 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_WIDTH 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_OFST 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LEN 4
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LBN 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_WIDTH 32
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MINNUM 0
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM 31
+#define	MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM_MCDI2 127
+
 /* EVB_PORT_ID structuredef */
 #define	EVB_PORT_ID_LEN 4
 #define	EVB_PORT_ID_PORT_ID_OFST 0
@@ -11820,6 +15458,9 @@
 #define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
@@ -11926,6 +15567,9 @@
 #define	MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
@@ -12061,6 +15705,9 @@
 #define	MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
@@ -12209,6 +15856,9 @@
 #define	MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16
 #define	MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
 #define	MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
+#define	MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
+#define	MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
 /* Owner ID to use if in buffer mode (zero if physical) */
 #define	MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
 #define	MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
@@ -13828,6 +17478,10 @@
 #define	MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
 /* enum: read the supported encapsulation types for the VNIC */
 #define	MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
+/* enum: read the supported RX filter matches for low-latency queues (as
+ * allocated by MC_CMD_ALLOC_LL_QUEUES)
+ */
+#define	MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_LL_RX_MATCHES 0x7
 
 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
 #define	MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
@@ -14554,7 +18208,7 @@
 
 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
-/* VI number to get information for. */
+/* Queue handle, encodes queue type and VI number to get information for. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
 #define	MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
 
@@ -14569,6 +18223,12 @@
 /* Use Relaxed ordering model for TLPs on this VI. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
+/* Use Relaxed ordering model for packet data transfer TLPs on this VI (alias
+ * of RELAXED_ORDERING for hardware that also understands the
+ * RELAXED_ORDERING_SYNC_DATA field and allows them to be used independently).
+ */
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_PACKET_DATA_LBN 16
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
 /* Use ID based ordering for TLPs on this VI. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
@@ -14578,15 +18238,56 @@
 /* Enable TPH for TLPs on this VI. */
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
+/* Use Relaxed ordering model for synchronization data transfer TLPs on this
+ * VI, used for relaxed ordering of metadata transfers on LL.
+ */
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_SYNC_DATA_LBN 20
+#define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
 #define	MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
 
+/* MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT msgresponse: This message has the same
+ * layout as GET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to
+ * simplify use in drivers
+ */
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_LEN 4
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_LEN 4
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_LBN 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_WIDTH 8
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_LBN 8
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_WIDTH 8
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_LBN 16
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_LBN 16
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_LBN 17
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_LBN 18
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_LBN 19
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_WIDTH 1
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_OFST 0
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_LBN 20
+#define	MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
+
 
 /***********************************/
 /* MC_CMD_SET_VI_TLP_PROCESSING
  * Set TLP steering and ordering information for a VI. The caller must have the
  * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
- * an ancestor of the current user (see MC_CMD_SET_VI_USER).
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER). Note that LL
+ * queues require this to be called after allocation but before initialisation
+ * of the queue. TLP options of a queue are fixed after queue is initialised,
+ * with the values set to current global value or they can be overriden using
+ * this command. At LL queue allocation, all overrides are cleared.
  */
 #define	MC_CMD_SET_VI_TLP_PROCESSING 0xb1
 #define	MC_CMD_SET_VI_TLP_PROCESSING_MSGSET 0xb1
@@ -14596,7 +18297,7 @@
 
 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
-/* VI number to set information for. */
+/* Queue handle, encodes queue type and VI number to set information for. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
 /* Transaction processing steering hint 1 for use with the Rx Queue. */
@@ -14608,6 +18309,12 @@
 /* Use Relaxed ordering model for TLPs on this VI. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
+/* Use Relaxed ordering model for packet data transfer TLPs on this VI (alias
+ * of RELAXED_ORDERING for hardware that also understands the
+ * RELAXED_ORDERING_SYNC_DATA field and allows them to be used independently).
+ */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_PACKET_DATA_LBN 48
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
 /* Use ID based ordering for TLPs on this VI. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
@@ -14617,9 +18324,49 @@
 /* Enable TPH for TLPs on this VI. */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
+/* Use Relaxed ordering model for synchronization data transfer TLPs on this
+ * VI, used for relaxed ordering of metadata transfers on LL.
+ */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_SYNC_DATA_LBN 52
+#define	MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
 #define	MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
 
+/* MC_CMD_SET_VI_TLP_PROCESSING_V2_IN msgrequest: This message has the same
+ * layout as SET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to
+ * simplify use in drivers.
+ */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_LEN 8
+/* Queue handle, encodes queue type and VI number to set information for. */
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_OFST 0
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_LEN 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_LEN 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_LBN 0
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_WIDTH 8
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_LBN 8
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_WIDTH 8
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_LBN 16
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_LBN 16
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_LBN 17
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_LBN 18
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_LBN 19
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_WIDTH 1
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_OFST 4
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_LBN 20
+#define	MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
+
 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
 #define	MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
 
@@ -14640,12 +18387,16 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
 /* enum: MISC. */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
-/* enum: IDO. */
+/* enum: ID-based Ordering (IDO). */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
-/* enum: RO. */
+/* enum: Relaxed Ordering (RO), excluding LL queues. */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
-/* enum: TPH Type. */
+/* enum: TLP Processing Hint (TPH) Type (excluding LL queues). */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
+/* enum: Relaxed Ordering (RO) of LL queues. */
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LL_RO 0x4
+/* enum: TPH Type of LL queues. */
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LL_TPH_TYPE 0x5
 
 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
@@ -14659,9 +18410,6 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
@@ -14674,9 +18422,6 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
@@ -14686,9 +18431,6 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
@@ -14704,9 +18446,18 @@
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
 #define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
-#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_RXDMA_EN_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_RXDMA_EN_LBN 0
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_RXDMA_EN_WIDTH 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_PACKET_RXDMA_EN_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_PACKET_RXDMA_EN_LBN 0
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_PACKET_RXDMA_EN_WIDTH 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_META_RXDMA_EN_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_META_RXDMA_EN_LBN 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_RO_META_RXDMA_EN_WIDTH 1
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_TPH_TYPE_RX_OFST 4
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_TPH_TYPE_RX_LBN 0
+#define	MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_LL_TPH_TYPE_RX_WIDTH 2
 
 
 /***********************************/
@@ -14767,9 +18518,18 @@
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
-#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
-#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
-#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_RXDMA_EN_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_RXDMA_EN_LBN 0
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_RXDMA_EN_WIDTH 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_PACKET_RXDMA_EN_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_PACKET_RXDMA_EN_LBN 0
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_PACKET_RXDMA_EN_WIDTH 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_META_RXDMA_EN_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_META_RXDMA_EN_LBN 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_RO_META_RXDMA_EN_WIDTH 1
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_TPH_TYPE_RX_OFST 4
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_TPH_TYPE_RX_LBN 0
+#define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_LL_TPH_TYPE_RX_WIDTH 2
 
 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
 #define	MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
@@ -15557,7 +19317,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -15967,7 +19730,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -16402,7 +20168,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -16845,7 +20614,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -17293,7 +21065,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -17752,7 +21527,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -17872,6 +21650,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 
 /* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
@@ -18262,7 +22046,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -18382,6 +22169,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 /* These bits are reserved for communicating test-specific capabilities to
  * host-side test software. All production drivers should treat this field as
  * opaque.
@@ -18786,7 +22579,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -18906,6 +22702,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 /* These bits are reserved for communicating test-specific capabilities to
  * host-side test software. All production drivers should treat this field as
  * opaque.
@@ -19345,7 +23147,10 @@
 /*               MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
 /* enum: PF does not exist. */
 /*               MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
-/* Number of VIs available for each external port */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 58
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 2
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
@@ -19465,6 +23270,12 @@
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_OFST 148
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_LBN 15
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_WIDTH 1
 /* These bits are reserved for communicating test-specific capabilities to
  * host-side test software. All production drivers should treat this field as
  * opaque.
@@ -19529,6 +23340,1182 @@
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
 #define	MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
 
+/* MC_CMD_GET_CAPABILITIES_V11_OUT msgresponse */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LEN 196
+/* First word of flags. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_WIDTH 1
+/* RxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_OFST 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_LEN 2
+/* enum: Standard RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP 0x0
+/* enum: Low latency RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_LOW_LATENCY 0x1
+/* enum: Packed stream RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_PACKED_STREAM 0x2
+/* enum: Rules engine RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_RULES_ENGINE 0x5
+/* enum: DPDK RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_DPDK 0x6
+/* enum: BIST RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_BIST 0x10a
+/* enum: RXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
+/* enum: RXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
+/* enum: RXDP Test firmware image 3 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
+/* enum: RXDP Test firmware image 4 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
+/* enum: RXDP Test firmware image 5 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_BACKPRESSURE 0x105
+/* enum: RXDP Test firmware image 6 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
+/* enum: RXDP Test firmware image 7 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
+/* enum: RXDP Test firmware image 8 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
+/* enum: RXDP Test firmware image 9 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
+/* enum: RXDP Test firmware image 10 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_SLOW 0x10c
+/* TxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_OFST 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_LEN 2
+/* enum: Standard TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP 0x0
+/* enum: Low latency TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_LOW_LATENCY 0x1
+/* enum: High packet rate TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_HIGH_PACKET_RATE 0x3
+/* enum: Rules engine TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_RULES_ENGINE 0x5
+/* enum: DPDK TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_DPDK 0x6
+/* enum: BIST TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_BIST 0x12d
+/* enum: TXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
+/* enum: TXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
+/* enum: TXDP CSR bus test firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_CSR 0x103
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+/* enum: Low latency RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
+/* enum: Packed stream RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
+ * encapsulations (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* Hardware capabilities of NIC */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_OFST 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_LEN 4
+/* Licensed capabilities */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_OFST 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_LEN 4
+/* Second word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
+/* One byte per PF containing the number of the external port assigned to this
+ * PF, indexed by PF number. Special values indicate that a PF is either not
+ * present or not assigned.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff
+/* enum: PF does not exist. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe
+/* enum: PF does exist but is not assigned to any external port. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_ASSIGNED 0xfd
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
+ * in this field. It is intended for a possible future situation where a more
+ * complex scheme of PFs to ports mapping is being used. The future driver
+ * should look for a new field supporting the new scheme. The current/old
+ * driver should treat this value as PF_NOT_ASSIGNED.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
+ * special value indicates that a PF is not present.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_OFST 42
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+/*               MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff */
+/* enum: PF does not exist. */
+/*               MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_OFST 58
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_NUM 4
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_OFST 66
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_LEN 1
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_OFST 67
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_LEN 1
+/* Total number of available PIO buffers */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_OFST 68
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_LEN 2
+/* Size of a single PIO buffer */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_OFST 70
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_LEN 2
+/* On chips later than Medford the amount of address space assigned to each VI
+ * is configurable. This is a global setting that the driver must query to
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
+ * with 8k VI windows.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_OFST 72
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_LEN 1
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
+ * CTPIO is not mapped.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_8K 0x0
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_16K 0x1
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_64K 0x2
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
+/* Entry count in the MAC stats array, including the final GENERATION_END
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
+ * hold at least this many 64-bit stats values, if they wish to receive all
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
+ * stats array returned will be truncated.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_OFST 76
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_LEN 2
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_OFST 80
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_LEN 4
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
+ * they create an RX queue. Due to hardware limitations, only a small number of
+ * different buffer sizes may be available concurrently. Nonzero entries in
+ * this array are the sizes of buffers which the system guarantees will be
+ * available for use. If the list is empty, there are no limitations on
+ * concurrent buffer sizes.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
+/* Third word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_WIDTH 1
+/* These bits are reserved for communicating test-specific capabilities to
+ * host-side test software. All production drivers should treat this field as
+ * opaque.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LEN 8
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LBN 1216
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_WIDTH 32
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_OFST 156
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LBN 1248
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_WIDTH 32
+/* The minimum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum number of queues that can be used by an RSS context in exclusive
+ * mode. In exclusive mode the context has a configurable indirection table and
+ * a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
+/* The maximum number of queues that can be used by an RSS context in even-
+ * spreading mode. In even-spreading mode the context has no indirection table
+ * but it does have a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
+/* The total number of RSS contexts supported. Note that the number of
+ * available contexts using indirection tables is also limited by the
+ * availability of indirection table space allocated from a common pool.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_OFST 176
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_LEN 4
+/* The total amount of indirection table space that can be shared between RSS
+ * contexts.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_OFST 180
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_LEN 4
+/* A bitmap of the queue sizes the device can provide, where bit N being set
+ * indicates that 2**N is a valid size. The device may be limited in the number
+ * of different queue sizes that can exist simultaneously, so a bit being set
+ * here does not guarantee that an attempt to create a queue of that size will
+ * succeed.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
+/* A bitmap of queue sizes that are always available, in the same format as
+ * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
+ * will never fail due to unavailability of the requested size.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
+/* Number of available indirect memory maps. */
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192
+#define	MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
+
+/* MC_CMD_GET_CAPABILITIES_V12_OUT msgresponse */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LEN 204
+/* First word of flags. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_OFST 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_WIDTH 1
+/* RxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_OFST 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_LEN 2
+/* enum: Standard RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP 0x0
+/* enum: Low latency RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_LOW_LATENCY 0x1
+/* enum: Packed stream RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_PACKED_STREAM 0x2
+/* enum: Rules engine RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_RULES_ENGINE 0x5
+/* enum: DPDK RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_DPDK 0x6
+/* enum: BIST RXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_BIST 0x10a
+/* enum: RXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
+/* enum: RXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
+/* enum: RXDP Test firmware image 3 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
+/* enum: RXDP Test firmware image 4 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
+/* enum: RXDP Test firmware image 5 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_BACKPRESSURE 0x105
+/* enum: RXDP Test firmware image 6 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
+/* enum: RXDP Test firmware image 7 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
+/* enum: RXDP Test firmware image 8 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
+/* enum: RXDP Test firmware image 9 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
+/* enum: RXDP Test firmware image 10 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_SLOW 0x10c
+/* TxDPCPU firmware id. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_OFST 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_LEN 2
+/* enum: Standard TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP 0x0
+/* enum: Low latency TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_LOW_LATENCY 0x1
+/* enum: High packet rate TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_HIGH_PACKET_RATE 0x3
+/* enum: Rules engine TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_RULES_ENGINE 0x5
+/* enum: DPDK TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_DPDK 0x6
+/* enum: BIST TXDP firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_BIST 0x12d
+/* enum: TXDP Test firmware image 1 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
+/* enum: TXDP Test firmware image 2 */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
+/* enum: TXDP CSR bus test firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_CSR 0x103
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_OFST 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+/* enum: Low latency RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
+/* enum: Packed stream RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK RX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
+ * encapsulations (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_WIDTH 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_OFST 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK TX PD production firmware */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* Hardware capabilities of NIC */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_OFST 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_LEN 4
+/* Licensed capabilities */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_OFST 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_LEN 4
+/* Second word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_LBN 19
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_LBN 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_LBN 22
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_LBN 24
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_LBN 25
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_LBN 28
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_LBN 29
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_LBN 30
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
+/* One byte per PF containing the number of the external port assigned to this
+ * PF, indexed by PF number. Special values indicate that a PF is either not
+ * present or not assigned.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff
+/* enum: PF does not exist. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe
+/* enum: PF does exist but is not assigned to any external port. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_ASSIGNED 0xfd
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
+ * in this field. It is intended for a possible future situation where a more
+ * complex scheme of PFs to ports mapping is being used. The future driver
+ * should look for a new field supporting the new scheme. The current/old
+ * driver should treat this value as PF_NOT_ASSIGNED.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
+ * special value indicates that a PF is not present.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_OFST 42
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_LEN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+/*               MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff */
+/* enum: PF does not exist. */
+/*               MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe */
+/* Number of VIs available for external ports 0-3. For devices with more than
+ * four ports, the remainder are in NUM_VIS_PER_PORT2 in
+ * GET_CAPABILITIES_V12_OUT.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_OFST 58
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_NUM 4
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_OFST 66
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_LEN 1
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_OFST 67
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_LEN 1
+/* Total number of available PIO buffers */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_OFST 68
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_LEN 2
+/* Size of a single PIO buffer */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_OFST 70
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_LEN 2
+/* On chips later than Medford the amount of address space assigned to each VI
+ * is configurable. This is a global setting that the driver must query to
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
+ * with 8k VI windows.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_OFST 72
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_LEN 1
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
+ * CTPIO is not mapped.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_8K 0x0
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_16K 0x1
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_64K 0x2
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
+/* Entry count in the MAC stats array, including the final GENERATION_END
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
+ * hold at least this many 64-bit stats values, if they wish to receive all
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
+ * stats array returned will be truncated.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_OFST 76
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_LEN 2
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_OFST 80
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_LEN 4
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
+ * they create an RX queue. Due to hardware limitations, only a small number of
+ * different buffer sizes may be available concurrently. Nonzero entries in
+ * this array are the sizes of buffers which the system guarantees will be
+ * available for use. If the list is empty, there are no limitations on
+ * concurrent buffer sizes.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
+/* Third word of flags. Not present on older firmware (check the length). */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_LBN 0
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_LBN 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_LBN 3
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_LBN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_LBN 15
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_LBN 17
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_WIDTH 1
+/* These bits are reserved for communicating test-specific capabilities to
+ * host-side test software. All production drivers should treat this field as
+ * opaque.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LEN 8
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_OFST 152
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LBN 1216
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_WIDTH 32
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_OFST 156
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LEN 4
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LBN 1248
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_WIDTH 32
+/* The minimum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum size (in table entries) of indirection table to be allocated
+ * from the pool for an RSS context. Note that the table size used must be a
+ * power of 2.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
+/* The maximum number of queues that can be used by an RSS context in exclusive
+ * mode. In exclusive mode the context has a configurable indirection table and
+ * a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
+/* The maximum number of queues that can be used by an RSS context in even-
+ * spreading mode. In even-spreading mode the context has no indirection table
+ * but it does have a configurable RSS key.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
+/* The total number of RSS contexts supported. Note that the number of
+ * available contexts using indirection tables is also limited by the
+ * availability of indirection table space allocated from a common pool.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_OFST 176
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_LEN 4
+/* The total amount of indirection table space that can be shared between RSS
+ * contexts.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_OFST 180
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_LEN 4
+/* A bitmap of the queue sizes the device can provide, where bit N being set
+ * indicates that 2**N is a valid size. The device may be limited in the number
+ * of different queue sizes that can exist simultaneously, so a bit being set
+ * here does not guarantee that an attempt to create a queue of that size will
+ * succeed.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
+/* A bitmap of queue sizes that are always available, in the same format as
+ * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
+ * will never fail due to unavailability of the requested size.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
+/* Number of available indirect memory maps. */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
+/* Number of VIs available for external ports 4-7. Information for ports 0-3 is
+ * in NUM_VIS_PER_PORT in GET_CAPABILITIES_V2_OUT.
+ */
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_OFST 196
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_LEN 2
+#define	MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_NUM 4
+
 
 /***********************************/
 /* MC_CMD_V2_EXTN
@@ -30722,7 +35709,8 @@
  * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
  * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
  * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
- * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
+ * VF on the calling interface - INTF=..., PF=PF_NULL, VF=VF_NULL to refer to
+ * the named interface itself - INTF=..., PF=..., VF=VF_NULL to refer to a PF
  * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
  * interface where ... refers to a small integer for the VF/PF fields, and to
  * values from the PCIE_INTERFACE enum for for the INTF field. It's only
@@ -33920,6 +38908,633 @@
 #define	MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
 #define	MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
 
+
+/***********************************/
+/* MC_CMD_PR_OPEN
+ * Open a session to manage a programmable region. Session handles can be
+ * explicitly closed with MC_CMD_PR_CLOSE, or implicitly via
+ * MC_CMD_ENTITY_RESET or a PCIe Function Level Reset. Although this command is
+ * available to all callers that are a member of the GENERAL privilege group,
+ * an additional privilege check may be performed against the target region.
+ * Returns ENODEV if the region doesn't exist; EPERM if the caller has
+ * insufficient privilege to open the region; EBUSY is the region is currently
+ * busy; ENOSPC if the caller has too many open programmable region sessions.
+ */
+#define	MC_CMD_PR_OPEN 0x1a2
+#define	MC_CMD_PR_OPEN_MSGSET 0x1a2
+#undef	MC_CMD_0x1a2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_OPEN_IN msgrequest */
+#define	MC_CMD_PR_OPEN_IN_LEN 4
+/* The programmable region to open. */
+#define	MC_CMD_PR_OPEN_IN_REGION_ID_OFST 0
+#define	MC_CMD_PR_OPEN_IN_REGION_ID_LEN 4
+
+/* MC_CMD_PR_OPEN_OUT msgresponse */
+#define	MC_CMD_PR_OPEN_OUT_LEN 4
+/* Session handle for operations on the contents of the programmable region.
+ * Handles should be considered opaque, although a value of 0xFFFFFFFF is
+ * guaranteed never to be a valid handle.
+ */
+#define	MC_CMD_PR_OPEN_OUT_HANDLE_OFST 0
+#define	MC_CMD_PR_OPEN_OUT_HANDLE_LEN 4
+/* enum: Invalid programmable region session handle */
+#define	MC_CMD_PR_OPEN_OUT_HANDLE_NULL 0xffffffff
+
+
+/***********************************/
+/* MC_CMD_PR_CLOSE
+ * Close a session created with MC_CMD_PR_OPEN. Returns ENOENT if the session
+ * handle doesn't exist.
+ */
+#define	MC_CMD_PR_CLOSE 0x1a3
+#define	MC_CMD_PR_CLOSE_MSGSET 0x1a3
+#undef	MC_CMD_0x1a3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_CLOSE_IN msgrequest */
+#define	MC_CMD_PR_CLOSE_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CLOSE_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_CLOSE_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CLOSE_OUT msgresponse */
+#define	MC_CMD_PR_CLOSE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_TRANSFER_BEGIN
+ * Starts transfer of a XCLBIN to the target region associated with a session,
+ * setting the target region's data transfer offset to 0. Although this command
+ * is available to all callers that are a member of the GENERAL privilege group
+ * an extra privilege check may be performed against the target region in
+ * addition to the check performed by MC_CMD_PR_OPEN. Returns ENOENT if the
+ * session handle doesn't exist; EPERM if the caller has insufficient privilege
+ * to update the target region; EBUSY if the target region is currently busy;
+ * ESTALE if the target region has been updated since the session was opened.
+ * The caller should close this handle and open a new session to retry its
+ * transfer; EINVAL if length is too small, e.g. smaller than the AXLF/XCLBIN2
+ * header; ENOMEM if length too large, e.g. larger than the resources available
+ * to buffer the transfer.
+ */
+#define	MC_CMD_PR_TRANSFER_BEGIN 0x1a4
+#define	MC_CMD_PR_TRANSFER_BEGIN_MSGSET 0x1a4
+#undef	MC_CMD_0x1a4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_TRANSFER_BEGIN_IN msgrequest */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LEN 16
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_HANDLE_LEN 4
+/* Reserved, must be zero. */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_RESERVED_OFST 4
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_RESERVED_LEN 4
+/* The length (in bytes) of the XCLBIN data to be transferred. */
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_OFST 8
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LEN 8
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_OFST 8
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_LEN 4
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_LBN 64
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_LO_WIDTH 32
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_OFST 12
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_LEN 4
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_LBN 96
+#define	MC_CMD_PR_TRANSFER_BEGIN_IN_LENGTH_HI_WIDTH 32
+
+/* MC_CMD_PR_TRANSFER_BEGIN_OUT msgresponse */
+#define	MC_CMD_PR_TRANSFER_BEGIN_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_TRANSFER_WRITE
+ * Transfer a chunk of a XCLBIN data to the target region of a session,
+ * advancing the current data transfer offset. Chunks are transferred in a
+ * streaming like way and it is the responsibility of the caller to ensure all
+ * chunks are transferred in order and with no duplicates. Requires a transfer
+ * to have been started with MC_CMD_PR_TRANSFER_BEGIN. Returns ENOENT if the
+ * session handle doesn't exist; EACCESS if the session does not have an in-
+ * progress transfer; ESTALE if session's transfer has been cancelled, e.g.
+ * another session has started a transfer; ERANGE if the chunk exceeds the
+ * total transfer length specified in MC_CMD_PR_TRANSFER_BEGIN_IN.
+ */
+#define	MC_CMD_PR_TRANSFER_WRITE 0x1a5
+#define	MC_CMD_PR_TRANSFER_WRITE_MSGSET 0x1a5
+#undef	MC_CMD_0x1a5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_TRANSFER_WRITE_IN msgrequest */
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LENMIN 5
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LENMAX 252
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_LEN(num) (4+1*(num))
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_NUM(len) (((len)-4)/1)
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_HANDLE_LEN 4
+/* Chunk of data to write */
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_OFST 4
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_LEN 1
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_MINNUM 1
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_MAXNUM 248
+#define	MC_CMD_PR_TRANSFER_WRITE_IN_DATA_MAXNUM_MCDI2 1016
+
+/* MC_CMD_PR_TRANSFER_WRITE_OUT msgresponse */
+#define	MC_CMD_PR_TRANSFER_WRITE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_TRANSFER_END
+ * End the transfer of a XCLBIN to the target region of a session. A success
+ * result indicates the firmware started the update process. If the XCLBIN data
+ * is accepted, and programming has started, all other sessions for the same
+ * target region will be marked stale. The caller can use MC_CMD_PR_STATUS_GET
+ * to determine the overall result of the update. Requires a transfer to have
+ * been started with MC_CMD_PR_TRANSFER_BEGIN. Returns ENOENT if the session
+ * handle doesn't exist; EACCESS if the session does not have an in-progress
+ * transfer; ESTALE if session's transfer has been cancelled, e.g. another
+ * session has started a transfer.
+ */
+#define	MC_CMD_PR_TRANSFER_END 0x1a6
+#define	MC_CMD_PR_TRANSFER_END_MSGSET 0x1a6
+#undef	MC_CMD_0x1a6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_TRANSFER_END_IN msgrequest */
+#define	MC_CMD_PR_TRANSFER_END_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_TRANSFER_END_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_TRANSFER_END_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_TRANSFER_END_OUT msgresponse */
+#define	MC_CMD_PR_TRANSFER_END_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_STATUS_GET
+ * Query the current update status of the target region of a session. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened.
+ */
+#define	MC_CMD_PR_STATUS_GET 0x1a7
+#define	MC_CMD_PR_STATUS_GET_MSGSET 0x1a7
+#undef	MC_CMD_0x1a7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_STATUS_GET_IN msgrequest */
+#define	MC_CMD_PR_STATUS_GET_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_STATUS_GET_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_STATUS_GET_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_STATUS_GET_OUT msgresponse */
+#define	MC_CMD_PR_STATUS_GET_OUT_LENMIN 9
+#define	MC_CMD_PR_STATUS_GET_OUT_LENMAX 252
+#define	MC_CMD_PR_STATUS_GET_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_PR_STATUS_GET_OUT_LEN(num) (8+1*(num))
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_NUM(len) (((len)-8)/1)
+/* The state of the last update attempt triggered by MC_CMD_PR_TRANSFER_END or
+ * last action triggered by MC_CMD_PR_CONTROL.
+ */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_OFST 0
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_LEN 4
+/* enum: Update in progress */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_PENDING 0x0
+/* enum: Update successful, or no update attempted since device boot */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_SUCCESS 0x1
+/* enum: Update failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_STATUS_ERROR 0x2
+/* Code providing more information about the state of the update process. */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_OFST 4
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_LEN 4
+/* enum: Operation successful */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_SUCCESS 0x0
+/* enum: xclbin package was not built for this platform */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_UUID_MISMATCH 0x1
+/* enum: Provided xclbin package contains no bitstream */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_NO_BITSTREAM 0x2
+/* enum: Provided xclbin package contains clock error */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_CLK_ERROR 0x3
+/* enum: Load attempt unexpectedly rejected - bitstream may be corrupt */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_BITSTREAM_ERROR 0x4
+/* enum: Clock programming failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_CLK_PROG_FAIL 0x5
+/* enum: Shell DDR failed to calibrate */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_DDR_CAL_FAIL 0x6
+/* enum: ICAP was unavailable before programming */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_ICAP_BUSY 0x7
+/* enum: ICAP failed to terminate programming */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_ICAP_FAIL 0x8
+/* enum: Clock scaling operation failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_CLK_SCALE_FAIL 0x9
+/* enum: Clock measurement operation failed */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_CLK_MON_FAIL 0xa
+/* enum: Firewall tripped */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_FIREWALL_TRIPPED 0xb
+/* enum: XCLBIN package parse error */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_XCLBIN_PARSER_FAIL 0xc
+/* enum: Extension metadata load error */
+#define	MC_CMD_PR_STATUS_GET_OUT_RESULT_METADATA_LOAD_ERROR 0xd
+/* Result description (NUL-terminated ASCII string) */
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_OFST 8
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_LEN 1
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_MINNUM 1
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_MAXNUM 244
+#define	MC_CMD_PR_STATUS_GET_OUT_DESCRIPTION_MAXNUM_MCDI2 1012
+
+
+/***********************************/
+/* MC_CMD_PR_CONTROL
+ * Control operations on programmable regions.
+ */
+#define	MC_CMD_PR_CONTROL 0x1ed
+#define	MC_CMD_PR_CONTROL_MSGSET 0x1ed
+#undef	MC_CMD_0x1ed_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ed_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_CONTROL_IN msgrequest */
+#define	MC_CMD_PR_CONTROL_IN_LEN 8
+/* Sub-command code */
+#define	MC_CMD_PR_CONTROL_IN_OP_OFST 0
+#define	MC_CMD_PR_CONTROL_IN_OP_LEN 4
+/* enum: Initiates the process of quiescing the logic within a programmable
+ * region in preparation for an update via an out-of-band mechanism. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened; EPERM if the
+ * caller has insufficient privilege to update the target region; EBUSY if the
+ * target region is currently busy and cannot be quieced (including if the
+ * region is being reinitialised); EALREADY if the target region is being
+ * quiesced or has already been quiesced. The progress of the quiesceing
+ * process can be checked with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET
+ * indicates that an error occurred during quiesceing them the programmable
+ * region is in an undefined state and the system must be reset. Once
+ * MC_CMD_PR_STATUS_GET indicates that the process has completed, a new image
+ * can be downloaded by the appropriate out-out-band mechanism.
+ */
+#define	MC_CMD_PR_CONTROL_IN_OP_QUIESCE 0x0
+/* enum: Reinitialise logic within a programmable region after an update via an
+ * out-of-band mechanism. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; EPERM if the caller has insufficient privilege to update
+ * the target region; EBUSY if the target region is currently being quiesced;
+ * EALREADY if the target region is currently being initialised or has already
+ * been initialised. The progress of the unquiesceing process can be checked
+ * with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET indicates that an error
+ * occurred during unquiesceing then the programmable region is still in a
+ * quiesced state. A new image can be downloaded via the appropriate out-of-
+ * band mechanism. Once MC_CMD_PR_STATUS_GET indicates that the process has
+ * completed, the logic within the programmable region is available for use.
+ */
+#define	MC_CMD_PR_CONTROL_IN_OP_UNQUIESCE 0x1
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CONTROL_IN_HANDLE_OFST 4
+#define	MC_CMD_PR_CONTROL_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CONTROL_OP_QUIESCE_IN msgrequest */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_LEN 8
+/* Sub-command code */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_OFST 0
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_LEN 4
+/* enum: Initiates the process of quiescing the logic within a programmable
+ * region in preparation for an update via an out-of-band mechanism. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened; EPERM if the
+ * caller has insufficient privilege to update the target region; EBUSY if the
+ * target region is currently busy and cannot be quieced (including if the
+ * region is being reinitialised); EALREADY if the target region is being
+ * quiesced or has already been quiesced. The progress of the quiesceing
+ * process can be checked with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET
+ * indicates that an error occurred during quiesceing them the programmable
+ * region is in an undefined state and the system must be reset. Once
+ * MC_CMD_PR_STATUS_GET indicates that the process has completed, a new image
+ * can be downloaded by the appropriate out-out-band mechanism.
+ */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_QUIESCE 0x0
+/* enum: Reinitialise logic within a programmable region after an update via an
+ * out-of-band mechanism. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; EPERM if the caller has insufficient privilege to update
+ * the target region; EBUSY if the target region is currently being quiesced;
+ * EALREADY if the target region is currently being initialised or has already
+ * been initialised. The progress of the unquiesceing process can be checked
+ * with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET indicates that an error
+ * occurred during unquiesceing then the programmable region is still in a
+ * quiesced state. A new image can be downloaded via the appropriate out-of-
+ * band mechanism. Once MC_CMD_PR_STATUS_GET indicates that the process has
+ * completed, the logic within the programmable region is available for use.
+ */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_OP_UNQUIESCE 0x1
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_HANDLE_OFST 4
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CONTROL_OP_QUIESCE_OUT msgresponse */
+#define	MC_CMD_PR_CONTROL_OP_QUIESCE_OUT_LEN 0
+
+/* MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN msgrequest */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_LEN 8
+/* Sub-command code */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_OFST 0
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_LEN 4
+/* enum: Initiates the process of quiescing the logic within a programmable
+ * region in preparation for an update via an out-of-band mechanism. Returns
+ * ENOENT if the session handle doesn't exist; ESTALE if the target region has
+ * been updated by another session since the session was opened; EPERM if the
+ * caller has insufficient privilege to update the target region; EBUSY if the
+ * target region is currently busy and cannot be quieced (including if the
+ * region is being reinitialised); EALREADY if the target region is being
+ * quiesced or has already been quiesced. The progress of the quiesceing
+ * process can be checked with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET
+ * indicates that an error occurred during quiesceing them the programmable
+ * region is in an undefined state and the system must be reset. Once
+ * MC_CMD_PR_STATUS_GET indicates that the process has completed, a new image
+ * can be downloaded by the appropriate out-out-band mechanism.
+ */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_QUIESCE 0x0
+/* enum: Reinitialise logic within a programmable region after an update via an
+ * out-of-band mechanism. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; EPERM if the caller has insufficient privilege to update
+ * the target region; EBUSY if the target region is currently being quiesced;
+ * EALREADY if the target region is currently being initialised or has already
+ * been initialised. The progress of the unquiesceing process can be checked
+ * with MC_CMD_PR_STATUS_GET. If MC_CMD_PR_STATUS_GET indicates that an error
+ * occurred during unquiesceing then the programmable region is still in a
+ * quiesced state. A new image can be downloaded via the appropriate out-of-
+ * band mechanism. Once MC_CMD_PR_STATUS_GET indicates that the process has
+ * completed, the logic within the programmable region is available for use.
+ */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_OP_UNQUIESCE 0x1
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_HANDLE_OFST 4
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_CONTROL_OP_UNQUIESCE_OUT msgresponse */
+#define	MC_CMD_PR_CONTROL_OP_UNQUIESCE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_PR_METADATA_INFO
+ * Query information (length and name) about the meta-data describing the
+ * active contents of the target region of a session. Returns ENOENT if the
+ * session handle doesn't exist; ESTALE if the target region has been updated
+ * by another session since the session was opened; ENODEV if the meta-data
+ * item doesn't exist.
+ */
+#define	MC_CMD_PR_METADATA_INFO 0x1a8
+#define	MC_CMD_PR_METADATA_INFO_MSGSET 0x1a8
+#undef	MC_CMD_0x1a8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_METADATA_INFO_IN msgrequest */
+#define	MC_CMD_PR_METADATA_INFO_IN_LEN 16
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_METADATA_INFO_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_METADATA_INFO_IN_HANDLE_LEN 4
+/* Item category */
+#define	MC_CMD_PR_METADATA_INFO_IN_CATEGORY_OFST 4
+#define	MC_CMD_PR_METADATA_INFO_IN_CATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_CATEGORY */
+/* Item sub-category */
+#define	MC_CMD_PR_METADATA_INFO_IN_SUBCATEGORY_OFST 8
+#define	MC_CMD_PR_METADATA_INFO_IN_SUBCATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_SUBCATEGORY */
+/* Item index */
+#define	MC_CMD_PR_METADATA_INFO_IN_INDEX_OFST 12
+#define	MC_CMD_PR_METADATA_INFO_IN_INDEX_LEN 4
+
+/* MC_CMD_PR_METADATA_INFO_OUT msgresponse */
+#define	MC_CMD_PR_METADATA_INFO_OUT_LEN 136
+/* Length (in bytes) of the meta-data item */
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_OFST 0
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LEN 8
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_OFST 0
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_LEN 4
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_LBN 0
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_LO_WIDTH 32
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_OFST 4
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_LEN 4
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_LBN 32
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_LENGTH_HI_WIDTH 32
+/* Meta-data item name (NUL-terminated ASCII string). For the SECTION category
+ * the name is AXLF section name (axlf_section_header::m_sectionName). The
+ * items of the categories (UUID, TIMESTAMP and SIGNATURE) are unnamed items
+ * and return an empty string (NAME[0] == '\0').
+ */
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_NAME_OFST 8
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_NAME_LEN 1
+#define	MC_CMD_PR_METADATA_INFO_OUT_ITEM_NAME_NUM 128
+
+
+/***********************************/
+/* MC_CMD_PR_METADATA_READ
+ * Read a chunk of the meta-data describing the active contents of the target
+ * region of a session. Returns ENOENT if the session handle doesn't exist;
+ * ESTALE if the target region has been updated by another session since the
+ * session was opened; ENODEV if the meta-data item doesn't exist; ERANGE if
+ * the offset is outside the valid range for the meta-data item, e.g. offset >=
+ * item_length.
+ */
+#define	MC_CMD_PR_METADATA_READ 0x1a9
+#define	MC_CMD_PR_METADATA_READ_MSGSET 0x1a9
+#undef	MC_CMD_0x1a9_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1a9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_METADATA_READ_IN msgrequest */
+#define	MC_CMD_PR_METADATA_READ_IN_LEN 26
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_METADATA_READ_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_METADATA_READ_IN_HANDLE_LEN 4
+/* Item category */
+#define	MC_CMD_PR_METADATA_READ_IN_CATEGORY_OFST 4
+#define	MC_CMD_PR_METADATA_READ_IN_CATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_CATEGORY */
+/* Item sub-category */
+#define	MC_CMD_PR_METADATA_READ_IN_SUBCATEGORY_OFST 8
+#define	MC_CMD_PR_METADATA_READ_IN_SUBCATEGORY_LEN 4
+/*            Enum values, see field(s): */
+/*               PR_METADATA_ITEM_SUBCATEGORY */
+/* Item index */
+#define	MC_CMD_PR_METADATA_READ_IN_INDEX_OFST 12
+#define	MC_CMD_PR_METADATA_READ_IN_INDEX_LEN 4
+/* Byte offset within meta-data chunk */
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_OFST 16
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LEN 8
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_OFST 16
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_LEN 4
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_LBN 128
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_LO_WIDTH 32
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_OFST 20
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_LEN 4
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_LBN 160
+#define	MC_CMD_PR_METADATA_READ_IN_OFFSET_HI_WIDTH 32
+/* Maximum length (in bytes) to read */
+#define	MC_CMD_PR_METADATA_READ_IN_MAX_LENGTH_OFST 24
+#define	MC_CMD_PR_METADATA_READ_IN_MAX_LENGTH_LEN 2
+
+/* MC_CMD_PR_METADATA_READ_OUT msgresponse */
+#define	MC_CMD_PR_METADATA_READ_OUT_LENMIN 1
+#define	MC_CMD_PR_METADATA_READ_OUT_LENMAX 252
+#define	MC_CMD_PR_METADATA_READ_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_PR_METADATA_READ_OUT_LEN(num) (0+1*(num))
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_NUM(len) (((len)-0)/1)
+/* Chunk of meta-data */
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_OFST 0
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_LEN 1
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_MINNUM 1
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_MAXNUM 252
+#define	MC_CMD_PR_METADATA_READ_OUT_DATA_MAXNUM_MCDI2 1020
+
+/* PR_FREQ_INFO structuredef: Information about a single programmable region
+ * clock
+ */
+#define	PR_FREQ_INFO_LEN 140
+/* Clock frequency (in Hz) */
+#define	PR_FREQ_INFO_FREQ_HZ_OFST 0
+#define	PR_FREQ_INFO_FREQ_HZ_LEN 8
+#define	PR_FREQ_INFO_FREQ_HZ_LO_OFST 0
+#define	PR_FREQ_INFO_FREQ_HZ_LO_LEN 4
+#define	PR_FREQ_INFO_FREQ_HZ_LO_LBN 0
+#define	PR_FREQ_INFO_FREQ_HZ_LO_WIDTH 32
+#define	PR_FREQ_INFO_FREQ_HZ_HI_OFST 4
+#define	PR_FREQ_INFO_FREQ_HZ_HI_LEN 4
+#define	PR_FREQ_INFO_FREQ_HZ_HI_LBN 32
+#define	PR_FREQ_INFO_FREQ_HZ_HI_WIDTH 32
+#define	PR_FREQ_INFO_FREQ_HZ_LBN 0
+#define	PR_FREQ_INFO_FREQ_HZ_WIDTH 64
+/* Clock type, a programmable region may have multiple clocks of the same type.
+ * (matches enum CLOCK_TYPE)
+ */
+#define	PR_FREQ_INFO_TYPE_OFST 8
+#define	PR_FREQ_INFO_TYPE_LEN 2
+/* enum: Unused/reserved. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_UNUSED 0x0
+/* enum: Data clock. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_DATA 0x1
+/* enum: Kernel clock. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_KERNEL 0x2
+/* enum: System clock. */
+#define	PR_FREQ_INFO_CLOCK_TYPE_SYSTEM 0x3
+#define	PR_FREQ_INFO_TYPE_LBN 64
+#define	PR_FREQ_INFO_TYPE_WIDTH 16
+/* Assorted flags */
+#define	PR_FREQ_INFO_FLAGS_OFST 10
+#define	PR_FREQ_INFO_FLAGS_LEN 2
+#define	PR_FREQ_INFO_SETTABLE_OFST 10
+#define	PR_FREQ_INFO_SETTABLE_LBN 0
+#define	PR_FREQ_INFO_SETTABLE_WIDTH 1
+#define	PR_FREQ_INFO_FLAGS_LBN 80
+#define	PR_FREQ_INFO_FLAGS_WIDTH 16
+/* Clock name (NUL-terminated ASCII string) */
+#define	PR_FREQ_INFO_NAME_OFST 12
+#define	PR_FREQ_INFO_NAME_LEN 1
+#define	PR_FREQ_INFO_NAME_NUM 128
+#define	PR_FREQ_INFO_NAME_LBN 96
+#define	PR_FREQ_INFO_NAME_WIDTH 8
+
+
+/***********************************/
+/* MC_CMD_PR_FREQ_GET
+ * Query the current clock frequencies of the target region of a session. If
+ * the target region is 'empty' then an empty response should be returned.
+ * Returns ENOENT if the session handle doesn't exist; ESTALE if the target
+ * region has been updated by another session since the session was opened.
+ */
+#define	MC_CMD_PR_FREQ_GET 0x1aa
+#define	MC_CMD_PR_FREQ_GET_MSGSET 0x1aa
+#undef	MC_CMD_0x1aa_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1aa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_FREQ_GET_IN msgrequest */
+#define	MC_CMD_PR_FREQ_GET_IN_LEN 4
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_FREQ_GET_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_FREQ_GET_IN_HANDLE_LEN 4
+
+/* MC_CMD_PR_FREQ_GET_OUT msgresponse */
+#define	MC_CMD_PR_FREQ_GET_OUT_LENMIN 0
+#define	MC_CMD_PR_FREQ_GET_OUT_LENMAX 140
+#define	MC_CMD_PR_FREQ_GET_OUT_LENMAX_MCDI2 980
+#define	MC_CMD_PR_FREQ_GET_OUT_LEN(num) (0+140*(num))
+#define	MC_CMD_PR_FREQ_GET_OUT_INFOS_NUM(len) (((len)-0)/140)
+/* An array of PR_FREQ_INFO structures. */
+#define	MC_CMD_PR_FREQ_GET_OUT_INFOS_OFST 0
+#define	MC_CMD_PR_FREQ_GET_OUT_INFOS_LEN 140
+
+
+/***********************************/
+/* MC_CMD_PR_FREQ_SET
+ * Set the desired clock frequencies of the target region of a session. The
+ * FREQ_HZ array must contain the same number of entries as the output to
+ * MC_CMD_PR_FREQ_GET. Callers should expect that the resulting frequencies may
+ * not precisely match the input and can use MC_CMD_PR_FREQ_GET to determine
+ * the actual frequencies selected. The algorithm for selecting the resulting
+ * clock settings is a firmware implementation detail based on the capabilities
+ * of the device and the target region. It is expected that the firmware will
+ * not exceed the desired frequency for any clock; will successfully apply a
+ * frequency value obtained from MC_CMD_PR_FREQ_GET without further adjustment;
+ * and if an error is returned no changes will have been applied to any of the
+ * clocks. Although this command is available to all callers that are a member
+ * of the GENERAL privilege group an extra privilege check may be performed
+ * against the target region in addition to tbe check performed by
+ * MC_CMD_PR_OPEN. Returns ENOENT if the session handle doesn't exist; ESTALE
+ * if the target region has been updated by another session since the session
+ * was opened; EINVAL if the target region is 'empty' or the wrong number of
+ * desired clock frequencies was specified in the input; ERANGE if one or more
+ * desired clock frequencies were not achievable.
+ */
+#define	MC_CMD_PR_FREQ_SET 0x1ab
+#define	MC_CMD_PR_FREQ_SET_MSGSET 0x1ab
+#undef	MC_CMD_0x1ab_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1ab_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_PR_FREQ_SET_IN msgrequest */
+#define	MC_CMD_PR_FREQ_SET_IN_LENMIN 16
+#define	MC_CMD_PR_FREQ_SET_IN_LENMAX 248
+#define	MC_CMD_PR_FREQ_SET_IN_LENMAX_MCDI2 1016
+#define	MC_CMD_PR_FREQ_SET_IN_LEN(num) (8+8*(num))
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_NUM(len) (((len)-8)/8)
+/* Session handle from MC_CMD_PR_OPEN_OUT */
+#define	MC_CMD_PR_FREQ_SET_IN_HANDLE_OFST 0
+#define	MC_CMD_PR_FREQ_SET_IN_HANDLE_LEN 4
+/* Reserved, must be zero. */
+#define	MC_CMD_PR_FREQ_SET_IN_RESERVED_OFST 4
+#define	MC_CMD_PR_FREQ_SET_IN_RESERVED_LEN 4
+/* Desired frequency for each clock */
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_OFST 8
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LEN 8
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_OFST 8
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_LEN 4
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_LBN 64
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_LO_WIDTH 32
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_OFST 12
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_LEN 4
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_LBN 96
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_HI_WIDTH 32
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_MINNUM 1
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_MAXNUM 30
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_MAXNUM_MCDI2 126
+/* enum: Leave the clock frequency unchanged. */
+#define	MC_CMD_PR_FREQ_SET_IN_FREQ_HZ_DONT_CHANGE 0x0
+
+/* MC_CMD_PR_FREQ_SET_OUT msgresponse */
+#define	MC_CMD_PR_FREQ_SET_OUT_LEN 0
+
 /* TABLE_FIELD_DESCR structuredef: An individual table field descriptor. This
  * describes the location and properties of one N-bit field within a wider
  * M-bit key/mask/response value.
@@ -34323,4 +39938,151 @@
 /* MC_CMD_TABLE_DELETE_OUT msgresponse */
 #define	MC_CMD_TABLE_DELETE_OUT_LEN 0
 
+/* MC_CMD_QUEUE_HANDLE structuredef: On X4, to distinguish between full-
+ * featured (X2-style) VIs and low-latency (X3-style) queues, we use the top
+ * bits of the queue handle to specify the queue type in all MCDI calls which
+ * refer to VIs/queues. These bits should be masked off when indexing into a
+ * queue in the BAR.
+ */
+#define	MC_CMD_QUEUE_HANDLE_LEN 4
+/* Combined queue number and type. This is the ID returned by and passed into
+ * MCDI calls that use queues.
+ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_OFST 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LEN 4
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_NUM_OFST 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_NUM_LBN 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_NUM_WIDTH 24
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_OFST 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LBN 24
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_WIDTH 8
+/* enum: Indicates that the queue instance is a full-featured VI */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0
+/* enum: Indicates that the queue instance is a LL TXQ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1
+/* enum: Indicates that the queue instance is a LL RXQ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2
+/* enum: Indicates that the queue instance is a LL EVQ */
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LBN 0
+#define	MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_WIDTH 32
+
+/* QUEUE_HANDLE structuredef: This definition is deprecated, use
+ * MC_CMD_QUEUE_HANDLE above.
+ */
+#define	QUEUE_HANDLE_LEN 4
+/* Combined queue number and type. This is the ID returned by and passed into
+ * MCDI calls that use queues.
+ */
+#define	QUEUE_HANDLE_QUEUE_HANDLE_OFST 0
+#define	QUEUE_HANDLE_QUEUE_HANDLE_LEN 4
+#define	QUEUE_HANDLE_QUEUE_NUM_OFST 0
+#define	QUEUE_HANDLE_QUEUE_NUM_LBN 0
+#define	QUEUE_HANDLE_QUEUE_NUM_WIDTH 24
+#define	QUEUE_HANDLE_QUEUE_TYPE_OFST 0
+#define	QUEUE_HANDLE_QUEUE_TYPE_LBN 24
+#define	QUEUE_HANDLE_QUEUE_TYPE_WIDTH 8
+/* enum: Indicates that the queue instance is a full-featured VI */
+#define	QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0
+/* enum: Indicates that the queue instance is a LL TXQ */
+#define	QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1
+/* enum: Indicates that the queue instance is a LL RXQ */
+#define	QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2
+/* enum: Indicates that the queue instance is a LL EVQ */
+#define	QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3
+#define	QUEUE_HANDLE_QUEUE_HANDLE_LBN 0
+#define	QUEUE_HANDLE_QUEUE_HANDLE_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_ALLOC_LL_QUEUES
+ * Allocate low latency (X3-style) queues for current PCI function. Can be
+ * called more than once if desired to allocate more queues.
+ */
+#define	MC_CMD_ALLOC_LL_QUEUES 0x1dd
+#define	MC_CMD_ALLOC_LL_QUEUES_MSGSET 0x1dd
+#undef	MC_CMD_0x1dd_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1dd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_ALLOC_LL_QUEUES_IN msgrequest */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_LEN 24
+/* The minimum number of TXQs that is acceptable */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_OFST 0
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_LEN 4
+/* The maximum number of TXQs that would be useful */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_OFST 4
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_LEN 4
+/* The minimum number of RXQs that is acceptable */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_OFST 8
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_LEN 4
+/* The maximum number of RXQs that would be useful */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_OFST 12
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_LEN 4
+/* The minimum number of EVQs that is acceptable */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_OFST 16
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_LEN 4
+/* The maximum number of EVQs that would be useful */
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_OFST 20
+#define	MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_LEN 4
+
+/* MC_CMD_ALLOC_LL_QUEUES_OUT msgresponse */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LENMIN 16
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX 252
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX_MCDI2 1020
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_LEN(num) (12+4*(num))
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_NUM(len) (((len)-12)/4)
+/* The number of TXQs allocated in this request */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_OFST 0
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_LEN 4
+/* The number of RXQs allocated in this request */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_OFST 4
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_LEN 4
+/* The number of EVQs allocated in this request */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_OFST 8
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_LEN 4
+/* A list of allocated queues, returned as MC_CMD_QUEUE_HANDLEs, not
+ * necessarily contiguous. TXQs are first in the list, followed by RXQs then
+ * EVQs. The type of each queue is indicated by the top bits (see the
+ * QUEUE_TYPE enum)
+ */
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_OFST 12
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_LEN 4
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MINNUM 1
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM 60
+#define	MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM_MCDI2 252
+
+
+/***********************************/
+/* MC_CMD_FREE_LL_QUEUES
+ * Free low latency (X3-style) queues for current PCI function.
+ */
+#define	MC_CMD_FREE_LL_QUEUES 0x1de
+#define	MC_CMD_FREE_LL_QUEUES_MSGSET 0x1de
+#undef	MC_CMD_0x1de_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1de_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FREE_LL_QUEUES_IN msgrequest */
+#define	MC_CMD_FREE_LL_QUEUES_IN_LENMIN 8
+#define	MC_CMD_FREE_LL_QUEUES_IN_LENMAX 252
+#define	MC_CMD_FREE_LL_QUEUES_IN_LENMAX_MCDI2 1020
+#define	MC_CMD_FREE_LL_QUEUES_IN_LEN(num) (4+4*(num))
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_NUM(len) (((len)-4)/4)
+/* The number of queues to free. */
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_OFST 0
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_LEN 4
+/* A list of queues to free, as a list of MC_CMD_QUEUE_HANDLEs. They must have
+ * all been previously allocated by MC_CMD_ALLOC_LL_QUEUES. The type of each
+ * queue should be indicated by the top bits.
+ */
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_OFST 4
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_LEN 4
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MINNUM 1
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM 62
+#define	MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM_MCDI2 254
+
+/* MC_CMD_FREE_LL_QUEUES_OUT msgresponse */
+#define	MC_CMD_FREE_LL_QUEUES_OUT_LEN 0
+
 #endif /* _SIENA_MC_DRIVER_PCOL_H */
-- 
2.39.5

[PATCH v2 19/45] common/sfc_efx/base: provide a stub for basic netport attach

[Ivan Malov]

New NICs (for instance, Medford4) offer new netport MCDI for
managing physical ports, which will supersede the legacy one.
Scope out the new interface initialisation on NIC probe path.
That will be augmented with the actual code by later patches.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_nic.c  | 30 ++++++++++++++++++------
 drivers/common/sfc_efx/base/efx_impl.h  | 15 ++++++++++++
 drivers/common/sfc_efx/base/efx_np.c    | 31 +++++++++++++++++++++++++
 drivers/common/sfc_efx/base/meson.build |  1 +
 4 files changed, 70 insertions(+), 7 deletions(-)
 create mode 100644 drivers/common/sfc_efx/base/efx_np.c

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index bce9df0aa6..627144cfb0 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -2220,6 +2220,9 @@ efx_mcdi_nic_board_cfg(
 
 	encp->enc_board_type = board_type;
 
+	if (efx_np_supported(enp) != B_FALSE)
+		goto skip_phy_props;
+
 	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
 		goto fail8;
@@ -2245,6 +2248,7 @@ efx_mcdi_nic_board_cfg(
 	epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
 	epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
 
+skip_phy_props:
 	/* Check capabilities of running datapath firmware */
 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
 		goto fail10;
@@ -2498,6 +2502,10 @@ ef10_nic_probe(
 	if ((rc = ef10_nic_board_cfg(enp)) != 0)
 		goto fail4;
 
+	rc = efx_np_attach(enp);
+	if (rc != 0)
+		goto fail5;
+
 	/*
 	 * Set default driver config limits (based on board config).
 	 *
@@ -2515,36 +2523,41 @@ ef10_nic_probe(
 #if EFSYS_OPT_MAC_STATS
 	/* Wipe the MAC statistics */
 	if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
-		goto fail5;
+		goto fail6;
 #endif
 
 #if EFSYS_OPT_LOOPBACK
-	if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
-		goto fail6;
+	if (efx_np_supported(enp) == B_FALSE) {
+		rc = efx_mcdi_get_loopback_modes(enp);
+		if (rc != 0)
+			goto fail7;
+	}
 #endif
 
 #if EFSYS_OPT_MON_STATS
 	if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
 		/* Unprivileged functions do not have access to sensors */
 		if (rc != EACCES)
-			goto fail7;
+			goto fail8;
 	}
 #endif
 
 	return (0);
 
 #if EFSYS_OPT_MON_STATS
+fail8:
+	EFSYS_PROBE(fail8);
+#endif
+#if EFSYS_OPT_LOOPBACK
 fail7:
 	EFSYS_PROBE(fail7);
 #endif
-#if EFSYS_OPT_LOOPBACK
+#if EFSYS_OPT_MAC_STATS
 fail6:
 	EFSYS_PROBE(fail6);
 #endif
-#if EFSYS_OPT_MAC_STATS
 fail5:
 	EFSYS_PROBE(fail5);
-#endif
 fail4:
 	EFSYS_PROBE(fail4);
 fail3:
@@ -3004,6 +3017,9 @@ ef10_nic_unprobe(
 #if EFSYS_OPT_MON_STATS
 	mcdi_mon_cfg_free(enp);
 #endif /* EFSYS_OPT_MON_STATS */
+
+	efx_np_detach(enp);
+
 	(void) efx_mcdi_drv_attach(enp, B_FALSE);
 }
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 89b7e0292e..9ad973ded7 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1880,6 +1880,21 @@ struct efx_virtio_vq_s {
 
 #endif /* EFSYS_OPT_VIRTIO */
 
+LIBEFX_INTERNAL
+extern			boolean_t
+efx_np_supported(
+	__in		efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_attach(
+	__in		efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern		void
+efx_np_detach(
+	__in	efx_nic_t *enp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
new file mode 100644
index 0000000000..432185f311
--- /dev/null
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#include "efx.h"
+#include "efx_impl.h"
+
+			boolean_t
+efx_np_supported(
+	__in		efx_nic_t *enp)
+{
+	return (enp->en_family >= EFX_FAMILY_MEDFORD4) ? B_TRUE : B_FALSE;
+}
+
+	__checkReturn	efx_rc_t
+efx_np_attach(
+	__in		efx_nic_t *enp)
+{
+	if (efx_np_supported(enp) == B_FALSE)
+		return (0);
+
+	return (0);
+}
+
+		void
+efx_np_detach(
+	__in	efx_nic_t *enp)
+{
+	if (efx_np_supported(enp) == B_FALSE)
+		return;
+}
diff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build
index c8deb4555e..02d5b2fbb9 100644
--- a/drivers/common/sfc_efx/base/meson.build
+++ b/drivers/common/sfc_efx/base/meson.build
@@ -20,6 +20,7 @@ sources = [
         'efx_mcdi.c',
         'efx_mon.c',
         'efx_nic.c',
+        'efx_np.c',
         'efx_nvram.c',
         'efx_pci.c',
         'efx_phy.c',
-- 
2.39.5

[PATCH v2 20/45] common/sfc_efx/base: provide defaults on netport attach path

[Ivan Malov]

Fill in some port information, including legacy Siena fields.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_np.c | 44 ++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 432185f311..abb8e20e4d 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -12,13 +12,57 @@ efx_np_supported(
 	return (enp->en_family >= EFX_FAMILY_MEDFORD4) ? B_TRUE : B_FALSE;
 }
 
+static				void
+efx_np_assign_legacy_props(
+	__in			efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+
+	memset(encp->enc_phy_revision, 0, sizeof (encp->enc_phy_revision));
+	encp->enc_phy_type = 0;
+
+#if EFSYS_OPT_NAMES
+	memset(encp->enc_phy_name, 0, sizeof (encp->enc_phy_name));
+#endif /* EFSYS_OPT_NAMES */
+
+#if EFSYS_OPT_PHY_STATS
+	encp->enc_mcdi_phy_stat_mask = 0;
+#endif /* EFSYS_OPT_PHY_STATS */
+
+#if EFSYS_OPT_PHY_FLAGS
+	encp->enc_phy_flags_mask = 0;
+#endif /* EFSYS_OPT_PHY_FLAGS */
+
+#if EFSYS_OPT_BIST
+	encp->enc_bist_mask = 0;
+#endif /* EFSYS_OPT_BIST */
+
+	encp->enc_mcdi_mdio_channel = 0;
+	encp->enc_port = 0;
+}
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
 {
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+
 	if (efx_np_supported(enp) == B_FALSE)
 		return (0);
 
+	/*
+	 * Some EFX properties are mostly leftover from Siena era
+	 * and we prefer to initialise those to harmless defaults.
+	 */
+	efx_np_assign_legacy_props(enp);
+
+#if EFSYS_OPT_PHY_LED_CONTROL
+	encp->enc_led_mask = 1U << EFX_PHY_LED_DEFAULT;
+#endif /* EFSYS_OPT_PHY_LED_CONTROL */
+
+	epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID;
+	epp->ep_module_type = EFX_PHY_MEDIA_INVALID;
 	return (0);
 }
 
-- 
2.39.5

[PATCH v2 21/45] common/sfc_efx/base: obtain assigned netport handle from NIC

[Ivan Malov]

Get an 'assigned' netport handle for the current MCDI entity.
This handle will be used when sending other netport commands.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h |  4 +++
 drivers/common/sfc_efx/base/efx_np.c   | 50 ++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 9ad973ded7..4952f45121 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -335,6 +335,8 @@ typedef struct efx_virtio_ops_s {
 } efx_virtio_ops_t;
 #endif /* EFSYS_OPT_VIRTIO */
 
+typedef uint32_t efx_np_handle_t;
+
 typedef struct efx_port_s {
 	efx_mac_type_t		ep_mac_type;
 	uint32_t		ep_phy_type;
@@ -378,6 +380,8 @@ typedef struct efx_port_s {
 #endif
 	const efx_mac_ops_t	*ep_emop;
 	const efx_phy_ops_t	*ep_epop;
+
+	efx_np_handle_t		ep_np_handle;
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index abb8e20e4d..404d2887b0 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -41,12 +41,53 @@ efx_np_assign_legacy_props(
 	encp->enc_port = 0;
 }
 
+static	__checkReturn		efx_rc_t
+efx_np_get_assigned_handle(
+	__in			efx_nic_t *enp,
+	__out			efx_np_handle_t *nphp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN,
+	    MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN;
+	req.emr_in_length = MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN;
+	req.emr_cmd = MC_CMD_GET_ASSIGNED_PORT_HANDLE;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	*nphp = MCDI_OUT_DWORD(req, GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE);
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
 
 	if (efx_np_supported(enp) == B_FALSE)
 		return (0);
@@ -63,7 +104,16 @@ efx_np_attach(
 
 	epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID;
 	epp->ep_module_type = EFX_PHY_MEDIA_INVALID;
+
+	rc = efx_np_get_assigned_handle(enp, &epp->ep_np_handle);
+	if (rc != 0)
+		goto fail1;
+
 	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
 }
 
 		void
-- 
2.39.5

[PATCH v2 22/45] common/sfc_efx/base: allow for const in MCDI struct accessor

[Ivan Malov]

The existing code is fine, however, future patches will need
to use this macro on buffers that are passed by callers with
const qualifier. With 'cast-qual' enabled, this macro causes
compile warnings in such cases. Rework it to allow for const.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_mcdi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/sfc_efx/base/efx_mcdi.h b/drivers/common/sfc_efx/base/efx_mcdi.h
index f13bf43da6..4e82717015 100644
--- a/drivers/common/sfc_efx/base/efx_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_mcdi.h
@@ -536,7 +536,7 @@ efx_mcdi_set_nic_addr_regions(
 		EFX_DWORD_1) << 32)
 
 #define MCDI_STRUCT_MEMBER(_buf, _type, _ofst)				\
-	((_type *)((char *)_buf + _ofst ## _OFST))	\
+	((_type *)((char *)(uintptr_t)(_buf) + _ofst ## _OFST))
 
 #define MCDI_STRUCT_BYTE(_buf, _ofst)					\
 	EFX_BYTE_FIELD(*MCDI_STRUCT_MEMBER(_buf, efx_byte_t, _ofst),	\
-- 
2.39.5

[PATCH v2 23/45] common/sfc_efx/base: get netport fixed capabilities on probe

[Ivan Malov]

These make the basic subset of PHY capabilities known to EFX

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx.h    |  21 ++-
 drivers/common/sfc_efx/base/efx_np.c | 209 +++++++++++++++++++++++++++
 2 files changed, 224 insertions(+), 6 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index a9ed3f423f..2c6af5f6b5 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1212,6 +1212,11 @@ typedef enum efx_phy_cap_type_e {
 	EFX_PHY_CAP_RS_FEC_REQUESTED,
 	EFX_PHY_CAP_25G_BASER_FEC,
 	EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
+	EFX_PHY_CAP_200000FDX,
+	EFX_PHY_CAP_IEEE_RS_INT_FEC,
+	EFX_PHY_CAP_IEEE_RS_INT_FEC_REQUESTED,
+	EFX_PHY_CAP_ETCS_RS_LL_FEC,
+	EFX_PHY_CAP_ETCS_RS_LL_FEC_REQUESTED,
 	EFX_PHY_CAP_NTYPES
 } efx_phy_cap_type_t;
 
@@ -4009,12 +4014,16 @@ typedef enum efx_phy_fec_type_e {
 
 #define EFX_PHY_CAP_FEC_BIT(_fec_bit) (1U << EFX_PHY_CAP_##_fec_bit)
 #define EFX_PHY_CAP_FEC_MASK \
-	(EFX_PHY_CAP_FEC_BIT(BASER_FEC) |		\
-	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) |		\
-	 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED) |	\
-	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED) |	\
-	 EFX_PHY_CAP_FEC_BIT(RS_FEC) |			\
-	 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED))
+	(EFX_PHY_CAP_FEC_BIT(BASER_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED) |		\
+	 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED) |		\
+	 EFX_PHY_CAP_FEC_BIT(RS_FEC) |				\
+	 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED) |		\
+	 EFX_PHY_CAP_FEC_BIT(IEEE_RS_INT_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(IEEE_RS_INT_FEC_REQUESTED) |	\
+	 EFX_PHY_CAP_FEC_BIT(ETCS_RS_LL_FEC) |			\
+	 EFX_PHY_CAP_FEC_BIT(ETCS_RS_LL_FEC_REQUESTED))
 
 LIBEFX_API
 extern	__checkReturn	efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 404d2887b0..100cf4d8a7 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -76,6 +76,203 @@ efx_np_get_assigned_handle(
 fail2:
 	EFSYS_PROBE(fail2);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+struct efx_np_cap_map {
+	uint16_t	encm_hw;
+	uint16_t	encm_sw;
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_tech[] = {
+	/* 1G */
+	{ MC_CMD_ETH_TECH_1000BASEKX, EFX_PHY_CAP_1000FDX },
+	{ MC_CMD_ETH_TECH_1000BASEX, EFX_PHY_CAP_1000FDX },
+
+	/* 10G */
+	{ MC_CMD_ETH_TECH_10GBASE_KR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_CR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_SR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_LR, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_LRM, EFX_PHY_CAP_10000FDX },
+	{ MC_CMD_ETH_TECH_10GBASE_ER, EFX_PHY_CAP_10000FDX },
+
+	/* 25GBASE */
+	{ MC_CMD_ETH_TECH_25GBASE_CR, EFX_PHY_CAP_25000FDX },
+	{ MC_CMD_ETH_TECH_25GBASE_KR, EFX_PHY_CAP_25000FDX },
+	{ MC_CMD_ETH_TECH_25GBASE_SR, EFX_PHY_CAP_25000FDX },
+	{ MC_CMD_ETH_TECH_25GBASE_LR_ER, EFX_PHY_CAP_25000FDX },
+
+	/* 40G */
+	{ MC_CMD_ETH_TECH_40GBASE_KR4, EFX_PHY_CAP_40000FDX },
+	{ MC_CMD_ETH_TECH_40GBASE_CR4, EFX_PHY_CAP_40000FDX },
+	{ MC_CMD_ETH_TECH_40GBASE_SR4, EFX_PHY_CAP_40000FDX },
+	{ MC_CMD_ETH_TECH_40GBASE_LR4, EFX_PHY_CAP_40000FDX },
+
+	/* 50G */
+	{ MC_CMD_ETH_TECH_50GBASE_CR2, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_KR2, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_SR2, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_KR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_SR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_CR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_LR_ER_FR, EFX_PHY_CAP_50000FDX },
+	{ MC_CMD_ETH_TECH_50GBASE_DR, EFX_PHY_CAP_50000FDX },
+
+	/* 100G */
+	{ MC_CMD_ETH_TECH_100GBASE_KR4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_SR4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_LR4_ER4, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_KR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_SR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_DR2, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_KR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_SR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_LR_ER_FR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_DR, EFX_PHY_CAP_100000FDX },
+	{ MC_CMD_ETH_TECH_100GBASE_CR10, EFX_PHY_CAP_100000FDX },
+
+	/* 200G */
+	{ MC_CMD_ETH_TECH_200GBASE_KR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_SR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_DR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_CR4, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_KR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_SR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_DR2, EFX_PHY_CAP_200000FDX },
+	{ MC_CMD_ETH_TECH_200GBASE_CR2, EFX_PHY_CAP_200000FDX },
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_fec[] = {
+	{ MC_CMD_FEC_BASER, EFX_PHY_CAP_BASER_FEC },
+	{ MC_CMD_FEC_RS, EFX_PHY_CAP_RS_FEC },
+	{ MC_CMD_FEC_IEEE_RS_INT, EFX_PHY_CAP_IEEE_RS_INT_FEC },
+	{ MC_CMD_FEC_ETCS_RS_LL, EFX_PHY_CAP_ETCS_RS_LL_FEC },
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_fec_req[] = {
+	{ MC_CMD_FEC_BASER, EFX_PHY_CAP_BASER_FEC_REQUESTED },
+	{ MC_CMD_FEC_RS, EFX_PHY_CAP_RS_FEC_REQUESTED },
+	{ MC_CMD_FEC_IEEE_RS_INT, EFX_PHY_CAP_IEEE_RS_INT_FEC_REQUESTED },
+	{ MC_CMD_FEC_ETCS_RS_LL, EFX_PHY_CAP_ETCS_RS_LL_FEC_REQUESTED },
+};
+
+static const struct efx_np_cap_map efx_np_cap_map_pause[] = {
+	{ MC_CMD_PAUSE_MODE_AN_ASYM_DIR, EFX_PHY_CAP_ASYM },
+	{ MC_CMD_PAUSE_MODE_AN_PAUSE, EFX_PHY_CAP_PAUSE },
+};
+
+#define	CAP_BYTE(_map)	((_map)->encm_hw / CHAR_BIT)
+
+#define	CAP_VLD(_map, _data_nbytes)	(CAP_BYTE(_map) < (_data_nbytes))
+
+#define	CAP_FLAG(_map)	(1U << ((_map)->encm_hw % CHAR_BIT))
+
+#define	CAP_SUP(_map, _data)						\
+	(((_data)[CAP_BYTE(_map)] & CAP_FLAG(_map)) == CAP_FLAG(_map))
+
+#define	FOREACH_SUP_CAP(_map, _map_nentries, _data, _data_nbytes)	\
+	for (unsigned int _i = 0; _i < (_map_nentries); ++_i, ++(_map))	\
+		if (CAP_VLD(_map, _data_nbytes) && CAP_SUP(_map, _data))
+
+static					void
+efx_np_cap_mask_hw_to_sw(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__out				uint32_t *sw_cap_maskp)
+{
+	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
+	    hw_cap_data, hw_cap_data_nbytes) {
+		*sw_cap_maskp |= 1U << hw_sw_map->encm_sw;
+	}
+}
+
+/*
+ * Convert the given fraction of raw HW netport capability data (identified by
+ * the given section name of the MCDI response) to the EFX mask representation,
+ * in accordance with the specified collection of HW-to-SW capability mappings.
+ */
+#define	EFX_NP_CAP_MASK_HW_TO_SW(					\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data, _sw_maskp)	\
+	efx_np_cap_mask_hw_to_sw((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN, (_sw_maskp))
+
+static				void
+efx_np_cap_hw_data_to_sw_mask(
+	__in			const uint8_t *hw_data,
+	__out			uint32_t *sw_maskp)
+{
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_tech, ETH_AN_FIELDS_TECH_MASK,
+	    hw_data, sw_maskp);
+
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_fec, ETH_AN_FIELDS_FEC_MASK,
+	    hw_data, sw_maskp);
+
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_fec_req, ETH_AN_FIELDS_FEC_REQ,
+	    hw_data, sw_maskp);
+
+	EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_pause, ETH_AN_FIELDS_PAUSE_MASK,
+	    hw_data, sw_maskp);
+}
+
+static	__checkReturn		efx_rc_t
+efx_np_get_fixed_port_props(
+	__in			efx_nic_t *enp,
+	__in			efx_np_handle_t nph,
+	__out_opt		uint32_t *sup_cap_maskp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN,
+	    MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN);
+	const uint8_t *cap_data;
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN;
+	req.emr_in_length = MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN;
+	req.emr_cmd = MC_CMD_GET_FIXED_PORT_PROPERTIES;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE, nph);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used <
+	    MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	cap_data = MCDI_OUT2(req, const uint8_t,
+		    GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES);
+
+	if (sup_cap_maskp != NULL)
+		efx_np_cap_hw_data_to_sw_mask(cap_data, sup_cap_maskp);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
@@ -109,8 +306,20 @@ efx_np_attach(
 	if (rc != 0)
 		goto fail1;
 
+	/*
+	 * FIXME: This may need revisiting for VFs, which
+	 * don't necessarily have access to these details.
+	 */
+	rc = efx_np_get_fixed_port_props(enp, epp->ep_np_handle,
+		    &epp->ep_phy_cap_mask);
+	if (rc != 0)
+		goto fail2;
+
 	return (0);
 
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
-- 
2.39.5

[PATCH v2 24/45] common/sfc_efx/base: decode netport link state on probe path

[Ivan Malov]

Retrieved properties form the advertised PHY capability mask.
The new code also helps to check support for autonegotiation.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h | 12 +++++
 drivers/common/sfc_efx/base/efx_np.c   | 67 ++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 4952f45121..a3e60fd19b 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1899,6 +1899,18 @@ extern		void
 efx_np_detach(
 	__in	efx_nic_t *enp);
 
+typedef struct efx_np_link_state_s {
+	uint32_t		enls_adv_cap_mask;
+	boolean_t		enls_an_supported;
+} efx_np_link_state_t;
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_link_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_link_state_t *lsp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 100cf4d8a7..eac3bb06ee 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -273,6 +273,61 @@ efx_np_get_fixed_port_props(
 fail2:
 	EFSYS_PROBE(fail2);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+efx_np_link_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_link_state_t *lsp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_LINK_STATE_IN_LEN,
+	    MC_CMD_LINK_STATE_OUT_V3_LEN);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_LINK_STATE_OUT_V3_LEN;
+	req.emr_in_length = MC_CMD_LINK_STATE_IN_LEN;
+	req.emr_cmd = MC_CMD_LINK_STATE;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, LINK_STATE_IN_PORT_HANDLE, nph);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_LINK_STATE_OUT_V3_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	memset(lsp, 0, sizeof (*lsp));
+
+	if (MCDI_OUT_DWORD(req, LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT) !=
+	    MC_CMD_AN_NONE)
+		lsp->enls_an_supported = B_TRUE;
+
+	if (lsp->enls_an_supported != B_FALSE)
+		lsp->enls_adv_cap_mask |= 1U << EFX_PHY_CAP_AN;
+
+	efx_np_cap_hw_data_to_sw_mask(
+	    MCDI_OUT2(req, const uint8_t, LINK_STATE_OUT_ADVERTISED_ABILITIES),
+	    &lsp->enls_adv_cap_mask);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
@@ -284,6 +339,7 @@ efx_np_attach(
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
+	efx_np_link_state_t ls;
 	efx_rc_t rc;
 
 	if (efx_np_supported(enp) == B_FALSE)
@@ -315,8 +371,19 @@ efx_np_attach(
 	if (rc != 0)
 		goto fail2;
 
+	rc = efx_np_link_state(enp, epp->ep_np_handle, &ls);
+	if (rc != 0)
+		goto fail3;
+
+	if (ls.enls_an_supported != B_FALSE)
+		epp->ep_phy_cap_mask |= 1U << EFX_PHY_CAP_AN;
+
+	epp->ep_adv_cap_mask = ls.enls_adv_cap_mask;
 	return (0);
 
+fail3:
+	EFSYS_PROBE(fail3);
+
 fail2:
 	EFSYS_PROBE(fail2);
 
-- 
2.39.5

[PATCH v2 25/45] common/sfc_efx/base: fill in loopback modes on netport probe

[Ivan Malov]

Indicate support for some of the loopback modes known to EFX.
Such have been technology-dependent, but, on netport capable
NICs, they are backed by new generic modes, that are tied to
the stages in the processing chain where loopback can happen.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx.h      |   1 +
 drivers/common/sfc_efx/base/efx_impl.h |   2 +
 drivers/common/sfc_efx/base/efx_np.c   | 157 ++++++++++++++++++++++++-
 3 files changed, 158 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 2c6af5f6b5..7ffa1f4cbd 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -655,6 +655,7 @@ typedef enum efx_link_mode_e {
 	EFX_LINK_25000FDX,
 	EFX_LINK_50000FDX,
 	EFX_LINK_100000FDX,
+	EFX_LINK_200000FDX,
 	EFX_LINK_NMODES
 } efx_link_mode_t;
 
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index a3e60fd19b..3a9c6fe3fd 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -382,6 +382,8 @@ typedef struct efx_port_s {
 	const efx_phy_ops_t	*ep_epop;
 
 	efx_np_handle_t		ep_np_handle;
+	efx_qword_t		ep_np_loopback_cap_mask;
+	uint8_t			ep_np_cap_data_raw[MC_CMD_ETH_AN_FIELDS_LEN];
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index eac3bb06ee..1b670435db 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -232,7 +232,9 @@ static	__checkReturn		efx_rc_t
 efx_np_get_fixed_port_props(
 	__in			efx_nic_t *enp,
 	__in			efx_np_handle_t nph,
-	__out_opt		uint32_t *sup_cap_maskp)
+	__out_opt		uint8_t *sup_cap_rawp,
+	__out_opt		uint32_t *sup_cap_maskp,
+	__out_opt		efx_qword_t *loopback_cap_maskp)
 {
 	EFX_MCDI_DECLARE_BUF(payload,
 	    MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN,
@@ -268,6 +270,18 @@ efx_np_get_fixed_port_props(
 	if (sup_cap_maskp != NULL)
 		efx_np_cap_hw_data_to_sw_mask(cap_data, sup_cap_maskp);
 
+	if (sup_cap_rawp != NULL) {
+		memcpy(sup_cap_rawp,
+		    MCDI_OUT2(req, const uint8_t,
+			    GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES),
+		    MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_LEN);
+	}
+
+	if (loopback_cap_maskp != NULL) {
+		*loopback_cap_maskp = *MCDI_OUT2(req, efx_qword_t,
+		    GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2);
+	}
+
 	return (0);
 
 fail2:
@@ -333,6 +347,139 @@ efx_np_link_state(
 	return (rc);
 }
 
+#if EFSYS_OPT_LOOPBACK
+static	__checkReturn		efx_rc_t
+efx_np_sw_link_mode_to_cap(
+	__in			efx_link_mode_t link_mode,
+	__out			uint16_t *capp)
+{
+	switch (link_mode) {
+	case EFX_LINK_1000FDX:
+		*capp = EFX_PHY_CAP_1000FDX;
+		break;
+	case EFX_LINK_10000FDX:
+		*capp = EFX_PHY_CAP_10000FDX;
+		break;
+	case EFX_LINK_40000FDX:
+		*capp = EFX_PHY_CAP_40000FDX;
+		break;
+	case EFX_LINK_25000FDX:
+		*capp = EFX_PHY_CAP_25000FDX;
+		break;
+	case EFX_LINK_50000FDX:
+		*capp = EFX_PHY_CAP_50000FDX;
+		break;
+	case EFX_LINK_100000FDX:
+		*capp = EFX_PHY_CAP_100000FDX;
+		break;
+	case EFX_LINK_200000FDX:
+		*capp = EFX_PHY_CAP_200000FDX;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	return (0);
+}
+
+static					void
+efx_np_cap_enum_sw_to_hw(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__in				uint16_t enum_sw,
+	__out				boolean_t *supportedp,
+	__out_opt			uint16_t *enum_hwp)
+{
+	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
+	    hw_cap_data, hw_cap_data_nbytes) {
+		if (hw_sw_map->encm_sw != enum_sw)
+			continue;
+
+		if (enum_hwp != NULL)
+			*enum_hwp = hw_sw_map->encm_hw;
+
+		*supportedp = B_TRUE;
+		return;
+	}
+
+	*supportedp = B_FALSE;
+}
+
+/*
+ * Convert the given EFX PHY capability enum value to the HW counterpart,
+ * provided that the capability is supported by the HW, where the latter
+ * is detected from the given fraction of raw HW netport capability data.
+ *
+ * As the mapping of a capability from EFX to HW can be one to many, use
+ * the first supported HW capability bit, in accordance with the HW data.
+ */
+#define	EFX_NP_CAP_ENUM_SW_TO_HW(						\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
+	    _enum_sw, _supportedp, _enum_hwp)				\
+	efx_np_cap_enum_sw_to_hw((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN, (_enum_sw),			\
+	    (_supportedp), (_enum_hwp))
+
+static				void
+efx_np_assign_loopback_props(
+	__in			efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+	efx_qword_t lbm_off;
+	efx_qword_t lbm_sup;
+	unsigned int i;
+
+	EFX_ZERO_QWORD(lbm_off);
+	EFX_SET_QWORD_BIT(lbm_off, EFX_LOOPBACK_OFF);
+
+	/*
+	 * Netport MCDI capable NICs support loopback modes which are
+	 * generalisations of the existing modes that specify roughly
+	 * where in the processing chain the loopback occurs, without
+	 * the need to refer to the specific technology. Provide some
+	 * to users under the guise of older technology-specific ones.
+	 */
+	EFX_ZERO_QWORD(lbm_sup);
+	EFX_SET_QWORD_BIT(lbm_sup, EFX_LOOPBACK_OFF);
+
+	if (EFX_TEST_QWORD_BIT(epp->ep_np_loopback_cap_mask,
+			    MC_CMD_LOOPBACK_V2_AUTO))
+		EFX_SET_QWORD_BIT(lbm_sup, EFX_LOOPBACK_DATA);
+
+	if (EFX_TEST_QWORD_BIT(epp->ep_np_loopback_cap_mask,
+			    MC_CMD_LOOPBACK_V2_POST_PCS))
+		EFX_SET_QWORD_BIT(lbm_sup, EFX_LOOPBACK_PCS);
+
+	for (i = 0; i < EFX_ARRAY_SIZE(encp->enc_loopback_types); ++i) {
+		boolean_t supported = B_FALSE;
+		uint16_t cap_enum_sw;
+		efx_rc_t rc;
+
+		rc = efx_np_sw_link_mode_to_cap(i, &cap_enum_sw);
+		if (rc != 0) {
+			/* No support for this link mode => no loopbacks. */
+			encp->enc_loopback_types[i] = lbm_off;
+			continue;
+		}
+
+		EFX_NP_CAP_ENUM_SW_TO_HW(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, epp->ep_np_cap_data_raw,
+		    cap_enum_sw, &supported, NULL);
+
+		if (supported != B_FALSE)
+			encp->enc_loopback_types[i] = lbm_sup;
+		else
+			encp->enc_loopback_types[i] = lbm_off;
+	}
+}
+#endif /* EFSYS_OPT_LOOPBACK */
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
@@ -367,7 +514,8 @@ efx_np_attach(
 	 * don't necessarily have access to these details.
 	 */
 	rc = efx_np_get_fixed_port_props(enp, epp->ep_np_handle,
-		    &epp->ep_phy_cap_mask);
+		    epp->ep_np_cap_data_raw, &epp->ep_phy_cap_mask,
+		    &epp->ep_np_loopback_cap_mask);
 	if (rc != 0)
 		goto fail2;
 
@@ -379,6 +527,11 @@ efx_np_attach(
 		epp->ep_phy_cap_mask |= 1U << EFX_PHY_CAP_AN;
 
 	epp->ep_adv_cap_mask = ls.enls_adv_cap_mask;
+
+#if EFSYS_OPT_LOOPBACK
+	efx_np_assign_loopback_props(enp);
+#endif /* EFSYS_OPT_LOOPBACK */
+
 	return (0);
 
 fail3:
-- 
2.39.5

[PATCH v2 26/45] common/sfc_efx/base: introduce Medford4 stub for PHY methods

[Ivan Malov]

Provide only a couple of no-op methods for now. Next patches
will augment the file with more, based on newer netport MCDI.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      |  4 +++
 drivers/common/sfc_efx/base/efx_phy.c       | 22 +++++++++++++++-
 drivers/common/sfc_efx/base/medford4_impl.h | 29 +++++++++++++++++++++
 drivers/common/sfc_efx/base/medford4_phy.c  | 28 ++++++++++++++++++++
 drivers/common/sfc_efx/base/meson.build     |  1 +
 5 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
 create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 3a9c6fe3fd..16b7f7640d 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -45,6 +45,10 @@
 #include "rhead_impl.h"
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+#include "medford4_impl.h"
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index 3d792f20b8..537865767a 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -68,6 +68,26 @@ static const efx_phy_ops_t	__efx_phy_rhead_ops = {
 };
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+static const efx_phy_ops_t	__efx_phy_medford4_ops = {
+	medford4_phy_power,		/* epo_power */
+	NULL,				/* epo_reset */
+	ef10_phy_reconfigure,		/* epo_reconfigure */
+	medford4_phy_verify,		/* epo_verify */
+	ef10_phy_oui_get,		/* epo_oui_get */
+	ef10_phy_link_state_get,	/* epo_link_state_get */
+#if EFSYS_OPT_PHY_STATS
+	ef10_phy_stats_update,		/* epo_stats_update */
+#endif	/* EFSYS_OPT_PHY_STATS */
+#if EFSYS_OPT_BIST
+	ef10_bist_enable_offline,	/* epo_bist_enable_offline */
+	ef10_bist_start,		/* epo_bist_start */
+	ef10_bist_poll,			/* epo_bist_poll */
+	ef10_bist_stop,			/* epo_bist_stop */
+#endif	/* EFSYS_OPT_BIST */
+};
+#endif	/* EFSYS_OPT_MEDFORD4 */
+
 	__checkReturn	efx_rc_t
 efx_phy_probe(
 	__in		efx_nic_t *enp)
@@ -116,7 +136,7 @@ efx_phy_probe(
 
 #if EFSYS_OPT_MEDFORD4
 	case EFX_FAMILY_MEDFORD4:
-		epop = &__efx_phy_ef10_ops;
+		epop = &__efx_phy_medford4_ops;
 	break;
 #endif	/* EFSYS_OPT_MEDFORD4 */
 
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
new file mode 100644
index 0000000000..ec8b3cec86
--- /dev/null
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#ifndef	_SYS_MEDFORD4_IMPL_H
+#define	_SYS_MEDFORD4_IMPL_H
+
+#include "efx.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_phy_power(
+	__in		efx_nic_t *enp,
+	__in		boolean_t power);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_phy_verify(
+	__in		efx_nic_t *enp);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MEDFORD4_IMPL_H */
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
new file mode 100644
index 0000000000..3e6080b4de
--- /dev/null
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#include "efx.h"
+#include "efx_impl.h"
+#include "medford4_impl.h"
+
+#if EFSYS_OPT_MEDFORD4
+	__checkReturn	efx_rc_t
+medford4_phy_power(
+	__in		efx_nic_t *enp,
+	__in		boolean_t power)
+{
+	if (power)
+		enp->en_reset_flags |= EFX_RESET_PHY;
+
+	return (0);
+}
+
+	__checkReturn	efx_rc_t
+medford4_phy_verify(
+	__in		efx_nic_t *enp)
+{
+	_NOTE(ARGUNUSED(enp))
+	return (0);
+}
+#endif	/* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build
index 02d5b2fbb9..937e3820a0 100644
--- a/drivers/common/sfc_efx/base/meson.build
+++ b/drivers/common/sfc_efx/base/meson.build
@@ -57,6 +57,7 @@ sources = [
         'hunt_nic.c',
         'medford_nic.c',
         'medford2_nic.c',
+        'medford4_phy.c',
         'rhead_ev.c',
         'rhead_intr.c',
         'rhead_nic.c',
-- 
2.39.5

[PATCH v2 27/45] common/sfc_efx/base: refactor EF10 link mode decoding helper

[Ivan Malov]

Future patches will use this change for netport MCDI support.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_impl.h | 13 +++++++++++
 drivers/common/sfc_efx/base/ef10_phy.c  | 31 ++++++++++++++++++-------
 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_impl.h b/drivers/common/sfc_efx/base/ef10_impl.h
index 3476f274ce..b872ec626c 100644
--- a/drivers/common/sfc_efx/base/ef10_impl.h
+++ b/drivers/common/sfc_efx/base/ef10_impl.h
@@ -801,6 +801,19 @@ ef10_phy_stats_update(
 
 #endif	/* EFSYS_OPT_PHY_STATS */
 
+LIBEFX_INTERNAL
+extern				void
+mcdi_phy_decode_link_mode(
+	__in			efx_nic_t *enp,
+	__in			boolean_t fd,
+	__in			boolean_t up,
+	__in			unsigned int speed,
+	__in			unsigned int fcntl,
+	__in			uint32_t fec,
+	__out			efx_link_mode_t *link_modep,
+	__out			unsigned int *fcntlp,
+	__out			efx_phy_fec_type_t *fecp);
+
 #if EFSYS_OPT_BIST
 
 LIBEFX_INTERNAL
diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index 49babdecd5..d458199c7a 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -92,10 +92,21 @@ mcdi_phy_decode_cap(
 	*maskp = mask;
 }
 
-static			void
+static				void
+mcdi_phy_decode_link_up_duplex(
+	__in			uint32_t link_flags,
+	__out			boolean_t *fdp,
+	__out			boolean_t *upp)
+{
+	*fdp = !!(link_flags & (1U << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
+	*upp = !!(link_flags & (1U << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
+}
+
+			void
 mcdi_phy_decode_link_mode(
 	__in		efx_nic_t *enp,
-	__in		uint32_t link_flags,
+	__in		boolean_t fd,
+	__in		boolean_t up,
 	__in		unsigned int speed,
 	__in		unsigned int fcntl,
 	__in		uint32_t fec,
@@ -103,11 +114,6 @@ mcdi_phy_decode_link_mode(
 	__out		unsigned int *fcntlp,
 	__out		efx_phy_fec_type_t *fecp)
 {
-	boolean_t fd = !!(link_flags &
-		    (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
-	boolean_t up = !!(link_flags &
-		    (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
-
 	_NOTE(ARGUNUSED(enp))
 
 	if (!up)
@@ -179,6 +185,8 @@ ef10_phy_link_ev(
 	unsigned int ev_fcntl;
 	unsigned int ev_speed;
 	uint32_t lp_cap_mask;
+	boolean_t fd;
+	boolean_t up;
 
 	if (ev_is_v2) {
 		link_flags = (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN);
@@ -226,7 +234,8 @@ ef10_phy_link_ev(
 		break;
 	}
 
-	mcdi_phy_decode_link_mode(enp, link_flags, speed, ev_fcntl,
+	mcdi_phy_decode_link_up_duplex(link_flags, &fd, &up);
+	mcdi_phy_decode_link_mode(enp, fd, up, speed, ev_fcntl,
 				    MC_CMD_FEC_NONE, &link_mode,
 				    &fcntl, &fec);
 	mcdi_phy_decode_cap(ev_lp_cap, &lp_cap_mask);
@@ -281,6 +290,8 @@ ef10_phy_get_link(
 	uint32_t fec;
 	EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,
 		MC_CMD_GET_LINK_OUT_V2_LEN);
+	boolean_t fd;
+	boolean_t up;
 	efx_rc_t rc;
 
 	req.emr_cmd = MC_CMD_GET_LINK;
@@ -311,7 +322,9 @@ ef10_phy_get_link(
 	else
 		fec = MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_FEC_TYPE);
 
-	mcdi_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
+	mcdi_phy_decode_link_up_duplex(MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
+				    &fd, &up);
+	mcdi_phy_decode_link_mode(enp, fd, up,
 			    MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
 			    MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
 			    fec, &elsp->epls.epls_link_mode,
-- 
2.39.5

[PATCH v2 28/45] common/sfc_efx/base: provide PHY link get method on Medford4

[Ivan Malov]

To do so, make use of new netport MCDI supported by Medford4.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_phy.c      |  8 ++
 drivers/common/sfc_efx/base/efx.h           |  4 +-
 drivers/common/sfc_efx/base/efx_impl.h      | 19 ++++
 drivers/common/sfc_efx/base/efx_np.c        | 97 ++++++++++++++++++++-
 drivers/common/sfc_efx/base/efx_phy.c       |  2 +-
 drivers/common/sfc_efx/base/medford4_impl.h | 12 +++
 drivers/common/sfc_efx/base/medford4_phy.c  | 62 +++++++++++++
 7 files changed, 201 insertions(+), 3 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index d458199c7a..8c3de273b4 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -118,6 +118,8 @@ mcdi_phy_decode_link_mode(
 
 	if (!up)
 		*link_modep = EFX_LINK_DOWN;
+	else if (speed == 200000 && fd)
+		*link_modep = EFX_LINK_200000FDX;
 	else if (speed == 100000 && fd)
 		*link_modep = EFX_LINK_100000FDX;
 	else if (speed == 50000 && fd)
@@ -160,6 +162,12 @@ mcdi_phy_decode_link_mode(
 	case MC_CMD_FEC_RS:
 		*fecp = EFX_PHY_FEC_RS;
 		break;
+	case MC_CMD_FEC_IEEE_RS_INT:
+		*fecp = EFX_PHY_FEC_IEEE_RS_INT;
+		break;
+	case MC_CMD_FEC_ETCS_RS_LL:
+		*fecp = EFX_PHY_FEC_ETCS_RS_LL;
+		break;
 	default:
 		EFSYS_PROBE1(mc_pcol_error, int, fec);
 		*fecp = EFX_PHY_FEC_NONE;
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 7ffa1f4cbd..6ca108cffe 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -4010,7 +4010,9 @@ efx_nic_set_fw_subvariant(
 typedef enum efx_phy_fec_type_e {
 	EFX_PHY_FEC_NONE = 0,
 	EFX_PHY_FEC_BASER,
-	EFX_PHY_FEC_RS
+	EFX_PHY_FEC_RS,
+	EFX_PHY_FEC_IEEE_RS_INT,
+	EFX_PHY_FEC_ETCS_RS_LL,
 } efx_phy_fec_type_t;
 
 #define EFX_PHY_CAP_FEC_BIT(_fec_bit) (1U << EFX_PHY_CAP_##_fec_bit)
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 16b7f7640d..63ff112194 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1907,7 +1907,14 @@ efx_np_detach(
 
 typedef struct efx_np_link_state_s {
 	uint32_t		enls_adv_cap_mask;
+	uint32_t		enls_lp_cap_mask;
+	efx_loopback_type_t	enls_loopback;
+	uint32_t		enls_speed;
+	uint8_t			enls_fec;
+
 	boolean_t		enls_an_supported;
+	boolean_t		enls_fd;
+	boolean_t		enls_up;
 } efx_np_link_state_t;
 
 LIBEFX_INTERNAL
@@ -1917,6 +1924,18 @@ efx_np_link_state(
 	__in		efx_np_handle_t nph,
 	__out		efx_np_link_state_t *lsp);
 
+typedef struct efx_np_mac_state_s {
+	uint32_t	enms_fcntl;
+	boolean_t	enms_up;
+} efx_np_mac_state_t;
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_mac_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_mac_state_t *msp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 1b670435db..409fe05772 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -301,7 +301,9 @@ efx_np_link_state(
 	EFX_MCDI_DECLARE_BUF(payload,
 	    MC_CMD_LINK_STATE_IN_LEN,
 	    MC_CMD_LINK_STATE_OUT_V3_LEN);
+	uint32_t status_flags;
 	efx_mcdi_req_t req;
+	uint32_t v3_flags;
 	efx_rc_t rc;
 
 	req.emr_out_length = MC_CMD_LINK_STATE_OUT_V3_LEN;
@@ -324,12 +326,43 @@ efx_np_link_state(
 		goto fail2;
 	}
 
+	status_flags = MCDI_OUT_DWORD(req, LINK_STATE_OUT_STATUS_FLAGS_LO);
+	v3_flags = MCDI_OUT_DWORD(req, LINK_STATE_OUT_V3_FLAGS);
 	memset(lsp, 0, sizeof (*lsp));
 
-	if (MCDI_OUT_DWORD(req, LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT) !=
+	if (status_flags & (1U << MC_CMD_LINK_STATUS_FLAGS_AN_ABLE) &&
+	    MCDI_OUT_DWORD(req, LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT) !=
 	    MC_CMD_AN_NONE)
 		lsp->enls_an_supported = B_TRUE;
 
+	if (v3_flags & (1U << MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN))
+		lsp->enls_fd = B_TRUE;
+
+	if (status_flags & (1U << MC_CMD_LINK_STATUS_FLAGS_LINK_UP))
+		lsp->enls_up = B_TRUE;
+
+	lsp->enls_speed = MCDI_OUT_DWORD(req, LINK_STATE_OUT_V3_LINK_SPEED);
+	lsp->enls_fec = MCDI_OUT_BYTE(req, LINK_STATE_OUT_FEC_MODE);
+
+#if EFSYS_OPT_LOOPBACK
+	switch (MCDI_OUT_BYTE(req, LINK_STATE_OUT_LOOPBACK)) {
+	case MC_CMD_LOOPBACK_V2_NONE:
+		lsp->enls_loopback = EFX_LOOPBACK_OFF;
+		break;
+	case MC_CMD_LOOPBACK_V2_AUTO:
+		lsp->enls_loopback = EFX_LOOPBACK_DATA;
+		break;
+	case MC_CMD_LOOPBACK_V2_POST_PCS:
+		lsp->enls_loopback = EFX_LOOPBACK_PCS;
+		break;
+	default:
+		rc = EINVAL;
+		goto fail3;
+	}
+#else /* ! EFSYS_OPT_LOOPBACK */
+	_NOTE(ARGUNUSED(lbp))
+#endif /* EFSYS_OPT_LOOPBACK */
+
 	if (lsp->enls_an_supported != B_FALSE)
 		lsp->enls_adv_cap_mask |= 1U << EFX_PHY_CAP_AN;
 
@@ -337,8 +370,21 @@ efx_np_link_state(
 	    MCDI_OUT2(req, const uint8_t, LINK_STATE_OUT_ADVERTISED_ABILITIES),
 	    &lsp->enls_adv_cap_mask);
 
+	if (lsp->enls_an_supported != B_FALSE)
+		lsp->enls_lp_cap_mask |= 1U << EFX_PHY_CAP_AN;
+
+	efx_np_cap_hw_data_to_sw_mask(
+	    MCDI_OUT2(req, const uint8_t,
+		    LINK_STATE_OUT_LINK_PARTNER_ABILITIES),
+	    &lsp->enls_lp_cap_mask);
+
 	return (0);
 
+#if EFSYS_OPT_LOOPBACK
+fail3:
+	EFSYS_PROBE(fail3);
+#endif /* EFSYS_OPT_LOOPBACK */
+
 fail2:
 	EFSYS_PROBE(fail2);
 
@@ -552,3 +598,52 @@ efx_np_detach(
 	if (efx_np_supported(enp) == B_FALSE)
 		return;
 }
+
+	__checkReturn	efx_rc_t
+efx_np_mac_state(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__out		efx_np_mac_state_t *msp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_MAC_STATE_IN_LEN,
+	    MC_CMD_MAC_STATE_OUT_LEN);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_MAC_STATE_OUT_LEN;
+	req.emr_in_length = MC_CMD_MAC_STATE_IN_LEN;
+	req.emr_cmd = MC_CMD_MAC_STATE;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, MAC_STATE_IN_PORT_HANDLE, nph);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_MAC_STATE_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	memset(msp, 0, sizeof (*msp));
+
+	if (MCDI_OUT_DWORD(req, MAC_STATE_OUT_MAC_FAULT_FLAGS) == 0)
+		msp->enms_up = B_TRUE;
+
+	msp->enms_fcntl = MCDI_OUT_DWORD(req, MAC_STATE_OUT_FCNTL);
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+	return (rc);
+}
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index 537865767a..0f748e32a4 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -75,7 +75,7 @@ static const efx_phy_ops_t	__efx_phy_medford4_ops = {
 	ef10_phy_reconfigure,		/* epo_reconfigure */
 	medford4_phy_verify,		/* epo_verify */
 	ef10_phy_oui_get,		/* epo_oui_get */
-	ef10_phy_link_state_get,	/* epo_link_state_get */
+	medford4_phy_link_state_get,	/* epo_link_state_get */
 #if EFSYS_OPT_PHY_STATS
 	ef10_phy_stats_update,		/* epo_stats_update */
 #endif	/* EFSYS_OPT_PHY_STATS */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index ec8b3cec86..f24c9d1e6c 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -22,6 +22,18 @@ extern	__checkReturn	efx_rc_t
 medford4_phy_verify(
 	__in		efx_nic_t *enp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_phy_get_link(
+	__in		efx_nic_t *enp,
+	__out		ef10_link_state_t *elsp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_phy_link_state_get(
+	__in			efx_nic_t *enp,
+	__out			efx_phy_link_state_t *eplsp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
index 3e6080b4de..6a61645384 100644
--- a/drivers/common/sfc_efx/base/medford4_phy.c
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -25,4 +25,66 @@ medford4_phy_verify(
 	_NOTE(ARGUNUSED(enp))
 	return (0);
 }
+
+	__checkReturn	efx_rc_t
+medford4_phy_get_link(
+	__in		efx_nic_t *enp,
+	__out		ef10_link_state_t *elsp)
+{
+	efx_np_handle_t nph = enp->en_port.ep_np_handle;
+	efx_np_link_state_t ls;
+	efx_np_mac_state_t ms;
+	uint32_t fcntl;
+	efx_rc_t rc;
+
+	rc = efx_np_link_state(enp, nph, &ls);
+	if (rc != 0)
+		goto fail1;
+
+	elsp->epls.epls_adv_cap_mask = ls.enls_adv_cap_mask;
+	elsp->epls.epls_lp_cap_mask = ls.enls_lp_cap_mask;
+	elsp->els_loopback = ls.enls_loopback;
+
+	rc = efx_np_mac_state(enp, nph, &ms);
+	if (rc != 0)
+		goto fail2;
+
+	elsp->els_mac_up = ms.enms_up;
+
+	mcdi_phy_decode_link_mode(enp, ls.enls_fd, ls.enls_up, ls.enls_speed,
+			    ms.enms_fcntl, ls.enls_fec,
+			    &elsp->epls.epls_link_mode,
+			    &elsp->epls.epls_fcntl,
+			    &elsp->epls.epls_fec);
+
+	elsp->epls.epls_ld_cap_mask = 0;
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_phy_link_state_get(
+	__in			efx_nic_t *enp,
+	__out			efx_phy_link_state_t *eplsp)
+{
+	ef10_link_state_t els;
+	efx_rc_t rc;
+
+	rc = medford4_phy_get_link(enp, &els);
+	if (rc != 0)
+		goto fail1;
+
+	*eplsp = els.epls;
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
 #endif	/* EFSYS_OPT_MEDFORD4 */
-- 
2.39.5

[PATCH v2 29/45] common/sfc_efx/base: implement PHY link control for Medford4

[Ivan Malov]

Use new MCDI to select loopback, speed, flow control and FEC.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_impl.h     |   6 +
 drivers/common/sfc_efx/base/ef10_phy.c      |   2 +-
 drivers/common/sfc_efx/base/efx_impl.h      |  11 +
 drivers/common/sfc_efx/base/efx_np.c        | 260 ++++++++++++++++++++
 drivers/common/sfc_efx/base/efx_phy.c       |   2 +-
 drivers/common/sfc_efx/base/medford4_impl.h |   5 +
 drivers/common/sfc_efx/base/medford4_phy.c  |  65 +++++
 7 files changed, 349 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_impl.h b/drivers/common/sfc_efx/base/ef10_impl.h
index b872ec626c..df4fd77833 100644
--- a/drivers/common/sfc_efx/base/ef10_impl.h
+++ b/drivers/common/sfc_efx/base/ef10_impl.h
@@ -814,6 +814,12 @@ mcdi_phy_decode_link_mode(
 	__out			unsigned int *fcntlp,
 	__out			efx_phy_fec_type_t *fecp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_mcdi_phy_set_led(
+	__in		efx_nic_t *enp,
+	__in		efx_phy_led_mode_t phy_led_mode);
+
 #if EFSYS_OPT_BIST
 
 LIBEFX_INTERNAL
diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index 8c3de273b4..114543e156 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -473,7 +473,7 @@ efx_mcdi_phy_set_link(
 	return (rc);
 }
 
-static	__checkReturn	efx_rc_t
+	__checkReturn	efx_rc_t
 efx_mcdi_phy_set_led(
 	__in		efx_nic_t *enp,
 	__in		efx_phy_led_mode_t phy_led_mode)
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 63ff112194..15cf62506e 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1936,6 +1936,17 @@ efx_np_mac_state(
 	__in		efx_np_handle_t nph,
 	__out		efx_np_mac_state_t *msp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_link_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const uint8_t *cap_mask_sup_raw,
+	__in		efx_link_mode_t loopback_link_mode,
+	__in		efx_loopback_type_t loopback_mode,
+	__in		uint32_t cap_mask_sw,
+	__in		boolean_t fcntl_an);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 409fe05772..26abc82dbf 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -647,3 +647,263 @@ efx_np_mac_state(
 
 	return (rc);
 }
+
+static					void
+efx_np_cap_mask_sw_to_hw(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__in				uint32_t mask_sw,
+	__out				uint8_t *mask_hwp)
+{
+	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
+	    hw_cap_data, hw_cap_data_nbytes) {
+		uint32_t flag_sw = 1U << hw_sw_map->encm_sw;
+
+		if ((mask_sw & flag_sw) != flag_sw)
+			continue;
+
+		mask_hwp[CAP_BYTE(hw_sw_map)] |= CAP_FLAG(hw_sw_map);
+		mask_sw &= ~(flag_sw);
+	}
+}
+
+/*
+ * Convert the given EFX PHY capability mask to the HW representation.
+ *
+ * The mapping of a capability from EFX to HW can be one to many. Use
+ * the given fraction of raw HW netport capability data to choose the
+ * first supported HW capability bit encountered for a particular EFX
+ * one and proceed with handling the next EFX bit, if any, afterwards.
+ *
+ * Do not check the input mask for leftover bits (unknown to EFX), as
+ * inputs should have been validated by efx_phy_adv_cap_set() already.
+ */
+#define	EFX_NP_CAP_MASK_SW_TO_HW(					\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
+	    _mask_sw, _mask_hwp)					\
+	efx_np_cap_mask_sw_to_hw((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN,				\
+	    (_mask_sw), (_mask_hwp))
+
+static					void
+efx_np_cap_sw_mask_to_hw_enum(
+	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
+	__in				unsigned int hw_sw_map_nentries,
+	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
+	__in				size_t hw_cap_data_nbytes,
+	__in				uint32_t mask_sw,
+	__out				boolean_t *supportedp,
+	__out_opt			uint16_t *enum_hwp)
+{
+	unsigned int sw_nflags_req = 0;
+	unsigned int sw_nflags_sup = 0;
+	uint32_t sw_check_mask = 0;
+	unsigned int i;
+
+	for (i = 0; i < hw_sw_map_nentries; ++i) {
+		uint32_t flag_sw = 1U << hw_sw_map->encm_sw;
+		unsigned int byte_idx = CAP_BYTE(hw_sw_map);
+		uint8_t flag_hw = CAP_FLAG(hw_sw_map);
+
+		if (byte_idx >= hw_cap_data_nbytes) {
+			++(hw_sw_map);
+			continue;
+		}
+
+		if ((mask_sw & flag_sw) == flag_sw) {
+			if ((sw_check_mask & flag_sw) == 0)
+				++(sw_nflags_req);
+
+			sw_check_mask |= flag_sw;
+
+			if ((hw_cap_data[byte_idx] & flag_hw) == flag_hw) {
+				mask_sw &= ~(flag_sw);
+
+				if (enum_hwp != NULL)
+					*enum_hwp = hw_sw_map->encm_hw;
+			}
+		}
+
+		++(hw_sw_map);
+	}
+
+	if (sw_check_mask != 0 && (mask_sw & sw_check_mask) == sw_check_mask) {
+		/* Failed to select the enum by at least one capability bit. */
+		*supportedp = B_FALSE;
+		return;
+	}
+
+	*supportedp = B_TRUE;
+}
+
+/*
+ * Convert (conceivably) the only EFX capability bit of the given mask to
+ * the HW enum value, provided that the capability is supported by the HW,
+ * where the latter follows from the given fraction of HW capability data.
+ */
+#define	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(					\
+	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
+	    _mask_sw, _supportedp, _enum_hwp)				\
+	efx_np_cap_sw_mask_to_hw_enum((_hw_sw_cap_map),			\
+	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
+	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
+		    MC_CMD_##_hw_cap_section),				\
+	    MC_CMD_##_hw_cap_section##_LEN, (_mask_sw),			\
+	    (_supportedp), (_enum_hwp))
+
+	__checkReturn	efx_rc_t
+efx_np_link_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const uint8_t *cap_data_raw,
+	__in		efx_link_mode_t loopback_link_mode,
+	__in		efx_loopback_type_t loopback_mode,
+	__in		uint32_t cap_mask_sw,
+	__in		boolean_t fcntl_an)
+{
+	uint32_t flags = 1U << MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ;
+	uint8_t loopback = MC_CMD_LOOPBACK_V2_NONE;
+	uint16_t link_tech = MC_CMD_ETH_TECH_NONE;
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_LINK_CTRL_IN_LEN,
+	    MC_CMD_LINK_CTRL_OUT_LEN);
+	uint8_t *cap_mask_hw_pausep;
+	uint8_t *cap_mask_hw_techp;
+	uint16_t cap_enum_hw;
+	boolean_t supported;
+	efx_mcdi_req_t req;
+	boolean_t phy_an;
+	efx_rc_t rc;
+	uint8_t fec;
+
+	req.emr_out_length = MC_CMD_LINK_CTRL_OUT_LEN;
+	req.emr_in_length = MC_CMD_LINK_CTRL_IN_LEN;
+	req.emr_cmd = MC_CMD_LINK_CTRL;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, LINK_CTRL_IN_PORT_HANDLE, nph);
+
+	cap_mask_hw_pausep = MCDI_IN2(req, uint8_t,
+	    LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK);
+
+	cap_mask_hw_techp = MCDI_IN2(req, uint8_t,
+	    LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK);
+
+	if (loopback_mode != EFX_LOOPBACK_OFF) {
+#if EFSYS_OPT_LOOPBACK
+		uint16_t cap_enum_sw;
+
+		switch (loopback_mode) {
+		case EFX_LOOPBACK_DATA:
+			loopback = MC_CMD_LOOPBACK_V2_AUTO;
+			break;
+		case EFX_LOOPBACK_PCS:
+			loopback = MC_CMD_LOOPBACK_V2_POST_PCS;
+			break;
+		default:
+			rc = ENOTSUP;
+			goto fail1;
+		}
+
+		rc = efx_np_sw_link_mode_to_cap(loopback_link_mode,
+					    &cap_enum_sw);
+		if (rc != 0)
+			goto fail2;
+
+		EFX_NP_CAP_ENUM_SW_TO_HW(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_enum_sw,
+		    &supported, &link_tech);
+
+		if (supported == B_FALSE) {
+			rc = ENOTSUP;
+			goto fail3;
+		}
+#else /* ! EFSYS_OPT_LOOPBACK */
+		rc = ENOTSUP;
+		goto fail1;
+#endif /* EFSYS_OPT_LOOPBACK */
+	} else if (cap_mask_sw & (1U << EFX_PHY_CAP_AN)) {
+		EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    cap_mask_hw_techp);
+
+		if (fcntl_an != B_FALSE) {
+			EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_pause,
+			    ETH_AN_FIELDS_PAUSE_MASK, cap_data_raw, cap_mask_sw,
+			    cap_mask_hw_pausep);
+		}
+
+		flags |= 1U << MC_CMD_LINK_FLAGS_AUTONEG_EN;
+		link_tech = MC_CMD_ETH_TECH_AUTO;
+	} else {
+		EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_tech,
+		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    &supported, &link_tech);
+
+		if (supported == B_FALSE) {
+			rc = ENOTSUP;
+			goto fail4;
+		}
+	}
+
+	/* The software mask may have no requested FEC bits. Default is NONE. */
+	cap_enum_hw = MC_CMD_FEC_NONE;
+
+	/*
+	 * Compared to older EF10 interface, in netport MCDI, FEC mode is a
+	 * single enum choice. For compatibility, do not enforce only single
+	 * requested FEC bit in the original mask.
+	 *
+	 * No requested FEC bits in the original mask gives supported=TRUE.
+	 */
+	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_fec_req,
+	    ETH_AN_FIELDS_FEC_REQ, cap_data_raw, cap_mask_sw,
+	    &supported, &cap_enum_hw);
+
+	if ((cap_mask_sw & EFX_PHY_CAP_FEC_MASK) != 0 && supported == B_FALSE) {
+		rc = ENOTSUP;
+		goto fail5;
+	}
+
+	EFSYS_ASSERT(cap_enum_hw <= UINT8_MAX);
+	fec = cap_enum_hw;
+
+	MCDI_IN_SET_WORD(req, LINK_CTRL_IN_LINK_TECHNOLOGY, link_tech);
+	MCDI_IN_SET_DWORD(req, LINK_CTRL_IN_CONTROL_FLAGS, flags);
+	MCDI_IN_SET_BYTE(req, LINK_CTRL_IN_LOOPBACK, loopback);
+	MCDI_IN_SET_BYTE(req, LINK_CTRL_IN_FEC_MODE, fec);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail6;
+	}
+
+	return (0);
+
+fail6:
+	EFSYS_PROBE(fail6);
+
+fail5:
+	EFSYS_PROBE(fail5);
+
+fail4:
+	EFSYS_PROBE(fail4);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index 0f748e32a4..e3b9d20d59 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -72,7 +72,7 @@ static const efx_phy_ops_t	__efx_phy_rhead_ops = {
 static const efx_phy_ops_t	__efx_phy_medford4_ops = {
 	medford4_phy_power,		/* epo_power */
 	NULL,				/* epo_reset */
-	ef10_phy_reconfigure,		/* epo_reconfigure */
+	medford4_phy_reconfigure,	/* epo_reconfigure */
 	medford4_phy_verify,		/* epo_verify */
 	ef10_phy_oui_get,		/* epo_oui_get */
 	medford4_phy_link_state_get,	/* epo_link_state_get */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index f24c9d1e6c..795fd45bd4 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -34,6 +34,11 @@ medford4_phy_link_state_get(
 	__in			efx_nic_t *enp,
 	__out			efx_phy_link_state_t *eplsp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_phy_reconfigure(
+	__in			efx_nic_t *enp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
index 6a61645384..cc4e77587b 100644
--- a/drivers/common/sfc_efx/base/medford4_phy.c
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -83,6 +83,71 @@ medford4_phy_link_state_get(
 	*eplsp = els.epls;
 	return (0);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_phy_reconfigure(
+	__in			efx_nic_t *enp)
+{
+	efx_link_mode_t loopback_link_mode;
+	efx_port_t *epp = &(enp->en_port);
+	efx_loopback_type_t loopback;
+	efx_phy_led_mode_t led;
+	boolean_t supported;
+	efx_rc_t rc;
+
+	rc = efx_mcdi_link_control_supported(enp, &supported);
+	if (rc != 0)
+		goto fail1;
+
+	if (supported == B_FALSE)
+		goto exit;
+
+#if EFSYS_OPT_LOOPBACK
+	loopback_link_mode = epp->ep_loopback_link_mode;
+	loopback = epp->ep_loopback_type;
+#else /* ! EFSYS_OPT_LOOPBACK */
+	loopback_link_mode = EFX_LINK_UNKNOWN;
+	loopback = EFX_LOOPBACK_OFF;
+#endif /* EFSYS_OPT_LOOPBACK */
+
+	rc = efx_np_link_ctrl(enp, epp->ep_np_handle, epp->ep_np_cap_data_raw,
+		    loopback_link_mode, loopback, epp->ep_adv_cap_mask,
+		    epp->ep_fcntl_autoneg);
+	if (rc != 0)
+		goto fail2;
+
+#if EFSYS_OPT_PHY_LED_CONTROL
+	led = epp->ep_phy_led_mode;
+#else /* ! EFSYS_OPT_PHY_LED_CONTROL */
+	led = EFX_PHY_LED_DEFAULT;
+#endif /* EFSYS_OPT_PHY_LED_CONTROL */
+
+	rc = efx_mcdi_phy_set_led(enp, led);
+	if (rc != 0) {
+		/*
+		 * If LED control is not supported by firmware, we can
+		 * silently ignore default mode set failure
+		 * (see FWRIVERHD-198).
+		 */
+		if (rc == EOPNOTSUPP && led == EFX_PHY_LED_DEFAULT)
+			goto exit;
+
+		goto fail3;
+	}
+
+exit:
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
-- 
2.39.5

[PATCH v2 30/45] common/sfc_efx/base: introduce Medford4 stub for MAC methods

[Ivan Malov]

Provide only a small subset of methods for now. Next patches
will augment the file with more, based on newer netport MCDI.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_mac.c       | 32 +++++++++++-
 drivers/common/sfc_efx/base/medford4_impl.h | 12 +++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 54 +++++++++++++++++++++
 drivers/common/sfc_efx/base/meson.build     |  1 +
 4 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c

diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index a2cbf02b46..dde0e5ab87 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -89,6 +89,31 @@ static const efx_mac_ops_t	__efx_mac_rhead_ops = {
 };
 #endif	/* EFSYS_OPT_RIVERHEAD */
 
+#if EFSYS_OPT_MEDFORD4
+static const efx_mac_ops_t	__efx_mac_medford4_ops = {
+	medford4_mac_poll,			/* emo_poll */
+	medford4_mac_up,			/* emo_up */
+	ef10_mac_addr_set,			/* emo_addr_set */
+	ef10_mac_pdu_set,			/* emo_pdu_set */
+	ef10_mac_pdu_get,			/* emo_pdu_get */
+	ef10_mac_reconfigure,			/* emo_reconfigure */
+	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
+	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
+	ef10_mac_filter_default_rxq_clear,
+					/* emo_filter_default_rxq_clear */
+#if EFSYS_OPT_LOOPBACK
+	ef10_mac_loopback_set,			/* emo_loopback_set */
+#endif	/* EFSYS_OPT_LOOPBACK */
+#if EFSYS_OPT_MAC_STATS
+	ef10_mac_stats_get_mask,		/* emo_stats_get_mask */
+	efx_mcdi_mac_stats_clear,		/* emo_stats_clear */
+	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
+	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
+	ef10_mac_stats_update			/* emo_stats_update */
+#endif	/* EFSYS_OPT_MAC_STATS */
+};
+#endif /* EFSYS_OPT_MEDFORD4 */
+
 	__checkReturn			efx_rc_t
 efx_mac_pdu_set(
 	__in				efx_nic_t *enp,
@@ -271,6 +296,11 @@ efx_mac_drain(
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 	EFSYS_ASSERT(emop != NULL);
 
+	if (efx_np_supported(enp) != B_FALSE) {
+		/* Only pre-Medford4 boards have supported MAC drain control. */
+		return (0);
+	}
+
 	if (epp->ep_mac_drain == enabled)
 		return (0);
 
@@ -955,7 +985,7 @@ efx_mac_select(
 
 #if EFSYS_OPT_MEDFORD4
 	case EFX_FAMILY_MEDFORD4:
-		emop = &__efx_mac_ef10_ops;
+		emop = &__efx_mac_medford4_ops;
 		type = EFX_MAC_MEDFORD4;
 		break;
 #endif /* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 795fd45bd4..6aa065c730 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -39,6 +39,18 @@ extern	__checkReturn		efx_rc_t
 medford4_phy_reconfigure(
 	__in			efx_nic_t *enp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_poll(
+	__in		efx_nic_t *enp,
+	__out		efx_link_mode_t *link_modep);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_up(
+	__in		efx_nic_t *enp,
+	__out		boolean_t *mac_upp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
new file mode 100644
index 0000000000..57ddbecfaa
--- /dev/null
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2025 Advanced Micro Devices, Inc.
+ */
+#include "efx.h"
+#include "efx_impl.h"
+#include "medford4_impl.h"
+
+#if EFSYS_OPT_MEDFORD4
+	__checkReturn	efx_rc_t
+medford4_mac_poll(
+	__in		efx_nic_t *enp,
+	__out		efx_link_mode_t *link_modep)
+{
+	efx_port_t *epp = &(enp->en_port);
+	ef10_link_state_t els;
+	efx_rc_t rc;
+
+	rc = medford4_phy_get_link(enp, &els);
+	if (rc != 0)
+		goto fail1;
+
+	epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
+	epp->ep_fcntl = els.epls.epls_fcntl;
+
+	*link_modep = els.epls.epls_link_mode;
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	*link_modep = EFX_LINK_UNKNOWN;
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+medford4_mac_up(
+	__in		efx_nic_t *enp,
+	__out		boolean_t *mac_upp)
+{
+	ef10_link_state_t els;
+	efx_rc_t rc;
+
+	rc = medford4_phy_get_link(enp, &els);
+	if (rc != 0)
+		goto fail1;
+
+	*mac_upp = els.els_mac_up;
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build
index 937e3820a0..f18011e186 100644
--- a/drivers/common/sfc_efx/base/meson.build
+++ b/drivers/common/sfc_efx/base/meson.build
@@ -57,6 +57,7 @@ sources = [
         'hunt_nic.c',
         'medford_nic.c',
         'medford2_nic.c',
+        'medford4_mac.c',
         'medford4_phy.c',
         'rhead_ev.c',
         'rhead_intr.c',
-- 
2.39.5

[PATCH v2 31/45] common/sfc_efx/base: add MAC reconfigure method for Medford4

[Ivan Malov]

That leverages MAC control functionality of new netport MCDI.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      | 13 ++++
 drivers/common/sfc_efx/base/efx_mac.c       |  2 +-
 drivers/common/sfc_efx/base/efx_np.c        | 73 +++++++++++++++++++++
 drivers/common/sfc_efx/base/medford4_impl.h |  5 ++
 drivers/common/sfc_efx/base/medford4_mac.c  | 38 +++++++++++
 5 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 15cf62506e..ac1cd5292b 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1947,6 +1947,19 @@ efx_np_link_ctrl(
 	__in		uint32_t cap_mask_sw,
 	__in		boolean_t fcntl_an);
 
+typedef struct efx_np_mac_ctrl_s {
+	boolean_t	enmc_fcntl_autoneg;
+	boolean_t	enmc_include_fcs;
+	uint32_t	enmc_fcntl;
+} efx_np_mac_ctrl_t;
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_mac_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const efx_np_mac_ctrl_t *mc);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index dde0e5ab87..3c29db0016 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -96,7 +96,7 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 	ef10_mac_addr_set,			/* emo_addr_set */
 	ef10_mac_pdu_set,			/* emo_pdu_set */
 	ef10_mac_pdu_get,			/* emo_pdu_get */
-	ef10_mac_reconfigure,			/* emo_reconfigure */
+	medford4_mac_reconfigure,		/* emo_reconfigure */
 	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
 	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
 	ef10_mac_filter_default_rxq_clear,
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 26abc82dbf..aa5bb76af7 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -903,6 +903,79 @@ efx_np_link_ctrl(
 fail2:
 	EFSYS_PROBE(fail2);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+efx_np_mac_ctrl(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		const efx_np_mac_ctrl_t *mc)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_MAC_CTRL_IN_LEN,
+	    MC_CMD_MAC_CTRL_OUT_LEN);
+	efx_mcdi_req_t req;
+	uint32_t flags = 0;
+	uint32_t cfg = 0;
+	uint32_t fcntl;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_MAC_CTRL_OUT_LEN;
+	req.emr_in_length = MC_CMD_MAC_CTRL_IN_LEN;
+	req.emr_cmd = MC_CMD_MAC_CTRL;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_PORT_HANDLE, nph);
+
+	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS;
+	if (mc->enmc_include_fcs != B_FALSE)
+		flags |= 1U << MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS;
+
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FLAGS, flags);
+
+	if (mc->enmc_fcntl_autoneg != B_FALSE) {
+		fcntl = MC_CMD_FCNTL_AUTO;
+	} else {
+		switch (mc->enmc_fcntl) {
+		case 0:
+			fcntl = MC_CMD_FCNTL_OFF;
+			break;
+		case EFX_FCNTL_RESPOND:
+			fcntl = MC_CMD_FCNTL_RESPOND;
+			break;
+		case EFX_FCNTL_GENERATE:
+			fcntl = MC_CMD_FCNTL_GENERATE;
+			break;
+		case EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE:
+			fcntl = MC_CMD_FCNTL_BIDIR;
+			break;
+		default:
+			rc = EINVAL;
+			goto fail1;
+		}
+	}
+
+	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL;
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FCNTL, fcntl);
+
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_V2_CONTROL_FLAGS, cfg);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail2;
+	}
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 6aa065c730..8b232c516a 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -51,6 +51,11 @@ medford4_mac_up(
 	__in		efx_nic_t *enp,
 	__out		boolean_t *mac_upp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_reconfigure(
+	__in			efx_nic_t *enp);
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index 57ddbecfaa..ade4379a19 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -47,6 +47,44 @@ medford4_mac_up(
 	*mac_upp = els.els_mac_up;
 	return (0);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_mac_reconfigure(
+	__in			efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_np_mac_ctrl_t mc = {0};
+	efx_rc_t rc;
+
+	mc.enmc_fcntl_autoneg = epp->ep_fcntl_autoneg;
+	mc.enmc_include_fcs = epp->ep_include_fcs;
+	mc.enmc_fcntl = epp->ep_fcntl;
+
+	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
+	if (rc != 0)
+		goto fail1;
+
+	/*
+	 * Apply the filters for the MAC configuration. If the NIC isn't ready
+	 * to accept filters, this may return success without setting anything.
+	 */
+	rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
+				    epp->ep_all_unicst, epp->ep_mulcst,
+				    epp->ep_all_mulcst, epp->ep_brdcst,
+				    epp->ep_mulcst_addr_list,
+				    epp->ep_mulcst_addr_count);
+	if (rc != 0)
+		goto fail2;
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
-- 
2.39.5

[PATCH v2 32/45] common/sfc_efx/base: fill in software LUT for MAC statistics

[Ivan Malov]

To support MAC statistics, it is required to fill in a table
which will be used by EFX to get DMA field IDs (offsets into
the DMA buffer where MC FW uploads the data) by software IDs.

Fill in the lookup table by parsing HW statistic descriptors.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h |   8 +
 drivers/common/sfc_efx/base/efx_np.c   | 279 +++++++++++++++++++++++++
 2 files changed, 287 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index ac1cd5292b..aafb2bf998 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -341,6 +341,12 @@ typedef struct efx_virtio_ops_s {
 
 typedef uint32_t efx_np_handle_t;
 
+typedef struct efx_np_stat_s {
+	uint32_t	ens_hw_id;
+	uint16_t	ens_dma_fld;
+	boolean_t	ens_valid;
+} efx_np_stat_t;
+
 typedef struct efx_port_s {
 	efx_mac_type_t		ep_mac_type;
 	uint32_t		ep_phy_type;
@@ -388,6 +394,8 @@ typedef struct efx_port_s {
 	efx_np_handle_t		ep_np_handle;
 	efx_qword_t		ep_np_loopback_cap_mask;
 	uint8_t			ep_np_cap_data_raw[MC_CMD_ETH_AN_FIELDS_LEN];
+	/* Lookup table providing DMA buffer field IDs by EFX statistic IDs. */
+	efx_np_stat_t		ep_np_mac_stat_lut[EFX_MAC_NSTATS];
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index aa5bb76af7..b2a1d56f9d 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -526,6 +526,274 @@ efx_np_assign_loopback_props(
 }
 #endif /* EFSYS_OPT_LOOPBACK */
 
+#if EFSYS_OPT_MAC_STATS
+/* HW statistic IDs, as per MC_CMD_MAC_STATISTICS_DESCRIPTOR format. */
+#define	EFX_NP_HW_STAT_ID(_src, _idx)					\
+	(((MC_CMD_STAT_ID_##_src) << MC_CMD_STAT_ID_SOURCE_ID_LBN) |	\
+	    ((uint32_t)(MC_CMD_STAT_ID_##_idx) <<			\
+		    MC_CMD_STAT_ID_MAC_STAT_ID_LBN))
+
+/*
+ * Mapping between EFX statistic IDs (array indices) and their HW counterparts.
+ *
+ * This is used in conjunction with HW statistic descriptors bearing DMA field
+ * IDs (offsets into the DMA buffer) to provide a SW lookup table for readings.
+ *
+ * From the HW perspective, statistics come from MAC and PHY, hence two macros.
+ */
+static const efx_np_stat_t efx_np_mac_stat_map[] = {
+#define	EFX_NP_STAT_MAC(_hw, _sw)				\
+	[EFX_MAC_##_sw] = {					\
+		.ens_hw_id = EFX_NP_HW_STAT_ID(MAC, _hw),	\
+		.ens_valid = B_TRUE,				\
+	}
+
+	EFX_NP_STAT_MAC(TX_PKTS, TX_PKTS),
+	EFX_NP_STAT_MAC(TX_PAUSE_PKTS, TX_PAUSE_PKTS),
+	EFX_NP_STAT_MAC(TX_UNICAST_PKTS, TX_UNICST_PKTS),
+	EFX_NP_STAT_MAC(TX_MULTICAST_PKTS, TX_MULTICST_PKTS),
+	EFX_NP_STAT_MAC(TX_BROADCAST_PKTS, TX_BRDCST_PKTS),
+	EFX_NP_STAT_MAC(TX_BYTES, TX_OCTETS),
+	EFX_NP_STAT_MAC(TX_64_PKTS, TX_LE_64_PKTS),
+	EFX_NP_STAT_MAC(TX_65_TO_127_PKTS, TX_65_TO_127_PKTS),
+	EFX_NP_STAT_MAC(TX_128_TO_255_PKTS, TX_128_TO_255_PKTS),
+	EFX_NP_STAT_MAC(TX_256_TO_511_PKTS, TX_256_TO_511_PKTS),
+	EFX_NP_STAT_MAC(TX_512_TO_1023_PKTS, TX_512_TO_1023_PKTS),
+	EFX_NP_STAT_MAC(TX_1024_TO_15XX_PKTS, TX_1024_TO_15XX_PKTS),
+	EFX_NP_STAT_MAC(TX_15XX_TO_JUMBO_PKTS, TX_GE_15XX_PKTS),
+	EFX_NP_STAT_MAC(RX_PKTS, RX_PKTS),
+	EFX_NP_STAT_MAC(RX_PAUSE_PKTS, RX_PAUSE_PKTS),
+	EFX_NP_STAT_MAC(RX_UNICAST_PKTS, RX_UNICST_PKTS),
+	EFX_NP_STAT_MAC(RX_MULTICAST_PKTS, RX_MULTICST_PKTS),
+	EFX_NP_STAT_MAC(RX_BROADCAST_PKTS, RX_BRDCST_PKTS),
+	EFX_NP_STAT_MAC(RX_BYTES, RX_OCTETS),
+	EFX_NP_STAT_MAC(RX_64_PKTS, RX_LE_64_PKTS),
+	EFX_NP_STAT_MAC(RX_65_TO_127_PKTS, RX_65_TO_127_PKTS),
+	EFX_NP_STAT_MAC(RX_128_TO_255_PKTS, RX_128_TO_255_PKTS),
+	EFX_NP_STAT_MAC(RX_256_TO_511_PKTS, RX_256_TO_511_PKTS),
+	EFX_NP_STAT_MAC(RX_512_TO_1023_PKTS, RX_512_TO_1023_PKTS),
+	EFX_NP_STAT_MAC(RX_1024_TO_15XX_PKTS, RX_1024_TO_15XX_PKTS),
+	EFX_NP_STAT_MAC(RX_15XX_TO_JUMBO_PKTS, RX_GE_15XX_PKTS),
+	EFX_NP_STAT_MAC(RX_BAD_FCS_PKTS, RX_FCS_ERRORS),
+	EFX_NP_STAT_MAC(RX_SYMBOL_ERROR_PKTS, RX_SYMBOL_ERRORS),
+	EFX_NP_STAT_MAC(RX_ALIGN_ERROR_PKTS, RX_ALIGN_ERRORS),
+	EFX_NP_STAT_MAC(RX_INTERNAL_ERROR_PKTS, RX_INTERNAL_ERRORS),
+	EFX_NP_STAT_MAC(RX_JABBER_PKTS, RX_JABBER_PKTS),
+	EFX_NP_STAT_MAC(RX_NODESC_DROPS, RX_NODESC_DROP_CNT),
+	EFX_NP_STAT_MAC(RX_MATCH_FAULT, RX_MATCH_FAULT),
+
+#undef EFX_NP_STAT_MAC
+
+#define	EFX_NP_STAT_PHY(_hw, _sw)				\
+	[EFX_MAC_##_sw] = {					\
+		.ens_hw_id = EFX_NP_HW_STAT_ID(PHY, _hw),	\
+		.ens_valid = B_TRUE,				\
+	}
+
+	EFX_NP_STAT_PHY(FEC_UNCORRECTED_ERRORS, FEC_UNCORRECTED_ERRORS),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_ERRORS, FEC_CORRECTED_ERRORS),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE0,
+	    FEC_CORRECTED_SYMBOLS_LANE0),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE1,
+	    FEC_CORRECTED_SYMBOLS_LANE1),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE2,
+	    FEC_CORRECTED_SYMBOLS_LANE2),
+	EFX_NP_STAT_PHY(FEC_CORRECTED_SYMBOLS_LANE3,
+	    FEC_CORRECTED_SYMBOLS_LANE3),
+
+#undef EFX_NP_STAT_PHY
+};
+#undef EFX_NP_HW_STAT_ID
+
+/* See efx_np_stats_describe() below. */
+static					void
+efx_np_stat_describe(
+	__in				uint8_t *hw_entry_buf,
+	__in				unsigned int lut_nentries,
+	__out_ecount_opt(lut_nentries)	efx_np_stat_t *lut)
+{
+	const efx_np_stat_t *map;
+	efx_mac_stat_t sw_id;
+	uint32_t hw_id;
+
+	hw_id = MCDI_STRUCT_DWORD(hw_entry_buf, MC_CMD_STAT_DESC_STAT_ID);
+
+	for (sw_id = 0; sw_id < EFX_ARRAY_SIZE(efx_np_mac_stat_map); ++sw_id) {
+		map = &efx_np_mac_stat_map[sw_id];
+
+		if (map->ens_valid != B_FALSE && map->ens_hw_id == hw_id)
+			goto found;
+	}
+
+	/* The statistic is unknown to EFX. */
+	return;
+
+found:
+	if (sw_id >= lut_nentries) {
+		/*
+		 * Static mapping size and the size of lookup
+		 * table are out-of-sync. Should never happen.
+		 */
+		return;
+	}
+
+	lut[sw_id].ens_dma_fld =
+	    MCDI_STRUCT_WORD(hw_entry_buf, MC_CMD_STAT_DESC_STAT_INDEX);
+	lut[sw_id].ens_valid = B_TRUE;
+	lut[sw_id].ens_hw_id = hw_id;
+}
+
+/*
+ * Get a fraction of statistic descriptors from the running FW, starting from
+ * the given HW ID offset, and fill DMA buffer field IDs in the corresponding
+ * entries of the software lookup table that will be used to get the readings.
+ */
+static	__checkReturn			efx_rc_t
+efx_np_stats_describe(
+	__in				efx_nic_t *enp,
+	__in				efx_np_handle_t nph,
+	__in				uint32_t req_ofst,
+	__in				unsigned int lut_nentries,
+	__out_ecount_opt(lut_nentries)	efx_np_stat_t *lut,
+	__out_opt			uint32_t *nprocessedp,
+	__out_opt			uint32_t *nstats_maxp)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN,
+	    MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2);
+	efx_port_t *epp = &(enp->en_port);
+	uint32_t nprocessed;
+	efx_mcdi_req_t req;
+	uint8_t *entries;
+	uint32_t stride;
+	unsigned int i;
+	size_t out_sz;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2;
+	req.emr_in_length = MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN;
+	req.emr_cmd = MC_CMD_MAC_STATISTICS_DESCRIPTOR;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE, nph);
+	MCDI_IN_SET_DWORD(req, MAC_STATISTICS_DESCRIPTOR_IN_OFFSET, req_ofst);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	out_sz = req.emr_out_length_used;
+	if (out_sz < MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMIN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (nstats_maxp != NULL) {
+		*nstats_maxp = MCDI_OUT_DWORD(req,
+		    MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE) /
+		    sizeof (efx_qword_t);
+	}
+
+	if (lut_nentries == 0 || lut == NULL || nprocessedp == NULL)
+		return (0);
+
+	stride = MCDI_OUT_DWORD(req, MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE);
+	nprocessed = MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(out_sz);
+	if (nprocessed == 0) {
+		rc = EMSGSIZE;
+		goto fail3;
+	}
+
+	entries = MCDI_OUT2(req, uint8_t,
+	    MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES);
+
+	for (i = 0; i < nprocessed; ++i)
+		efx_np_stat_describe(entries + i * stride, lut_nentries, lut);
+
+	*nprocessedp = nprocessed;
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+static	__checkReturn	efx_rc_t
+efx_np_stats_assign(
+	__in		efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+	unsigned int lut_nentries;
+	uint32_t nprocessed = 0;
+	efx_mac_stat_t sw_id;
+	efx_rc_t rc;
+
+	memset(epp->ep_np_mac_stat_lut, 0, sizeof (epp->ep_np_mac_stat_lut));
+	lut_nentries = EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut);
+
+	/*
+	 * First get encp->enc_mac_stats_nstats from the firmware.
+	 *
+	 * Do not limit encp->enc_mac_stats_nstats by the size of
+	 * epp->ep_np_mac_stat_lut, because the former is used to
+	 * allocate DMA buffer by client drivers, which must have
+	 * its size match expectations of the running MC firmware.
+	 */
+	rc = efx_np_stats_describe(enp, epp->ep_np_handle, 0, 0, NULL,
+			    NULL, &encp->enc_mac_stats_nstats);
+	if (rc != 0)
+		goto fail1;
+
+	/* Then process the actual descriptor data. */
+	while (nprocessed < encp->enc_mac_stats_nstats) {
+		uint32_t batch;
+
+		rc = efx_np_stats_describe(enp, epp->ep_np_handle, nprocessed,
+		    lut_nentries, epp->ep_np_mac_stat_lut, &batch, NULL);
+		if (rc != 0)
+			goto fail2;
+
+		nprocessed += batch;
+
+		if (batch == 0) {
+			/* Failed to supply all descriptors. */
+			rc = EMSGSIZE;
+			goto fail3;
+		}
+	}
+
+	sw_id = EFX_MAC_FEC_UNCORRECTED_ERRORS;
+	if (epp->ep_np_mac_stat_lut[sw_id].ens_valid == B_FALSE)
+		encp->enc_fec_counters = B_FALSE;
+	else
+		encp->enc_fec_counters = B_TRUE;
+
+	encp->enc_hlb_counters = B_FALSE;
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MAC_STATS */
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
@@ -578,8 +846,19 @@ efx_np_attach(
 	efx_np_assign_loopback_props(enp);
 #endif /* EFSYS_OPT_LOOPBACK */
 
+#if EFSYS_OPT_MAC_STATS
+	rc = efx_np_stats_assign(enp);
+	if (rc != 0)
+		goto fail4;
+#endif /* EFSYS_OPT_MAC_STATS */
+
 	return (0);
 
+#if EFSYS_OPT_MAC_STATS
+fail4:
+	EFSYS_PROBE(fail4);
+#endif /* EFSYS_OPT_MAC_STATS */
+
 fail3:
 	EFSYS_PROBE(fail3);
 
-- 
2.39.5

[PATCH v2 33/45] common/sfc_efx/base: fill in MAC statistics mask on Medford4

[Ivan Malov]

Let client drivers know which MAC statistics can be accessed.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_mac.c       |  2 +-
 drivers/common/sfc_efx/base/medford4_impl.h |  9 ++++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 31 +++++++++++++++++++++
 3 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 3c29db0016..6abe2046e8 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -105,7 +105,7 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 	ef10_mac_loopback_set,			/* emo_loopback_set */
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_MAC_STATS
-	ef10_mac_stats_get_mask,		/* emo_stats_get_mask */
+	medford4_mac_stats_get_mask,		/* emo_stats_get_mask */
 	efx_mcdi_mac_stats_clear,		/* emo_stats_clear */
 	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
 	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 8b232c516a..2fbf1495d1 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -56,6 +56,15 @@ extern	__checkReturn		efx_rc_t
 medford4_mac_reconfigure(
 	__in			efx_nic_t *enp);
 
+#if EFSYS_OPT_MAC_STATS
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_get_mask(
+	__in			efx_nic_t *enp,
+	__inout_bcount(sz)	uint32_t *maskp,
+	__in			size_t sz);
+#endif /* EFSYS_OPT_MAC_STATS */
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index ade4379a19..23c59f18ed 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -89,4 +89,35 @@ medford4_mac_reconfigure(
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
 }
+
+#if EFSYS_OPT_MAC_STATS
+	__checkReturn		efx_rc_t
+medford4_mac_stats_get_mask(
+	__in			efx_nic_t *enp,
+	__inout_bcount(sz)	uint32_t *maskp,
+	__in			size_t sz)
+{
+	efx_port_t *epp = &(enp->en_port);
+	unsigned int i;
+	efx_rc_t rc;
+
+	for (i = 0; i < EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut); ++i) {
+		const struct efx_mac_stats_range rng[] = { { i, i } };
+
+		if (epp->ep_np_mac_stat_lut[i].ens_valid == B_FALSE)
+			continue;
+
+		rc = efx_mac_stats_mask_add_ranges(maskp, sz, rng, 1);
+		if (rc != 0)
+			goto fail1;
+	}
+
+	/* TODO: care about VADAPTOR statistics when VF support arrives */
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MAC_STATS */
 #endif /* EFSYS_OPT_MEDFORD4 */
-- 
2.39.5

[PATCH v2 34/45] common/sfc_efx/base: support MAC statistics on Medford4 NICs

[Ivan Malov]

Supply Medford4-specific methods to clear, upload and update
MAC statistics, as well as the method to toggle periodic DMA
updates. All of these leverage the same netport MCDI command.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      |  11 ++
 drivers/common/sfc_efx/base/efx_mac.c       |   6 +-
 drivers/common/sfc_efx/base/efx_mcdi.c      |  12 +-
 drivers/common/sfc_efx/base/efx_np.c        |  88 +++++++++++++++
 drivers/common/sfc_efx/base/medford4_impl.h |  22 ++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 119 ++++++++++++++++++++
 6 files changed, 253 insertions(+), 5 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index aafb2bf998..7dbad601ff 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1968,6 +1968,17 @@ efx_np_mac_ctrl(
 	__in		efx_np_handle_t nph,
 	__in		const efx_np_mac_ctrl_t *mc);
 
+#if EFSYS_OPT_MAC_STATS
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+efx_np_mac_stats(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		efx_stats_action_t action,
+	__in_opt	const efsys_mem_t *esmp,
+	__in		uint16_t period_ms);
+#endif /* EFSYS_OPT_MAC_STATS */
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 6abe2046e8..92585517c0 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -107,9 +107,9 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 #if EFSYS_OPT_MAC_STATS
 	medford4_mac_stats_get_mask,		/* emo_stats_get_mask */
 	efx_mcdi_mac_stats_clear,		/* emo_stats_clear */
-	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
-	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
-	ef10_mac_stats_update			/* emo_stats_update */
+	medford4_mac_stats_upload,		/* emo_stats_upload */
+	medford4_mac_stats_periodic,		/* emo_stats_periodic */
+	medford4_mac_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MAC_STATS */
 };
 #endif /* EFSYS_OPT_MEDFORD4 */
diff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c
index 0bd56dd84d..20051c7da9 100644
--- a/drivers/common/sfc_efx/base/efx_mcdi.c
+++ b/drivers/common/sfc_efx/base/efx_mcdi.c
@@ -2244,10 +2244,18 @@ efx_mcdi_mac_stats(
 efx_mcdi_mac_stats_clear(
 	__in		efx_nic_t *enp)
 {
+	efx_port_t *epp = &(enp->en_port);
 	efx_rc_t rc;
 
-	if ((rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL,
-			EFX_STATS_CLEAR, 0)) != 0)
+	if (efx_np_supported(enp) != B_FALSE) {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_CLEAR, NULL, 0);
+	} else {
+		rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL,
+				EFX_STATS_CLEAR, 0);
+	}
+
+	if (rc != 0)
 		goto fail1;
 
 	return (0);
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index b2a1d56f9d..d54174332e 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -1259,3 +1259,91 @@ efx_np_mac_ctrl(
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
 }
+
+#if EFSYS_OPT_MAC_STATS
+	__checkReturn	efx_rc_t
+efx_np_mac_stats(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		efx_stats_action_t action,
+	__in_opt	const efsys_mem_t *esmp,
+	__in		uint16_t period_ms)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_GET_NETPORT_STATISTICS_IN_LEN,
+	    MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN);
+	boolean_t enable = (action == EFX_STATS_ENABLE_NOEVENTS);
+	boolean_t events = (action == EFX_STATS_ENABLE_EVENTS);
+	boolean_t disable = (action == EFX_STATS_DISABLE);
+	boolean_t upload = (action == EFX_STATS_UPLOAD);
+	boolean_t clear = (action == EFX_STATS_CLEAR);
+	efx_mcdi_req_t req;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN;
+	req.emr_in_length = MC_CMD_GET_NETPORT_STATISTICS_IN_LEN;
+	req.emr_cmd = MC_CMD_GET_NETPORT_STATISTICS;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_PORT_HANDLE, nph);
+
+	MCDI_IN_POPULATE_DWORD_6(req, GET_NETPORT_STATISTICS_IN_CMD,
+	    GET_NETPORT_STATISTICS_IN_DMA, upload,
+	    GET_NETPORT_STATISTICS_IN_CLEAR, clear,
+	    GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE,
+		    enable | events | disable,
+	    GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE, enable | events,
+	    GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT, !events,
+	    GET_NETPORT_STATISTICS_IN_PERIOD_MS,
+		    (enable | events) ? period_ms : 0);
+
+	if (enable || events || upload) {
+		const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
+		uint32_t sz;
+
+		/* Periodic stats or stats upload require a DMA buffer */
+		if (esmp == NULL) {
+			rc = EINVAL;
+			goto fail1;
+		}
+
+		sz = encp->enc_mac_stats_nstats * sizeof (efx_qword_t);
+
+		if (EFSYS_MEM_SIZE(esmp) < sz) {
+			/* DMA buffer too small */
+			rc = ENOSPC;
+			goto fail2;
+		}
+
+		MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO,
+		    EFSYS_MEM_ADDR(esmp) & 0xffffffff);
+		MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI,
+		    EFSYS_MEM_ADDR(esmp) >> 32);
+		MCDI_IN_SET_DWORD(req, GET_NETPORT_STATISTICS_IN_DMA_LEN, sz);
+	}
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		/* EF10: Expect ENOENT if no DMA queues are initialised */
+		if ((req.emr_rc != ENOENT) ||
+		    (enp->en_rx_qcount + enp->en_tx_qcount != 0)) {
+			rc = req.emr_rc;
+			goto fail3;
+		}
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+#endif /* EFSYS_OPT_MAC_STATS */
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 2fbf1495d1..94d076db95 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -63,6 +63,28 @@ medford4_mac_stats_get_mask(
 	__in			efx_nic_t *enp,
 	__inout_bcount(sz)	uint32_t *maskp,
 	__in			size_t sz);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_upload(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn		efx_rc_t
+medford4_mac_stats_periodic(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp,
+	__in			uint16_t period_ms,
+	__in			boolean_t events);
+
+LIBEFX_INTERNAL
+extern	__checkReturn			efx_rc_t
+medford4_mac_stats_update(
+	__in				efx_nic_t *enp,
+	__in				efsys_mem_t *esmp,
+	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stats,
+	__inout_opt			uint32_t *generationp);
 #endif /* EFSYS_OPT_MAC_STATS */
 
 #ifdef	__cplusplus
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index 23c59f18ed..3e2493e824 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -119,5 +119,124 @@ medford4_mac_stats_get_mask(
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
 }
+
+	__checkReturn		efx_rc_t
+medford4_mac_stats_upload(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
+
+	rc = efx_np_mac_stats(enp,
+		    epp->ep_np_handle, EFX_STATS_UPLOAD, esmp, 0);
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn		efx_rc_t
+medford4_mac_stats_periodic(
+	__in			efx_nic_t *enp,
+	__in			efsys_mem_t *esmp,
+	__in			uint16_t period_ms,
+	__in			boolean_t events)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_rc_t rc;
+
+	if (period_ms == 0) {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_DISABLE, NULL, 0);
+	} else if (events != B_FALSE) {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_ENABLE_EVENTS, esmp, period_ms);
+	} else {
+		rc = efx_np_mac_stats(enp, epp->ep_np_handle,
+			    EFX_STATS_ENABLE_NOEVENTS, esmp, period_ms);
+	}
+
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+#define	MEDFORD4_MAC_STAT_READ(_esmp, _field, _eqp)			\
+	EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
+
+	__checkReturn			efx_rc_t
+medford4_mac_stats_update(
+	__in				efx_nic_t *enp,
+	__in				efsys_mem_t *esmp,
+	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stats,
+	__inout_opt			uint32_t *generationp)
+{
+	const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
+	efx_port_t *epp = &(enp->en_port);
+	efx_qword_t generation_start;
+	efx_qword_t generation_end;
+	unsigned int i;
+	efx_rc_t rc;
+
+	if (EFSYS_MEM_SIZE(esmp) <
+	    (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
+		/* DMA buffer too small */
+		rc = ENOSPC;
+		goto fail1;
+	}
+
+	/* Read END first so we don't race with the MC */
+	EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
+	MEDFORD4_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
+	    &generation_end);
+	EFSYS_MEM_READ_BARRIER();
+
+	for (i = 0; i < EFX_ARRAY_SIZE(epp->ep_np_mac_stat_lut); ++i) {
+		efx_qword_t value;
+
+		if (epp->ep_np_mac_stat_lut[i].ens_valid == B_FALSE)
+			continue;
+
+		MEDFORD4_MAC_STAT_READ(esmp,
+		    epp->ep_np_mac_stat_lut[i].ens_dma_fld, &value);
+
+		EFSYS_STAT_SET_QWORD(&(stats[i]), &value);
+	}
+
+	/* TODO: care about VADAPTOR statistics when VF support arrives */
+
+	/* Read START generation counter */
+	EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
+	EFSYS_MEM_READ_BARRIER();
+
+	/* We never parse marker descriptors; assume start is 0 offset */
+	MEDFORD4_MAC_STAT_READ(esmp, 0, &generation_start);
+
+	/* Check that we didn't read the stats in the middle of a DMA */
+	if (memcmp(&generation_start, &generation_end,
+		    sizeof (generation_start)) != 0)
+		return (EAGAIN);
+
+	if (generationp != NULL)
+		*generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+#undef MEDFORD4_MAC_STAT_READ
 #endif /* EFSYS_OPT_MAC_STATS */
 #endif /* EFSYS_OPT_MEDFORD4 */
-- 
2.39.5

[PATCH v2 35/45] common/sfc_efx/base: implement MAC PDU controls for Medford4

[Ivan Malov]

Leverage new netport MCDI to implement support for such APIs.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_impl.h      |  4 ++
 drivers/common/sfc_efx/base/efx_mac.c       |  4 +-
 drivers/common/sfc_efx/base/efx_np.c        | 17 ++++++++
 drivers/common/sfc_efx/base/medford4_impl.h | 11 ++++++
 drivers/common/sfc_efx/base/medford4_mac.c  | 44 +++++++++++++++++++++
 5 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 7dbad601ff..43964ccdba 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1934,6 +1934,7 @@ efx_np_link_state(
 
 typedef struct efx_np_mac_state_s {
 	uint32_t	enms_fcntl;
+	uint32_t	enms_pdu;
 	boolean_t	enms_up;
 } efx_np_mac_state_t;
 
@@ -1956,9 +1957,12 @@ efx_np_link_ctrl(
 	__in		boolean_t fcntl_an);
 
 typedef struct efx_np_mac_ctrl_s {
+	boolean_t	enmc_set_pdu_only;
+
 	boolean_t	enmc_fcntl_autoneg;
 	boolean_t	enmc_include_fcs;
 	uint32_t	enmc_fcntl;
+	uint32_t	enmc_pdu;
 } efx_np_mac_ctrl_t;
 
 LIBEFX_INTERNAL
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 92585517c0..9a0cf64fd9 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -94,8 +94,8 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 	medford4_mac_poll,			/* emo_poll */
 	medford4_mac_up,			/* emo_up */
 	ef10_mac_addr_set,			/* emo_addr_set */
-	ef10_mac_pdu_set,			/* emo_pdu_set */
-	ef10_mac_pdu_get,			/* emo_pdu_get */
+	medford4_mac_pdu_set,			/* emo_pdu_set */
+	medford4_mac_pdu_get,			/* emo_pdu_get */
 	medford4_mac_reconfigure,		/* emo_reconfigure */
 	ef10_mac_multicast_list_set,		/* emo_multicast_list_set */
 	ef10_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index d54174332e..2e2043b520 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -801,6 +801,7 @@ efx_np_attach(
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
 	efx_np_link_state_t ls;
+	efx_np_mac_state_t ms;
 	efx_rc_t rc;
 
 	if (efx_np_supported(enp) == B_FALSE)
@@ -852,8 +853,16 @@ efx_np_attach(
 		goto fail4;
 #endif /* EFSYS_OPT_MAC_STATS */
 
+	rc = efx_np_mac_state(enp, epp->ep_np_handle, &ms);
+	if (rc != 0)
+		goto fail5;
+
+	epp->ep_mac_pdu = ms.enms_pdu;
 	return (0);
 
+fail5:
+	EFSYS_PROBE(fail5);
+
 #if EFSYS_OPT_MAC_STATS
 fail4:
 	EFSYS_PROBE(fail4);
@@ -915,6 +924,7 @@ efx_np_mac_state(
 	if (MCDI_OUT_DWORD(req, MAC_STATE_OUT_MAC_FAULT_FLAGS) == 0)
 		msp->enms_up = B_TRUE;
 
+	msp->enms_pdu = MCDI_OUT_DWORD(req, MAC_STATE_OUT_MAX_FRAME_LEN);
 	msp->enms_fcntl = MCDI_OUT_DWORD(req, MAC_STATE_OUT_FCNTL);
 	return (0);
 
@@ -1210,6 +1220,12 @@ efx_np_mac_ctrl(
 
 	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_PORT_HANDLE, nph);
 
+	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_MAX_FRAME_LEN, mc->enmc_pdu);
+	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN;
+
+	if (mc->enmc_set_pdu_only != B_FALSE)
+		goto skip_full_reconfigure;
+
 	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS;
 	if (mc->enmc_include_fcs != B_FALSE)
 		flags |= 1U << MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS;
@@ -1241,6 +1257,7 @@ efx_np_mac_ctrl(
 	cfg |= 1U << MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL;
 	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_FCNTL, fcntl);
 
+skip_full_reconfigure:
 	MCDI_IN_SET_DWORD(req, MAC_CTRL_IN_V2_CONTROL_FLAGS, cfg);
 
 	efx_mcdi_execute(enp, &req);
diff --git a/drivers/common/sfc_efx/base/medford4_impl.h b/drivers/common/sfc_efx/base/medford4_impl.h
index 94d076db95..e861b3e7de 100644
--- a/drivers/common/sfc_efx/base/medford4_impl.h
+++ b/drivers/common/sfc_efx/base/medford4_impl.h
@@ -51,6 +51,17 @@ medford4_mac_up(
 	__in		efx_nic_t *enp,
 	__out		boolean_t *mac_upp);
 
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_pdu_set(
+	__in		efx_nic_t *enp);
+
+LIBEFX_INTERNAL
+extern	__checkReturn	efx_rc_t
+medford4_mac_pdu_get(
+	__in		efx_nic_t *enp,
+	__out		size_t *pdup);
+
 LIBEFX_INTERNAL
 extern	__checkReturn		efx_rc_t
 medford4_mac_reconfigure(
diff --git a/drivers/common/sfc_efx/base/medford4_mac.c b/drivers/common/sfc_efx/base/medford4_mac.c
index 3e2493e824..8ef84c69c6 100644
--- a/drivers/common/sfc_efx/base/medford4_mac.c
+++ b/drivers/common/sfc_efx/base/medford4_mac.c
@@ -47,6 +47,49 @@ medford4_mac_up(
 	*mac_upp = els.els_mac_up;
 	return (0);
 
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+medford4_mac_pdu_set(
+	__in		efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_np_mac_ctrl_t mc = {0};
+	efx_rc_t rc;
+
+	mc.enmc_set_pdu_only = B_TRUE;
+	mc.enmc_pdu = epp->ep_mac_pdu;
+
+	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
+	__checkReturn	efx_rc_t
+medford4_mac_pdu_get(
+	__in		efx_nic_t *enp,
+	__out		size_t *pdup)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_np_mac_state_t ms;
+	efx_rc_t rc;
+
+	rc = efx_np_mac_state(enp, epp->ep_np_handle, &ms);
+	if (rc != 0)
+		goto fail1;
+
+	*pdup = ms.enms_pdu;
+	return (0);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 	return (rc);
@@ -63,6 +106,7 @@ medford4_mac_reconfigure(
 	mc.enmc_fcntl_autoneg = epp->ep_fcntl_autoneg;
 	mc.enmc_include_fcs = epp->ep_include_fcs;
 	mc.enmc_fcntl = epp->ep_fcntl;
+	mc.enmc_pdu = epp->ep_mac_pdu;
 
 	rc = efx_np_mac_ctrl(enp, epp->ep_np_handle, &mc);
 	if (rc != 0)
-- 
2.39.5

[PATCH v2 36/45] common/sfc_efx/base: correct MAC PDU calculation on Medford4

[Ivan Malov]

For managing MAC PDU (max. frame size), client drivers apply
EFX macros to switch between PDU and SDU forms. These macros
include a workaround for a bug that dates back to Siena NICs.

Starting with Medford4, the bug is no longer there and it is
wrong to use the macros, so provide users with a replacement.
The new APIs will either include the said workaround or omit
it, depending on whether support for netport MCDI is present.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx.h         | 25 +++++++++++++++++++++++
 drivers/common/sfc_efx/base/efx_mac.c     | 19 +++++++++++++++--
 drivers/common/sfc_efx/base/efx_nic.c     |  3 +++
 drivers/common/sfc_efx/sfc_base_symbols.c |  1 +
 4 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 6ca108cffe..73dc38f84e 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -668,24 +668,45 @@ typedef enum efx_link_mode_e {
 
 #define	EFX_MAC_SDU_MAX	9202
 
+/*
+ * NOTE: the PDU macros implement an obsolete workaround that is needed for
+ * MC_CMD_SET_MAC; do not use the PDU macros for the netport MCDI commands,
+ * which do not use the workaround.
+ */
+
 #define	EFX_MAC_PDU_ADJUSTMENT					\
 	(/* EtherII */ 14					\
 	    + /* VLAN */ 4					\
 	    + /* CRC */ 4					\
 	    + /* bug16011 */ 16)				\
 
+/* NOTE: this macro is deprecated; use efx_mac_pdu_from_sdu(). */
 #define	EFX_MAC_PDU(_sdu)					\
 	EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
 
 /*
  * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
  * the SDU rounded up slightly.
+ *
+ * NOTE: do not use this macro in new code as it is
+ * incorrect for the netport MCDI commands.
  */
 #define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
 
 #define	EFX_MAC_PDU_MIN	60
+
+/* NOTE: this macro is deprecated; use encp->enc_mac_pdu_max. */
 #define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
 
+/*
+ * For use with efx_mac_pdu_set(), convert the given SDU value to its PDU form.
+ */
+LIBEFX_API
+extern			size_t
+efx_mac_pdu_from_sdu(
+	__in		efx_nic_t *enp,
+	__in		size_t sdu);
+
 LIBEFX_API
 extern	__checkReturn	efx_rc_t
 efx_mac_pdu_get(
@@ -1729,6 +1750,10 @@ typedef struct efx_nic_cfg_s {
 	efx_nic_dma_mapping_t	enc_dma_mapping;
 	/* Physical ports shared by PFs */
 	efx_port_usage_t	enc_port_usage;
+	/* Minimum MAC PDU value to use with efx_mac_pdu_set() */
+	uint32_t		enc_mac_pdu_min;
+	/* Maximum MAC PDU value to use with efx_mac_pdu_set() */
+	uint32_t		enc_mac_pdu_max;
 } efx_nic_cfg_t;
 
 #define	EFX_PCI_VF_INVALID 0xffff
diff --git a/drivers/common/sfc_efx/base/efx_mac.c b/drivers/common/sfc_efx/base/efx_mac.c
index 9a0cf64fd9..69f053ce44 100644
--- a/drivers/common/sfc_efx/base/efx_mac.c
+++ b/drivers/common/sfc_efx/base/efx_mac.c
@@ -114,6 +114,20 @@ static const efx_mac_ops_t	__efx_mac_medford4_ops = {
 };
 #endif /* EFSYS_OPT_MEDFORD4 */
 
+			size_t
+efx_mac_pdu_from_sdu(
+	__in		efx_nic_t *enp,
+	__in		size_t sdu)
+{
+	if (efx_np_supported(enp) != B_FALSE) {
+		/* PDU size for netport MCDI capable adaptors. */
+		return sdu + 14 /* ETH */ + 4 /* VLAN */ + 4 /* FCS */;
+	} else {
+		/* PDU size for legacy MC_CMD_SET_MAC command. */
+		return EFX_MAC_PDU(sdu);
+	}
+}
+
 	__checkReturn			efx_rc_t
 efx_mac_pdu_set(
 	__in				efx_nic_t *enp,
@@ -121,6 +135,7 @@ efx_mac_pdu_set(
 {
 	efx_port_t *epp = &(enp->en_port);
 	const efx_mac_ops_t *emop = epp->ep_emop;
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	uint32_t old_pdu;
 	efx_rc_t rc;
 
@@ -128,12 +143,12 @@ efx_mac_pdu_set(
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 	EFSYS_ASSERT(emop != NULL);
 
-	if (pdu < EFX_MAC_PDU_MIN) {
+	if (pdu < encp->enc_mac_pdu_min) {
 		rc = EINVAL;
 		goto fail1;
 	}
 
-	if (pdu > EFX_MAC_PDU_MAX) {
+	if (pdu > encp->enc_mac_pdu_max) {
 		rc = EINVAL;
 		goto fail2;
 	}
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 1ec684da40..1c25270792 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -491,6 +491,9 @@ efx_nic_probe(
 
 	encp->enc_features = enp->en_features;
 
+	encp->enc_mac_pdu_max = efx_mac_pdu_from_sdu(enp, EFX_MAC_SDU_MAX);
+	encp->enc_mac_pdu_min = EFX_MAC_PDU_MIN;
+
 	if ((rc = efx_phy_probe(enp)) != 0)
 		goto fail2;
 
diff --git a/drivers/common/sfc_efx/sfc_base_symbols.c b/drivers/common/sfc_efx/sfc_base_symbols.c
index ae6605632d..0e74034031 100644
--- a/drivers/common/sfc_efx/sfc_base_symbols.c
+++ b/drivers/common/sfc_efx/sfc_base_symbols.c
@@ -59,6 +59,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_trigger)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_status_line)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_status_message)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_intr_fatal)
+RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_pdu_from_sdu)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_pdu_set)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_pdu_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_mac_addr_set)
-- 
2.39.5

[PATCH v2 37/45] net/sfc: make use of generic EFX MAC PDU calculation helpers

[Ivan Malov]

To make sure that MAC PDU values do not come with legacy bug
workaround baked in when running on newer Medford4 NICs, use
generic replacement APIs from EFX in place of MAC PDU macros.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc_dp_tx.h   |  3 +++
 drivers/net/sfc/sfc_ef10_tx.c | 13 ++++++++-----
 drivers/net/sfc/sfc_ethdev.c  | 17 ++++++++++-------
 drivers/net/sfc/sfc_port.c    |  2 +-
 drivers/net/sfc/sfc_repr.c    |  7 ++++++-
 drivers/net/sfc/sfc_repr.h    |  1 +
 drivers/net/sfc/sfc_tx.c      |  2 ++
 7 files changed, 31 insertions(+), 14 deletions(-)

diff --git a/drivers/net/sfc/sfc_dp_tx.h b/drivers/net/sfc/sfc_dp_tx.h
index aad3b06595..0baf8c7dd6 100644
--- a/drivers/net/sfc/sfc_dp_tx.h
+++ b/drivers/net/sfc/sfc_dp_tx.h
@@ -84,6 +84,9 @@ struct sfc_dp_tx_qcreate_info {
 
 	/** NIC's DMA mapping information */
 	const struct sfc_nic_dma_info	*nic_dma_info;
+
+	/** Maximum MAC PDU (frame size) */
+	unsigned int		max_pdu;
 };
 
 /**
diff --git a/drivers/net/sfc/sfc_ef10_tx.c b/drivers/net/sfc/sfc_ef10_tx.c
index 116229382b..5543dc495f 100644
--- a/drivers/net/sfc/sfc_ef10_tx.c
+++ b/drivers/net/sfc/sfc_ef10_tx.c
@@ -65,6 +65,7 @@ struct sfc_ef10_txq {
 	unsigned int			max_fill_level;
 	unsigned int			free_thresh;
 	unsigned int			evq_read_ptr;
+	unsigned int			max_pdu;
 	struct sfc_ef10_tx_sw_desc	*sw_ring;
 	efx_qword_t			*txq_hw_ring;
 	volatile void			*doorbell;
@@ -252,7 +253,7 @@ sfc_ef10_tx_qpush(struct sfc_ef10_txq *txq, unsigned int added,
 }
 
 static unsigned int
-sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m)
+sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m, unsigned int max_pdu)
 {
 	unsigned int extra_descs_per_seg;
 	unsigned int extra_descs_per_pkt;
@@ -290,8 +291,7 @@ sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m)
 	 * maximum PDU size.
 	 */
 	extra_descs_per_pkt =
-		(RTE_MIN((unsigned int)EFX_MAC_PDU_MAX,
-			 SFC_MBUF_PKT_LEN_MAX) - 1) /
+		(RTE_MIN(max_pdu, SFC_MBUF_PKT_LEN_MAX) - 1) /
 		SFC_EF10_TX_DMA_DESC_LEN_MAX;
 
 	return m->nb_segs + RTE_MIN(m->nb_segs * extra_descs_per_seg,
@@ -672,7 +672,8 @@ sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 			goto dma_desc_space_update;
 		}
 
-		if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space) {
+		if (sfc_ef10_tx_pkt_descs_max(m_seg, txq->max_pdu) >
+		    dma_desc_space) {
 			if (reap_done)
 				break;
 
@@ -686,7 +687,8 @@ sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 			reap_done = true;
 			dma_desc_space = txq->max_fill_level -
 				(added - txq->completed);
-			if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space)
+			if (sfc_ef10_tx_pkt_descs_max(m_seg, txq->max_pdu) >
+			    dma_desc_space)
 				break;
 		}
 
@@ -986,6 +988,7 @@ sfc_ef10_tx_qcreate(uint16_t port_id, uint16_t queue_id,
 			(info->hw_index << info->vi_window_shift);
 	txq->evq_hw_ring = info->evq_hw_ring;
 	txq->tso_tcp_header_offset_limit = info->tso_tcp_header_offset_limit;
+	txq->max_pdu = info->max_pdu;
 
 	sfc_ef10_tx_info(&txq->dp.dpq, "TxQ doorbell is %p", txq->doorbell);
 
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 05194918f9..bd0061f557 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -90,6 +90,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev);
 	struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev);
 	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 	struct sfc_rss *rss = &sas->rss;
 	struct sfc_mae *mae = &sa->mae;
 
@@ -98,7 +99,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 	dev_info->max_mtu = EFX_MAC_SDU_MAX;
 
-	dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX;
+	dev_info->max_rx_pktlen = encp->enc_mac_pdu_max;
 
 	dev_info->max_vfs = sa->sriov.num_vfs;
 
@@ -1112,23 +1113,24 @@ static int
 sfc_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 {
 	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
-	size_t pdu = EFX_MAC_PDU(mtu);
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
+	size_t pdu = efx_mac_pdu_from_sdu(sa->nic, mtu);
 	size_t old_pdu;
 	int rc;
 
 	sfc_log_init(sa, "mtu=%u", mtu);
 
 	rc = EINVAL;
-	if (pdu < EFX_MAC_PDU_MIN) {
+	if (pdu < encp->enc_mac_pdu_min) {
 		sfc_err(sa, "too small MTU %u (PDU size %u less than min %u)",
 			(unsigned int)mtu, (unsigned int)pdu,
-			EFX_MAC_PDU_MIN);
+			encp->enc_mac_pdu_min);
 		goto fail_inval;
 	}
-	if (pdu > EFX_MAC_PDU_MAX) {
+	if (pdu > encp->enc_mac_pdu_max) {
 		sfc_err(sa, "too big MTU %u (PDU size %u greater than max %u)",
 			(unsigned int)mtu, (unsigned int)pdu,
-			(unsigned int)EFX_MAC_PDU_MAX);
+			encp->enc_mac_pdu_max);
 		goto fail_inval;
 	}
 
@@ -3378,6 +3380,7 @@ sfc_eth_dev_create_repr(struct sfc_adapter *sa,
 			uint16_t repr_port,
 			enum rte_eth_representor_type type)
 {
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 	struct sfc_repr_entity_info entity;
 	efx_mport_sel_t mport_sel;
 	int rc;
@@ -3414,7 +3417,7 @@ sfc_eth_dev_create_repr(struct sfc_adapter *sa,
 	entity.vf = repr_port;
 
 	rc = sfc_repr_create(sa->eth_dev, &entity, sa->mae.switch_domain_id,
-			     &mport_sel);
+			     encp->enc_mac_pdu_max, &mport_sel);
 	if (rc != 0) {
 		sfc_err(sa,
 			"failed to create representor for controller %u port %u repr_port %u: %s",
diff --git a/drivers/net/sfc/sfc_port.c b/drivers/net/sfc/sfc_port.c
index e5bb6d8620..5e80003ca1 100644
--- a/drivers/net/sfc/sfc_port.c
+++ b/drivers/net/sfc/sfc_port.c
@@ -391,7 +391,7 @@ sfc_port_configure(struct sfc_adapter *sa)
 
 	sfc_log_init(sa, "entry");
 
-	port->pdu = EFX_MAC_PDU(dev_data->mtu);
+	port->pdu = efx_mac_pdu_from_sdu(sa->nic, dev_data->mtu);
 
 	if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 		port->include_fcs = true;
diff --git a/drivers/net/sfc/sfc_repr.c b/drivers/net/sfc/sfc_repr.c
index 2c1421b959..18e76fa7da 100644
--- a/drivers/net/sfc/sfc_repr.c
+++ b/drivers/net/sfc/sfc_repr.c
@@ -32,6 +32,7 @@ struct sfc_repr_shared {
 	uint16_t		repr_id;
 	uint16_t		switch_domain_id;
 	uint16_t		switch_port_id;
+	unsigned int		max_pdu;
 };
 
 struct sfc_repr_queue_stats {
@@ -514,7 +515,7 @@ sfc_repr_dev_infos_get(struct rte_eth_dev *dev,
 
 	dev_info->device = dev->device;
 
-	dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX;
+	dev_info->max_rx_pktlen = srs->max_pdu;
 	dev_info->max_rx_queues = SFC_REPR_RXQ_MAX;
 	dev_info->max_tx_queues = SFC_REPR_TXQ_MAX;
 	dev_info->default_rxconf.rx_drop_en = 1;
@@ -920,6 +921,7 @@ struct sfc_repr_init_data {
 	efx_pcie_interface_t	intf;
 	uint16_t		pf;
 	uint16_t		vf;
+	unsigned int		max_pdu;
 };
 
 static int
@@ -1012,6 +1014,7 @@ sfc_repr_eth_dev_init(struct rte_eth_dev *dev, void *init_params)
 	srs->pf_port_id = repr_data->pf_port_id;
 	srs->repr_id = srs->switch_port_id;
 	srs->switch_domain_id = repr_data->switch_domain_id;
+	srs->max_pdu = repr_data->max_pdu;
 
 	dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 	dev->data->representor_id = srs->repr_id;
@@ -1062,6 +1065,7 @@ int
 sfc_repr_create(struct rte_eth_dev *parent,
 		struct sfc_repr_entity_info *entity,
 		uint16_t switch_domain_id,
+		unsigned int max_pdu,
 		const efx_mport_sel_t *mport_sel)
 {
 	struct sfc_repr_init_data repr_data;
@@ -1108,6 +1112,7 @@ sfc_repr_create(struct rte_eth_dev *parent,
 		repr_data.intf = entity->intf;
 		repr_data.pf = entity->pf;
 		repr_data.vf = entity->vf;
+		repr_data.max_pdu = max_pdu;
 
 		ret = rte_eth_dev_create(parent->device, name,
 					 sizeof(struct sfc_repr_shared),
diff --git a/drivers/net/sfc/sfc_repr.h b/drivers/net/sfc/sfc_repr.h
index 2093973761..01f5947a84 100644
--- a/drivers/net/sfc/sfc_repr.h
+++ b/drivers/net/sfc/sfc_repr.h
@@ -36,6 +36,7 @@ struct sfc_repr_entity_info {
 int sfc_repr_create(struct rte_eth_dev *parent,
 		    struct sfc_repr_entity_info *entity,
 		    uint16_t switch_domain_id,
+		    unsigned int max_pdu,
 		    const efx_mport_sel_t *mport_sel);
 
 #ifdef __cplusplus
diff --git a/drivers/net/sfc/sfc_tx.c b/drivers/net/sfc/sfc_tx.c
index f376f24f7b..ebc0a8235b 100644
--- a/drivers/net/sfc/sfc_tx.c
+++ b/drivers/net/sfc/sfc_tx.c
@@ -228,6 +228,8 @@ sfc_tx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
 
 	info.nic_dma_info = &sas->nic_dma_info;
 
+	info.max_pdu = encp->enc_mac_pdu_max;
+
 	rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
 				     &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
 				     socket_id, &info, &txq_info->dp);
-- 
2.39.5

[PATCH v2 38/45] common/sfc_efx/base: ignore legacy link events on new boards

[Ivan Malov]

New adaptors (for instance, Medford4) come with netport MCDI
and also support new link change events, however, older ones
can also be generated. For consistency, ignore legacy events.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_ev.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/common/sfc_efx/base/ef10_ev.c b/drivers/common/sfc_efx/base/ef10_ev.c
index 011ef49de7..82a2284f2b 100644
--- a/drivers/common/sfc_efx/base/ef10_ev.c
+++ b/drivers/common/sfc_efx/base/ef10_ev.c
@@ -907,6 +907,16 @@ ef10_ev_mcdi(
 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 
 	case MCDI_EVENT_CODE_LINKCHANGE_V2:
+		if (efx_np_supported(enp) != B_FALSE) {
+			/*
+			 * Netport MCDI capable NICs support new link change
+			 * events, but legacy LINKCHANGE_V2 events may still
+			 * show up should the firmware support them. For the
+			 * sake of consistency, ignore LINKCHANGE_V2 events.
+			 */
+			break;
+		}
+
 		ev_is_v2 = B_TRUE;
 		/* Fallthrough */
 	case MCDI_EVENT_CODE_LINKCHANGE: {
-- 
2.39.5

[PATCH v2 39/45] common/sfc_efx/base: add link event processing on new boards

[Ivan Malov]

Link change events on netport MCDI capable NICs do not carry
any specifics of the new link state. Such need to be queried
separately. Add processing of the events, with an indication
to the client driver telling it to collect the status itself.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_ev.c | 29 +++++++++++++++++++++++++++
 drivers/common/sfc_efx/base/efx.h     |  6 ++++++
 drivers/common/sfc_efx/base/efx_nic.c |  5 +++++
 3 files changed, 40 insertions(+)

diff --git a/drivers/common/sfc_efx/base/ef10_ev.c b/drivers/common/sfc_efx/base/ef10_ev.c
index 82a2284f2b..a97c1bf43e 100644
--- a/drivers/common/sfc_efx/base/ef10_ev.c
+++ b/drivers/common/sfc_efx/base/ef10_ev.c
@@ -866,6 +866,7 @@ ef10_ev_mcdi(
 	__in_opt	void *arg)
 {
 	efx_nic_t *enp = eep->ee_enp;
+	efx_port_t *epp = &(enp->en_port);
 	unsigned int code;
 	boolean_t should_abort = B_FALSE;
 	boolean_t ev_is_v2 = B_FALSE;
@@ -906,6 +907,34 @@ ef10_ev_mcdi(
 		break;
 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 
+	case MCDI_EVENT_CODE_PORT_LINKCHANGE:
+		/*
+		 * These events are generated on netport MCDI capable
+		 * boards. They supersede legacy LINKCHANGE_V2 events.
+		 */
+		if (MCDI_EV_FIELD(eqp, PORT_LINKCHANGE_PORT_HANDLE) ==
+		    epp->ep_np_handle) {
+			efx_link_mode_t mode;
+
+			if (MCDI_EV_FIELD(eqp, PORT_LINKCHANGE_LINK_UP) == 1)
+				mode = EFX_LINK_UNKNOWN;
+			else
+				mode = EFX_LINK_DOWN;
+
+			/*
+			 * The event does not contain full link state details.
+			 *
+			 * Either notify the client driver with a dummy link
+			 * mode value (UNKNOWN), just to say the link is up,
+			 * or, in case the link is not up, pass DOWN value.
+			 *
+			 * The client driver will need to poll for link state
+			 * in order to get full details like speed and duplex.
+			 */
+			should_abort = eecp->eec_link_change(arg, mode);
+		}
+		break;
+
 	case MCDI_EVENT_CODE_LINKCHANGE_V2:
 		if (efx_np_supported(enp) != B_FALSE) {
 			/*
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 73dc38f84e..7b43a89551 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1754,6 +1754,12 @@ typedef struct efx_nic_cfg_s {
 	uint32_t		enc_mac_pdu_min;
 	/* Maximum MAC PDU value to use with efx_mac_pdu_set() */
 	uint32_t		enc_mac_pdu_max;
+	/*
+	 * When true, the link mode value passed from eec_link_change() is
+	 * either UNKNOWN (merely saying the link is up) or DOWN. In order
+	 * to have exact speed/duplex, efx_port_poll() needs to be invoked.
+	 */
+	boolean_t		enc_link_ev_need_poll;
 } efx_nic_cfg_t;
 
 #define	EFX_PCI_VF_INVALID 0xffff
diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c
index 1c25270792..ab2bb1c160 100644
--- a/drivers/common/sfc_efx/base/efx_nic.c
+++ b/drivers/common/sfc_efx/base/efx_nic.c
@@ -494,6 +494,11 @@ efx_nic_probe(
 	encp->enc_mac_pdu_max = efx_mac_pdu_from_sdu(enp, EFX_MAC_SDU_MAX);
 	encp->enc_mac_pdu_min = EFX_MAC_PDU_MIN;
 
+	if (efx_np_supported(enp) == B_FALSE)
+		encp->enc_link_ev_need_poll = B_FALSE;
+	else
+		encp->enc_link_ev_need_poll = B_TRUE;
+
 	if ((rc = efx_phy_probe(enp)) != 0)
 		goto fail2;
 
-- 
2.39.5

[PATCH v2 40/45] net/sfc: query link status on link change events on new NICs

[Ivan Malov]

Link events signaled on new adaptors (Medford4 and later) do
not carry any specifics, so query the link status separately.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc.h        |  2 ++
 drivers/net/sfc/sfc_ethdev.c |  2 ++
 drivers/net/sfc/sfc_ev.c     | 51 +++++++++++++++++++++++++++++++++++-
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/drivers/net/sfc/sfc.h b/drivers/net/sfc/sfc.h
index 2432a2307e..819ce52529 100644
--- a/drivers/net/sfc/sfc.h
+++ b/drivers/net/sfc/sfc.h
@@ -309,6 +309,8 @@ struct sfc_adapter {
 	uint32_t			rxd_wait_timeout_ns;
 
 	bool				switchdev;
+
+	bool				link_ev_need_poll;
 };
 
 static inline struct sfc_adapter_shared *
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index bd0061f557..05933b1d39 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -3252,6 +3252,8 @@ sfc_eth_dev_init(struct rte_eth_dev *dev, void *init_params)
 	if (rc != 0)
 		goto fail_nic_dma_attach;
 
+	sa->link_ev_need_poll = encp->enc_link_ev_need_poll;
+
 	sfc_adapter_unlock(sa);
 
 	sfc_log_init(sa, "done");
diff --git a/drivers/net/sfc/sfc_ev.c b/drivers/net/sfc/sfc_ev.c
index c0d58c9554..1d1ee0671f 100644
--- a/drivers/net/sfc/sfc_ev.c
+++ b/drivers/net/sfc/sfc_ev.c
@@ -467,9 +467,58 @@ sfc_ev_link_change(void *arg, efx_link_mode_t link_mode)
 {
 	struct sfc_evq *evq = arg;
 	struct sfc_adapter *sa = evq->sa;
-	struct rte_eth_link new_link;
+	struct rte_eth_link new_link = {0};
 
+	if (sa->link_ev_need_poll) {
+		efx_link_mode_t new_mode;
+		bool poll_done = false;
+
+		/*
+		 * The event provides only the general status. When the link is
+		 * up, poll the port to get the speed, but it is not compulsory.
+		 */
+		if (link_mode != EFX_LINK_DOWN) {
+			int ret = 0;
+
+			if (sfc_adapter_trylock(sa)) {
+				/* Never poll when the adaptor is going down. */
+				if (sa->state == SFC_ETHDEV_STARTED) {
+					ret = efx_port_poll(sa->nic, &new_mode);
+					poll_done = true;
+				}
+
+				sfc_adapter_unlock(sa);
+			}
+
+			if (ret != 0) {
+				sfc_warn(sa, "port poll failed on link event");
+				poll_done = false;
+			}
+		}
+
+		if (poll_done) {
+			link_mode = new_mode;
+			goto decode_comprehensive;
+		}
+
+		new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		new_link.link_autoneg = RTE_ETH_LINK_AUTONEG;
+
+		if (link_mode == EFX_LINK_DOWN) {
+			new_link.link_speed  = RTE_ETH_SPEED_NUM_NONE;
+			new_link.link_status = RTE_ETH_LINK_DOWN;
+		} else {
+			new_link.link_speed  = RTE_ETH_SPEED_NUM_UNKNOWN;
+			new_link.link_status = RTE_ETH_LINK_UP;
+		}
+
+		goto set;
+	}
+
+decode_comprehensive:
 	sfc_port_link_mode_to_info(link_mode, &new_link);
+
+set:
 	if (rte_eth_linkstatus_set(sa->eth_dev, &new_link) == 0)
 		evq->sa->port.lsc_seq++;
 
-- 
2.39.5

[PATCH v2 41/45] common/sfc_efx/base: subscribe to netport link change events

[Ivan Malov]

Subscribe to the new link events on netport MCDI attach path.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/efx_np.c | 56 ++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 2e2043b520..3cefdda0e9 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -794,6 +794,48 @@ efx_np_stats_assign(
 }
 #endif /* EFSYS_OPT_MAC_STATS */
 
+static	__checkReturn	efx_rc_t
+efx_np_set_event_mask(
+	__in		efx_nic_t *enp,
+	__in		efx_np_handle_t nph,
+	__in		boolean_t want_linkchange_events)
+{
+	EFX_MCDI_DECLARE_BUF(payload,
+	    MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN,
+	    MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN);
+	efx_mcdi_req_t req;
+	efx_dword_t dword;
+	efx_rc_t rc;
+
+	req.emr_out_length = MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN;
+	req.emr_in_length = MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN;
+	req.emr_cmd = MC_CMD_SET_NETPORT_EVENTS_MASK;
+	req.emr_out_buf = payload;
+	req.emr_in_buf = payload;
+
+	EFX_ZERO_DWORD(dword);
+
+	if (want_linkchange_events != B_FALSE)
+		EFX_SET_DWORD_BIT(dword, EVENT_MASK_PORT_LINKCHANGE);
+
+	MCDI_IN_SET_DWORD(req, SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE, nph);
+	MCDI_IN_SET_DWORD(req, SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK,
+	    dword.ed_u32[0]);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
 	__checkReturn	efx_rc_t
 efx_np_attach(
 	__in		efx_nic_t *enp)
@@ -858,8 +900,17 @@ efx_np_attach(
 		goto fail5;
 
 	epp->ep_mac_pdu = ms.enms_pdu;
+
+	/* Subscribe to link change events. */
+	rc = efx_np_set_event_mask(enp, epp->ep_np_handle, B_TRUE);
+	if (rc != 0)
+		goto fail6;
+
 	return (0);
 
+fail6:
+	EFSYS_PROBE(fail6);
+
 fail5:
 	EFSYS_PROBE(fail5);
 
@@ -883,8 +934,13 @@ efx_np_attach(
 efx_np_detach(
 	__in	efx_nic_t *enp)
 {
+	efx_port_t *epp = &(enp->en_port);
+
 	if (efx_np_supported(enp) == B_FALSE)
 		return;
+
+	/* Unsubscribe from link change events. */
+	(void) efx_np_set_event_mask(enp, epp->ep_np_handle, B_FALSE);
 }
 
 	__checkReturn	efx_rc_t
-- 
2.39.5

[PATCH v2 42/45] net/sfc: offer support for 200G link ability on new adaptors

[Ivan Malov]

New adaptors (for instance, Medford4) can support 200G speed.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc.c        |  5 ++++-
 drivers/net/sfc/sfc_ethdev.c | 15 +++++++++++++++
 drivers/net/sfc/sfc_port.c   |  6 ++++++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/sfc/sfc.c b/drivers/net/sfc/sfc.c
index 938c967430..69747e49ae 100644
--- a/drivers/net/sfc/sfc.c
+++ b/drivers/net/sfc/sfc.c
@@ -126,7 +126,8 @@ sfc_phy_cap_from_link_speeds(uint32_t speeds)
 				(1 << EFX_PHY_CAP_25000FDX) |
 				(1 << EFX_PHY_CAP_40000FDX) |
 				(1 << EFX_PHY_CAP_50000FDX) |
-				(1 << EFX_PHY_CAP_100000FDX);
+				(1 << EFX_PHY_CAP_100000FDX) |
+				(1 << EFX_PHY_CAP_200000FDX);
 	}
 	if (speeds & RTE_ETH_LINK_SPEED_1G)
 		phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
@@ -140,6 +141,8 @@ sfc_phy_cap_from_link_speeds(uint32_t speeds)
 		phy_caps |= (1 << EFX_PHY_CAP_50000FDX);
 	if (speeds & RTE_ETH_LINK_SPEED_100G)
 		phy_caps |= (1 << EFX_PHY_CAP_100000FDX);
+	if (speeds & RTE_ETH_LINK_SPEED_200G)
+		phy_caps |= (1 << EFX_PHY_CAP_200000FDX);
 
 	return phy_caps;
 }
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 05933b1d39..80eb39e58d 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -117,6 +117,8 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G;
 	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX))
 		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G;
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_200000FDX))
+		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_200G;
 
 	dev_info->max_rx_queues = sa->rxq_max;
 	dev_info->max_tx_queues = sa->txq_max;
@@ -2442,6 +2444,19 @@ sfc_fec_get_capa_speed_to_fec(uint32_t supported_caps,
 		}
 		num++;
 	}
+	if (supported_caps & (1u << EFX_PHY_CAP_200000FDX)) {
+		if (speed_fec_capa != NULL) {
+			speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_200G;
+			speed_fec_capa[num].capa =
+				RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+				RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
+			if (rs) {
+				speed_fec_capa[num].capa |=
+					RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+			}
+		}
+		num++;
+	}
 
 	return num;
 }
diff --git a/drivers/net/sfc/sfc_port.c b/drivers/net/sfc/sfc_port.c
index 5e80003ca1..0a31a394d5 100644
--- a/drivers/net/sfc/sfc_port.c
+++ b/drivers/net/sfc/sfc_port.c
@@ -144,6 +144,8 @@ sfc_port_init_dev_link(struct sfc_adapter *sa)
 static efx_link_mode_t
 sfc_port_phy_caps_to_max_link_speed(uint32_t phy_caps)
 {
+	if (phy_caps & (1u << EFX_PHY_CAP_200000FDX))
+		return EFX_LINK_200000FDX;
 	if (phy_caps & (1u << EFX_PHY_CAP_100000FDX))
 		return EFX_LINK_100000FDX;
 	if (phy_caps & (1u << EFX_PHY_CAP_50000FDX))
@@ -649,6 +651,10 @@ sfc_port_link_mode_to_info(efx_link_mode_t link_mode,
 		link_info->link_speed  = RTE_ETH_SPEED_NUM_100G;
 		link_info->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 		break;
+	case EFX_LINK_200000FDX:
+		link_info->link_speed  = RTE_ETH_SPEED_NUM_200G;
+		link_info->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		break;
 	default:
 		SFC_ASSERT(B_FALSE);
 		/* FALLTHROUGH */
-- 
2.39.5

[PATCH v2 43/45] common/sfc_efx/base: support controls for netport lane count

[Ivan Malov]

On netport MCDI capable adaptors, link modes exported by libefx can be
backed by different technologies with different lane counts. Allow the
client drivers to get and set the lane count and query possible values.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/common/sfc_efx/base/ef10_phy.c     |   2 +
 drivers/common/sfc_efx/base/efx.h          |  29 ++++
 drivers/common/sfc_efx/base/efx_impl.h     |   4 +
 drivers/common/sfc_efx/base/efx_np.c       | 189 +++++++++++++++++++--
 drivers/common/sfc_efx/base/efx_phy.c      |  62 ++++++-
 drivers/common/sfc_efx/base/efx_port.c     |   1 +
 drivers/common/sfc_efx/base/medford4_phy.c |   5 +-
 drivers/common/sfc_efx/sfc_base_symbols.c  |   1 +
 8 files changed, 278 insertions(+), 15 deletions(-)

diff --git a/drivers/common/sfc_efx/base/ef10_phy.c b/drivers/common/sfc_efx/base/ef10_phy.c
index 114543e156..aaad105735 100644
--- a/drivers/common/sfc_efx/base/ef10_phy.c
+++ b/drivers/common/sfc_efx/base/ef10_phy.c
@@ -338,6 +338,8 @@ ef10_phy_get_link(
 			    fec, &elsp->epls.epls_link_mode,
 			    &elsp->epls.epls_fcntl, &elsp->epls.epls_fec);
 
+	elsp->epls.epls_lane_count = EFX_PHY_LANE_COUNT_DEFAULT;
+
 	if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN) {
 		elsp->epls.epls_ld_cap_mask = 0;
 	} else {
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 7b43a89551..8958f1b170 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1266,6 +1266,28 @@ efx_phy_lp_cap_get(
 	__in		efx_nic_t *enp,
 	__out		uint32_t *maskp);
 
+typedef enum efx_phy_lane_count_e {
+	EFX_PHY_LANE_COUNT_DEFAULT = 0,
+	EFX_PHY_LANE_COUNT_1 = 1,
+	EFX_PHY_LANE_COUNT_2 = 2,
+	EFX_PHY_LANE_COUNT_4 = 4,
+	EFX_PHY_LANE_COUNT_10 = 10,
+	EFX_PHY_LANE_COUNT_NTYPES,
+} efx_phy_lane_count_t;
+
+/*
+ * Instruct the port to use the specified lane count. For this to work, the
+ * active subset of advertised link modes must include at least one mode that
+ * supports this value. This API works only on netport MCDI capable adaptors.
+ *
+ * To query the current lane count, use efx_phy_link_state_get().
+ */
+LIBEFX_API
+extern	__checkReturn	efx_rc_t
+efx_phy_lane_count_set(
+	__in		efx_nic_t *enp,
+	__in		efx_phy_lane_count_t lane_count);
+
 LIBEFX_API
 extern	__checkReturn	efx_rc_t
 efx_phy_oui_get(
@@ -1760,6 +1782,12 @@ typedef struct efx_nic_cfg_s {
 	 * to have exact speed/duplex, efx_port_poll() needs to be invoked.
 	 */
 	boolean_t		enc_link_ev_need_poll;
+	/*
+	 * An array of masks to tell which link mode supports which lane counts.
+	 * For bit definitions, see 'efx_phy_lane_count_t'. It is only filled in
+	 * on netport MCDI capable adaptors.
+	 */
+	efx_dword_t		enc_phy_lane_counts[EFX_LINK_NMODES];
 } efx_nic_cfg_t;
 
 #define	EFX_PCI_VF_INVALID 0xffff
@@ -4072,6 +4100,7 @@ typedef struct efx_phy_link_state_s {
 	unsigned int		epls_fcntl;
 	efx_phy_fec_type_t	epls_fec;
 	efx_link_mode_t		epls_link_mode;
+	efx_phy_lane_count_t	epls_lane_count;
 } efx_phy_link_state_t;
 
 LIBEFX_API
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 43964ccdba..69268546d2 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -396,6 +396,8 @@ typedef struct efx_port_s {
 	uint8_t			ep_np_cap_data_raw[MC_CMD_ETH_AN_FIELDS_LEN];
 	/* Lookup table providing DMA buffer field IDs by EFX statistic IDs. */
 	efx_np_stat_t		ep_np_mac_stat_lut[EFX_MAC_NSTATS];
+	/* Client-requested lane count for the physical link. */
+	efx_phy_lane_count_t	ep_np_lane_count_req;
 } efx_port_t;
 
 typedef struct efx_mon_ops_s {
@@ -1916,6 +1918,7 @@ efx_np_detach(
 typedef struct efx_np_link_state_s {
 	uint32_t		enls_adv_cap_mask;
 	uint32_t		enls_lp_cap_mask;
+	efx_phy_lane_count_t	enls_lane_count;
 	efx_loopback_type_t	enls_loopback;
 	uint32_t		enls_speed;
 	uint8_t			enls_fec;
@@ -1953,6 +1956,7 @@ efx_np_link_ctrl(
 	__in		const uint8_t *cap_mask_sup_raw,
 	__in		efx_link_mode_t loopback_link_mode,
 	__in		efx_loopback_type_t loopback_mode,
+	__in		efx_phy_lane_count_t lane_count,
 	__in		uint32_t cap_mask_sw,
 	__in		boolean_t fcntl_an);
 
diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c
index 3cefdda0e9..a19c986691 100644
--- a/drivers/common/sfc_efx/base/efx_np.c
+++ b/drivers/common/sfc_efx/base/efx_np.c
@@ -86,6 +86,7 @@ struct efx_np_cap_map {
 	uint16_t	encm_sw;
 };
 
+/* NOTE: keep this in sync with 'efx_np_tech_to_lane_count'. */
 static const struct efx_np_cap_map efx_np_cap_map_tech[] = {
 	/* 1G */
 	{ MC_CMD_ETH_TECH_1000BASEKX, EFX_PHY_CAP_1000FDX },
@@ -292,6 +293,71 @@ efx_np_get_fixed_port_props(
 	return (rc);
 }
 
+static efx_phy_lane_count_t efx_np_tech_to_lane_count[] = {
+	/* 1G */
+	[MC_CMD_ETH_TECH_1000BASEKX] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_1000BASEX] = EFX_PHY_LANE_COUNT_1,
+
+	/* 10G */
+	[MC_CMD_ETH_TECH_10GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_LR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_LRM] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_10GBASE_ER] = EFX_PHY_LANE_COUNT_1,
+
+	/* 25GBASE */
+	[MC_CMD_ETH_TECH_25GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_25GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_25GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_25GBASE_LR_ER] = EFX_PHY_LANE_COUNT_1,
+
+	/* 40G */
+	[MC_CMD_ETH_TECH_40GBASE_KR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_40GBASE_CR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_40GBASE_SR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_40GBASE_LR4] = EFX_PHY_LANE_COUNT_4,
+
+	/* 50G */
+	[MC_CMD_ETH_TECH_50GBASE_CR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_50GBASE_KR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_50GBASE_SR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_50GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_LR_ER_FR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_50GBASE_DR] = EFX_PHY_LANE_COUNT_1,
+
+	/* 100G */
+	[MC_CMD_ETH_TECH_100GBASE_KR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_SR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_CR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_LR4_ER4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_100GBASE_KR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_SR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_CR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_DR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_100GBASE_KR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_SR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_LR_ER_FR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_CR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_DR] = EFX_PHY_LANE_COUNT_1,
+	[MC_CMD_ETH_TECH_100GBASE_CR10] = EFX_PHY_LANE_COUNT_10,
+
+	/* 200G */
+	[MC_CMD_ETH_TECH_200GBASE_KR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_SR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_DR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_CR4] = EFX_PHY_LANE_COUNT_4,
+	[MC_CMD_ETH_TECH_200GBASE_KR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_SR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_DR2] = EFX_PHY_LANE_COUNT_2,
+	[MC_CMD_ETH_TECH_200GBASE_CR2] = EFX_PHY_LANE_COUNT_2,
+};
+
 	__checkReturn	efx_rc_t
 efx_np_link_state(
 	__in		efx_nic_t *enp,
@@ -304,6 +370,7 @@ efx_np_link_state(
 	uint32_t status_flags;
 	efx_mcdi_req_t req;
 	uint32_t v3_flags;
+	uint16_t tech;
 	efx_rc_t rc;
 
 	req.emr_out_length = MC_CMD_LINK_STATE_OUT_V3_LEN;
@@ -378,6 +445,13 @@ efx_np_link_state(
 		    LINK_STATE_OUT_LINK_PARTNER_ABILITIES),
 	    &lsp->enls_lp_cap_mask);
 
+	tech = MCDI_OUT_WORD(req, LINK_STATE_OUT_LINK_TECHNOLOGY);
+
+	if (tech < EFX_ARRAY_SIZE(efx_np_tech_to_lane_count))
+		lsp->enls_lane_count = efx_np_tech_to_lane_count[tech];
+	else
+		lsp->enls_lane_count = EFX_PHY_LANE_COUNT_DEFAULT;
+
 	return (0);
 
 #if EFSYS_OPT_LOOPBACK
@@ -526,6 +600,53 @@ efx_np_assign_loopback_props(
 }
 #endif /* EFSYS_OPT_LOOPBACK */
 
+static				void
+efx_np_assign_lane_counts(
+	__in			efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_port_t *epp = &(enp->en_port);
+	unsigned int i;
+
+	for (i = 0; i < EFX_ARRAY_SIZE(encp->enc_phy_lane_counts); ++i) {
+		const struct efx_np_cap_map *map = efx_np_cap_map_tech;
+		uint16_t cap_enum_sw;
+		efx_dword_t dword;
+		efx_rc_t rc;
+
+		EFX_ZERO_DWORD(dword);
+
+		rc = efx_np_sw_link_mode_to_cap(i, &cap_enum_sw);
+		if (rc != 0) {
+			/* No support for this link mode => no lane counts. */
+			encp->enc_phy_lane_counts[i] = dword;
+			continue;
+		}
+
+		FOREACH_SUP_CAP(map,
+		    EFX_ARRAY_SIZE(efx_np_cap_map_tech),
+		    MCDI_STRUCT_MEMBER(epp->ep_np_cap_data_raw, const uint8_t,
+			    MC_CMD_ETH_AN_FIELDS_TECH_MASK),
+		    MC_CMD_ETH_AN_FIELDS_TECH_MASK_LEN) {
+			efx_phy_lane_count_t lane_count;
+
+			if (map->encm_sw != cap_enum_sw)
+				continue;
+
+			if (map->encm_hw >=
+			    EFX_ARRAY_SIZE(efx_np_tech_to_lane_count))
+				continue;
+
+			lane_count = efx_np_tech_to_lane_count[map->encm_hw];
+
+			if (lane_count != EFX_PHY_LANE_COUNT_DEFAULT)
+				EFX_SET_DWORD_BIT(dword, lane_count);
+		}
+
+		encp->enc_phy_lane_counts[i] = dword;
+	}
+}
+
 #if EFSYS_OPT_MAC_STATS
 /* HW statistic IDs, as per MC_CMD_MAC_STATISTICS_DESCRIPTOR format. */
 #define	EFX_NP_HW_STAT_ID(_src, _idx)					\
@@ -889,6 +1010,8 @@ efx_np_attach(
 	efx_np_assign_loopback_props(enp);
 #endif /* EFSYS_OPT_LOOPBACK */
 
+	efx_np_assign_lane_counts(enp);
+
 #if EFSYS_OPT_MAC_STATS
 	rc = efx_np_stats_assign(enp);
 	if (rc != 0)
@@ -993,6 +1116,13 @@ efx_np_mac_state(
 	return (rc);
 }
 
+/* Filter callback for capability lookups. Return 'B_FALSE' to skip the enum. */
+typedef			boolean_t
+(efx_np_cap_filter_cb)(
+	__in		uint16_t enum_hw,
+	__in		void *arg);
+
+
 static					void
 efx_np_cap_mask_sw_to_hw(
 	__in_ecount(hw_sw_map_nentries)	const struct efx_np_cap_map *hw_sw_map,
@@ -1000,6 +1130,8 @@ efx_np_cap_mask_sw_to_hw(
 	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
 	__in				size_t hw_cap_data_nbytes,
 	__in				uint32_t mask_sw,
+	__in_opt			efx_np_cap_filter_cb *filter_cb,
+	__in_opt			void *filter_arg,
 	__out				uint8_t *mask_hwp)
 {
 	FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries,
@@ -1009,6 +1141,10 @@ efx_np_cap_mask_sw_to_hw(
 		if ((mask_sw & flag_sw) != flag_sw)
 			continue;
 
+		if (filter_cb != NULL &&
+		    filter_cb(hw_sw_map->encm_hw, filter_arg) == B_FALSE)
+			continue;
+
 		mask_hwp[CAP_BYTE(hw_sw_map)] |= CAP_FLAG(hw_sw_map);
 		mask_sw &= ~(flag_sw);
 	}
@@ -1024,16 +1160,18 @@ efx_np_cap_mask_sw_to_hw(
  *
  * Do not check the input mask for leftover bits (unknown to EFX), as
  * inputs should have been validated by efx_phy_adv_cap_set() already.
+ *
+ * It is possible to use a callback to filter out certain mappings.
  */
 #define	EFX_NP_CAP_MASK_SW_TO_HW(					\
 	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
-	    _mask_sw, _mask_hwp)					\
+	    _mask_sw, _filter_cb, _filter_arg, _mask_hwp)		\
 	efx_np_cap_mask_sw_to_hw((_hw_sw_cap_map),			\
 	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
 	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
 		    MC_CMD_##_hw_cap_section),				\
-	    MC_CMD_##_hw_cap_section##_LEN,				\
-	    (_mask_sw), (_mask_hwp))
+	    MC_CMD_##_hw_cap_section##_LEN, (_mask_sw),			\
+	    (_filter_cb), (_filter_arg), (_mask_hwp))
 
 static					void
 efx_np_cap_sw_mask_to_hw_enum(
@@ -1042,6 +1180,8 @@ efx_np_cap_sw_mask_to_hw_enum(
 	__in_bcount(hw_cap_data_nbytes)	const uint8_t *hw_cap_data,
 	__in				size_t hw_cap_data_nbytes,
 	__in				uint32_t mask_sw,
+	__in_opt			efx_np_cap_filter_cb *filter_cb,
+	__in_opt			void *filter_arg,
 	__out				boolean_t *supportedp,
 	__out_opt			uint16_t *enum_hwp)
 {
@@ -1067,10 +1207,14 @@ efx_np_cap_sw_mask_to_hw_enum(
 			sw_check_mask |= flag_sw;
 
 			if ((hw_cap_data[byte_idx] & flag_hw) == flag_hw) {
-				mask_sw &= ~(flag_sw);
-
-				if (enum_hwp != NULL)
-					*enum_hwp = hw_sw_map->encm_hw;
+				if (filter_cb == NULL ||
+				    filter_cb(hw_sw_map->encm_hw, filter_arg) !=
+				    B_FALSE) {
+					mask_sw &= ~(flag_sw);
+
+					if (enum_hwp != NULL)
+						*enum_hwp = hw_sw_map->encm_hw;
+				}
 			}
 		}
 
@@ -1090,17 +1234,39 @@ efx_np_cap_sw_mask_to_hw_enum(
  * Convert (conceivably) the only EFX capability bit of the given mask to
  * the HW enum value, provided that the capability is supported by the HW,
  * where the latter follows from the given fraction of HW capability data.
+ *
+ * It is possible to use a callback to filter out certain mappings.
  */
 #define	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(					\
 	    _hw_sw_cap_map, _hw_cap_section, _hw_cap_data,		\
-	    _mask_sw, _supportedp, _enum_hwp)				\
+	    _mask_sw, _filter_cb, _filter_arg, _supportedp, _enum_hwp)	\
 	efx_np_cap_sw_mask_to_hw_enum((_hw_sw_cap_map),			\
 	    EFX_ARRAY_SIZE(_hw_sw_cap_map),				\
 	    MCDI_STRUCT_MEMBER((_hw_cap_data), const uint8_t,		\
 		    MC_CMD_##_hw_cap_section),				\
 	    MC_CMD_##_hw_cap_section##_LEN, (_mask_sw),			\
+	    (_filter_cb), (_filter_arg),				\
 	    (_supportedp), (_enum_hwp))
 
+static					boolean_t
+efx_np_filter_tech_by_lane_count_cb(
+	__in				uint16_t enum_hw,
+	__in				void *arg)
+{
+	efx_phy_lane_count_t lane_count = *((efx_phy_lane_count_t *)arg);
+
+	if (lane_count == EFX_PHY_LANE_COUNT_DEFAULT)
+		return B_TRUE;
+
+	if (enum_hw >= EFX_ARRAY_SIZE(efx_np_tech_to_lane_count))
+		return B_FALSE;
+
+	if (efx_np_tech_to_lane_count[enum_hw] != lane_count)
+		return B_FALSE;
+
+	return B_TRUE;
+}
+
 	__checkReturn	efx_rc_t
 efx_np_link_ctrl(
 	__in		efx_nic_t *enp,
@@ -1108,6 +1274,7 @@ efx_np_link_ctrl(
 	__in		const uint8_t *cap_data_raw,
 	__in		efx_link_mode_t loopback_link_mode,
 	__in		efx_loopback_type_t loopback_mode,
+	__in		efx_phy_lane_count_t lane_count,
 	__in		uint32_t cap_mask_sw,
 	__in		boolean_t fcntl_an)
 {
@@ -1176,12 +1343,13 @@ efx_np_link_ctrl(
 	} else if (cap_mask_sw & (1U << EFX_PHY_CAP_AN)) {
 		EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_tech,
 		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    efx_np_filter_tech_by_lane_count_cb, &lane_count,
 		    cap_mask_hw_techp);
 
 		if (fcntl_an != B_FALSE) {
 			EFX_NP_CAP_MASK_SW_TO_HW(efx_np_cap_map_pause,
 			    ETH_AN_FIELDS_PAUSE_MASK, cap_data_raw, cap_mask_sw,
-			    cap_mask_hw_pausep);
+			    NULL, NULL, cap_mask_hw_pausep);
 		}
 
 		flags |= 1U << MC_CMD_LINK_FLAGS_AUTONEG_EN;
@@ -1189,6 +1357,7 @@ efx_np_link_ctrl(
 	} else {
 		EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_tech,
 		    ETH_AN_FIELDS_TECH_MASK, cap_data_raw, cap_mask_sw,
+		    efx_np_filter_tech_by_lane_count_cb, &lane_count,
 		    &supported, &link_tech);
 
 		if (supported == B_FALSE) {
@@ -1209,7 +1378,7 @@ efx_np_link_ctrl(
 	 */
 	EFX_NP_CAP_SW_MASK_TO_HW_ENUM(efx_np_cap_map_fec_req,
 	    ETH_AN_FIELDS_FEC_REQ, cap_data_raw, cap_mask_sw,
-	    &supported, &cap_enum_hw);
+	    NULL, NULL, &supported, &cap_enum_hw);
 
 	if ((cap_mask_sw & EFX_PHY_CAP_FEC_MASK) != 0 && supported == B_FALSE) {
 		rc = ENOTSUP;
diff --git a/drivers/common/sfc_efx/base/efx_phy.c b/drivers/common/sfc_efx/base/efx_phy.c
index e3b9d20d59..1f99c72e62 100644
--- a/drivers/common/sfc_efx/base/efx_phy.c
+++ b/drivers/common/sfc_efx/base/efx_phy.c
@@ -262,6 +262,12 @@ efx_phy_adv_cap_set(
 		goto fail1;
 	}
 
+	if (efx_np_supported(enp) == B_FALSE &&
+	    epp->ep_np_lane_count_req != EFX_PHY_LANE_COUNT_DEFAULT) {
+		rc = ENOTSUP;
+		goto fail2;
+	}
+
 	if (epp->ep_adv_cap_mask == mask)
 		goto done;
 
@@ -269,13 +275,13 @@ efx_phy_adv_cap_set(
 	epp->ep_adv_cap_mask = mask;
 
 	if ((rc = epop->epo_reconfigure(enp)) != 0)
-		goto fail2;
+		goto fail3;
 
 done:
 	return (0);
 
-fail2:
-	EFSYS_PROBE(fail2);
+fail3:
+	EFSYS_PROBE(fail3);
 
 	epp->ep_adv_cap_mask = old_mask;
 	/* Reconfigure for robustness */
@@ -287,6 +293,9 @@ efx_phy_adv_cap_set(
 		EFSYS_ASSERT(0);
 	}
 
+fail2:
+	EFSYS_PROBE(fail2);
+
 fail1:
 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
 
@@ -306,6 +315,53 @@ efx_phy_lp_cap_get(
 	*maskp = epp->ep_lp_cap_mask;
 }
 
+	__checkReturn	efx_rc_t
+efx_phy_lane_count_set(
+	__in		efx_nic_t *enp,
+	__in		efx_phy_lane_count_t lane_count)
+{
+	efx_port_t *epp = &(enp->en_port);
+	const efx_phy_ops_t *epop = epp->ep_epop;
+	efx_phy_lane_count_t lane_count_prev = epp->ep_np_lane_count_req;
+	efx_rc_t rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+
+	if (lane_count == lane_count_prev)
+		return 0;
+
+	if (efx_np_supported(enp) == B_FALSE) {
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
+	if (lane_count >= EFX_PHY_LANE_COUNT_NTYPES) {
+		rc = EINVAL;
+		goto fail2;
+	}
+
+	epp->ep_np_lane_count_req = lane_count;
+
+	rc = epop->epo_reconfigure(enp);
+	if (rc != 0) {
+		epp->ep_np_lane_count_req = lane_count_prev;
+		goto fail3;
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+	return (rc);
+}
+
 	__checkReturn	efx_rc_t
 efx_phy_oui_get(
 	__in		efx_nic_t *enp,
diff --git a/drivers/common/sfc_efx/base/efx_port.c b/drivers/common/sfc_efx/base/efx_port.c
index 389efb2fe9..7e514e92dd 100644
--- a/drivers/common/sfc_efx/base/efx_port.c
+++ b/drivers/common/sfc_efx/base/efx_port.c
@@ -26,6 +26,7 @@ efx_port_init(
 
 	enp->en_mod_flags |= EFX_MOD_PORT;
 
+	epp->ep_np_lane_count_req = EFX_PHY_LANE_COUNT_DEFAULT;
 	epp->ep_mac_type = EFX_MAC_INVALID;
 	epp->ep_link_mode = EFX_LINK_UNKNOWN;
 	epp->ep_mac_drain = B_TRUE;
diff --git a/drivers/common/sfc_efx/base/medford4_phy.c b/drivers/common/sfc_efx/base/medford4_phy.c
index cc4e77587b..9ba6dfbc10 100644
--- a/drivers/common/sfc_efx/base/medford4_phy.c
+++ b/drivers/common/sfc_efx/base/medford4_phy.c
@@ -43,6 +43,7 @@ medford4_phy_get_link(
 
 	elsp->epls.epls_adv_cap_mask = ls.enls_adv_cap_mask;
 	elsp->epls.epls_lp_cap_mask = ls.enls_lp_cap_mask;
+	elsp->epls.epls_lane_count = ls.enls_lane_count;
 	elsp->els_loopback = ls.enls_loopback;
 
 	rc = efx_np_mac_state(enp, nph, &ms);
@@ -115,8 +116,8 @@ medford4_phy_reconfigure(
 #endif /* EFSYS_OPT_LOOPBACK */
 
 	rc = efx_np_link_ctrl(enp, epp->ep_np_handle, epp->ep_np_cap_data_raw,
-		    loopback_link_mode, loopback, epp->ep_adv_cap_mask,
-		    epp->ep_fcntl_autoneg);
+		    loopback_link_mode, loopback, epp->ep_np_lane_count_req,
+		    epp->ep_adv_cap_mask, epp->ep_fcntl_autoneg);
 	if (rc != 0)
 		goto fail2;
 
diff --git a/drivers/common/sfc_efx/sfc_base_symbols.c b/drivers/common/sfc_efx/sfc_base_symbols.c
index 0e74034031..bbb6f39924 100644
--- a/drivers/common/sfc_efx/sfc_base_symbols.c
+++ b/drivers/common/sfc_efx/sfc_base_symbols.c
@@ -195,6 +195,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(efx_nic_dma_map)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_verify)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_adv_cap_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_adv_cap_set)
+RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_lane_count_set)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_lp_cap_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_oui_get)
 RTE_EXPORT_INTERNAL_SYMBOL(efx_phy_media_type_get)
-- 
2.39.5

[PATCH v2 44/45] net/sfc: add support for control of physical port lane count

[Ivan Malov]

Since 24.11, DPDK has supported APIs to control lane count of the
physical link. Provide driver-level support for that on adaptors that
are netport MCDI capabale (Medford4, for instance).

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
Reviewed-by: Andy Moreton <andy.moreton@amd.com>
Reviewed-by: Pieter Jansen Van Vuuren <pieter.jansen-van-vuuren@amd.com>
---
 drivers/net/sfc/sfc.h        |   2 +
 drivers/net/sfc/sfc_ethdev.c | 147 +++++++++++++++++++++++++++++++++++
 drivers/net/sfc/sfc_port.c   |  19 +++++
 3 files changed, 168 insertions(+)

diff --git a/drivers/net/sfc/sfc.h b/drivers/net/sfc/sfc.h
index 819ce52529..af32ccfaa3 100644
--- a/drivers/net/sfc/sfc.h
+++ b/drivers/net/sfc/sfc.h
@@ -67,6 +67,8 @@ struct sfc_dp_rx;
 struct sfc_port {
 	unsigned int			lsc_seq;
 
+	efx_phy_lane_count_t		phy_lane_count_active;
+	efx_phy_lane_count_t		phy_lane_count_req;
 	uint32_t			phy_adv_cap_mask;
 	uint32_t			phy_adv_cap;
 	uint32_t			fec_cfg;
diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index 80eb39e58d..2122d42847 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -291,6 +291,150 @@ sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 	return ret;
 }
 
+static int
+sfc_dev_speed_lanes_get(struct rte_eth_dev *dev, uint32_t *lane_countp)
+{
+	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	struct sfc_port *port;
+	int rc = 0;
+
+	if (lane_countp == NULL)
+		return -EINVAL;
+
+	sfc_adapter_lock(sa);
+	port = &sa->port;
+
+	if (sa->state != SFC_ETHDEV_STARTED) {
+		/* The API wants 'active' lanes, so it is safe to indicate 0. */
+		*lane_countp = 0;
+		goto unlock;
+	}
+
+	if (port->phy_lane_count_active == EFX_PHY_LANE_COUNT_DEFAULT) {
+		rc = ENOTSUP;
+		goto unlock;
+	}
+
+	*lane_countp = port->phy_lane_count_active;
+
+unlock:
+	sfc_adapter_unlock(sa);
+	return -rc;
+}
+
+static int
+sfc_dev_speed_lanes_set(struct rte_eth_dev *dev, uint32_t lane_count)
+{
+	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	int rc = 0;
+
+	sfc_adapter_lock(sa);
+
+	if (sa->state == SFC_ETHDEV_STARTED) {
+		rc = EBUSY;
+		goto unlock;
+	}
+
+	if (lane_count == 0) {
+		rc = EINVAL;
+		goto unlock;
+	}
+
+	sa->port.phy_lane_count_req = lane_count;
+
+unlock:
+	sfc_adapter_unlock(sa);
+	return -rc;
+}
+
+static int
+sfc_dev_speed_lane_cap_handle(const efx_nic_cfg_t *encp,
+			      efx_link_mode_t link_mode,
+			      unsigned int *nb_caps_to_fillp,
+			      struct rte_eth_speed_lanes_capa **capp)
+{
+	uint32_t lane_counts = encp->enc_phy_lane_counts[link_mode].ed_u32[0];
+	struct rte_eth_speed_lanes_capa *cap = *capp;
+	uint32_t speed;
+
+	if (lane_counts == 0) {
+		/*
+		 * The mask of supported lane counts for this link mode is
+		 * empty. Do not waste output entries for such link modes.
+		 */
+		return 0;
+	}
+
+	switch (link_mode) {
+	case EFX_LINK_1000FDX:
+		speed = RTE_ETH_SPEED_NUM_1G;
+		break;
+	case EFX_LINK_10000FDX:
+		speed = RTE_ETH_SPEED_NUM_10G;
+		break;
+	case EFX_LINK_25000FDX:
+		speed = RTE_ETH_SPEED_NUM_25G;
+		break;
+	case EFX_LINK_40000FDX:
+		speed = RTE_ETH_SPEED_NUM_40G;
+		break;
+	case EFX_LINK_50000FDX:
+		speed = RTE_ETH_SPEED_NUM_50G;
+		break;
+	case EFX_LINK_100000FDX:
+		speed = RTE_ETH_SPEED_NUM_100G;
+		break;
+	case EFX_LINK_200000FDX:
+		speed = RTE_ETH_SPEED_NUM_200G;
+		break;
+	default:
+		/* No lane counts for this link mode. */
+		return 0;
+	}
+
+	if (*nb_caps_to_fillp == 0) {
+		if (cap == NULL) {
+			/* Dry run. Indicate that an entry is available. */
+			return 1;
+		}
+
+		/* We have run out of space in the user output buffer. */
+		return 0;
+	}
+
+	cap->capa = lane_counts;
+	cap->speed = speed;
+
+	--(*nb_caps_to_fillp);
+	++(*capp);
+	return 1;
+}
+
+static int
+sfc_dev_speed_lanes_get_capa(struct rte_eth_dev *dev,
+			     struct rte_eth_speed_lanes_capa *caps,
+			     unsigned int nb_caps)
+{
+	struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
+	efx_link_mode_t i;
+	int ret = 0;
+
+	sfc_adapter_lock(sa);
+
+	if (sa->state < SFC_ETHDEV_INITIALIZED) {
+		ret = -ENODEV;
+		goto unlock;
+	}
+
+	for (i = 0; i < EFX_LINK_NMODES; ++i)
+		ret += sfc_dev_speed_lane_cap_handle(encp, i, &nb_caps, &caps);
+
+unlock:
+	sfc_adapter_unlock(sa);
+	return ret;
+}
+
 static int
 sfc_dev_stop(struct rte_eth_dev *dev)
 {
@@ -2759,6 +2903,9 @@ static const struct eth_dev_ops sfc_eth_dev_ops = {
 	.allmulticast_enable		= sfc_dev_allmulti_enable,
 	.allmulticast_disable		= sfc_dev_allmulti_disable,
 	.link_update			= sfc_dev_link_update,
+	.speed_lanes_get		= sfc_dev_speed_lanes_get,
+	.speed_lanes_set		= sfc_dev_speed_lanes_set,
+	.speed_lanes_get_capa		= sfc_dev_speed_lanes_get_capa,
 	.stats_get			= sfc_stats_get,
 	.stats_reset			= sfc_stats_reset,
 	.xstats_get			= sfc_xstats_get,
diff --git a/drivers/net/sfc/sfc_port.c b/drivers/net/sfc/sfc_port.c
index 0a31a394d5..e5a7b8358d 100644
--- a/drivers/net/sfc/sfc_port.c
+++ b/drivers/net/sfc/sfc_port.c
@@ -187,6 +187,7 @@ sfc_port_fill_mac_stats_info(struct sfc_adapter *sa)
 int
 sfc_port_start(struct sfc_adapter *sa)
 {
+	efx_phy_link_state_t link_state = {0};
 	struct sfc_port *port = &sa->port;
 	int rc;
 	uint32_t phy_adv_cap;
@@ -243,6 +244,20 @@ sfc_port_start(struct sfc_adapter *sa)
 	if (rc != 0)
 		goto fail_phy_adv_cap_set;
 
+	sfc_log_init(sa, "set phy lane count -- %s",
+		     (port->phy_lane_count_req == EFX_PHY_LANE_COUNT_DEFAULT) ?
+		     "let EFX pick default value" : "use custom value");
+	rc = efx_phy_lane_count_set(sa->nic, port->phy_lane_count_req);
+	if (rc != 0)
+		goto fail_phy_lane_count_set;
+
+	sfc_log_init(sa, "get phy lane count");
+	rc = efx_phy_link_state_get(sa->nic, &link_state);
+	if (rc != 0)
+		goto fail_phy_lane_count_get;
+
+	port->phy_lane_count_active = link_state.epls_lane_count;
+
 	sfc_log_init(sa, "set MAC PDU %u", (unsigned int)port->pdu);
 	rc = efx_mac_pdu_set(sa->nic, port->pdu);
 	if (rc != 0)
@@ -350,6 +365,8 @@ sfc_port_start(struct sfc_adapter *sa)
 fail_mac_filter_set:
 fail_mac_addr_set:
 fail_mac_pdu_set:
+fail_phy_lane_count_get:
+fail_phy_lane_count_set:
 fail_phy_adv_cap_set:
 fail_mac_fcntl_set:
 fail_mac_vlan_strip_set:
@@ -427,6 +444,8 @@ sfc_port_attach(struct sfc_adapter *sa)
 
 	sfc_log_init(sa, "entry");
 
+	port->phy_lane_count_req = EFX_PHY_LANE_COUNT_DEFAULT;
+
 	efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM, &port->phy_adv_cap_mask);
 
 	/* Enable flow control by default */
-- 
2.39.5

[PATCH v2 45/45] doc: advertise support for AMD Solarflare X45xx adapters

[Ivan Malov]

The two NICs, X4522 and X4542, are based on EF10 architecture.

Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
---
 doc/guides/nics/sfc_efx.rst            | 9 ++++++++-
 doc/guides/rel_notes/release_25_07.rst | 4 ++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/sfc_efx.rst b/doc/guides/nics/sfc_efx.rst
index eafb88191a..4bd9f8c441 100644
--- a/doc/guides/nics/sfc_efx.rst
+++ b/doc/guides/nics/sfc_efx.rst
@@ -10,7 +10,8 @@ Solarflare libefx-based Poll Mode Driver
 
 The SFC EFX PMD (**librte_net_sfc_efx**) provides poll mode driver support
 for **Solarflare SFN7xxx and SFN8xxx** family of 10/40 Gbps adapters,
-**Solarflare XtremeScale X2xxx** family of 10/25/40/50/100 Gbps adapters and
+**Solarflare XtremeScale X2xxx** family of 10/25/40/50/100 Gbps adapters,
+**Solarflare X45xx** family of 10/25/40/50/100 Gbps adapters and
 **Alveo SN1000 SmartNICs** family of 10/25/40/50/100 Gbps adapters.
 SFC EFX PMD has support for the latest Linux and FreeBSD operating systems.
 
@@ -21,6 +22,12 @@ More information can be found at `Solarflare Communications website
 Supported NICs
 --------------
 
+- AMD Solarflare Adapters:
+
+   - AMD Solarflare X4522 Dual Port SFP56 Adapter
+
+   - AMD Solarflare X4542 Dual Port QSFP56 Adapter
+
 - Xilinx Adapters:
 
    - Alveo SN1022 SmartNIC
diff --git a/doc/guides/rel_notes/release_25_07.rst b/doc/guides/rel_notes/release_25_07.rst
index b8b56510f8..467536fe05 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -60,6 +60,10 @@ New Features
   Added a new network PMD which supports Mucse 10 Gigabit Ethernet NICs.
   See the :doc:`../nics/rnp` for more details.
 
+* **Updated Solarflare network PMD.**
+
+  Added support for AMD Solarflare X45xx adapters.
+
 
 Removed Items
 -------------
-- 
2.39.5

Re: [PATCH v2 45/45] doc: advertise support for AMD Solarflare X45xx adapters

[Andrew Rybchenko]

On 4/23/25 19:00, Ivan Malov wrote:
> The two NICs, X4522 and X4542, are based on EF10 architecture.
> 
> Signed-off-by: Ivan Malov <ivan.malov@arknetworks.am>
> ---
>   doc/guides/nics/sfc_efx.rst            | 9 ++++++++-
>   doc/guides/rel_notes/release_25_07.rst | 4 ++++
>   2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/doc/guides/nics/sfc_efx.rst b/doc/guides/nics/sfc_efx.rst
> index eafb88191a..4bd9f8c441 100644
> --- a/doc/guides/nics/sfc_efx.rst
> +++ b/doc/guides/nics/sfc_efx.rst
> @@ -10,7 +10,8 @@ Solarflare libefx-based Poll Mode Driver
>   
>   The SFC EFX PMD (**librte_net_sfc_efx**) provides poll mode driver support
>   for **Solarflare SFN7xxx and SFN8xxx** family of 10/40 Gbps adapters,
> -**Solarflare XtremeScale X2xxx** family of 10/25/40/50/100 Gbps adapters and
> +**Solarflare XtremeScale X2xxx** family of 10/25/40/50/100 Gbps adapters,
> +**Solarflare X45xx** family of 10/25/40/50/100 Gbps adapters and

Shouldn't 200 be added above?

>   **Alveo SN1000 SmartNICs** family of 10/25/40/50/100 Gbps adapters.
>   SFC EFX PMD has support for the latest Linux and FreeBSD operating systems.
>   
> @@ -21,6 +22,12 @@ More information can be found at `Solarflare Communications website
>   Supported NICs
>   --------------
>   
> +- AMD Solarflare Adapters:
> +
> +   - AMD Solarflare X4522 Dual Port SFP56 Adapter
> +
> +   - AMD Solarflare X4542 Dual Port QSFP56 Adapter
> +
>   - Xilinx Adapters:
>   
>      - Alveo SN1022 SmartNIC
> diff --git a/doc/guides/rel_notes/release_25_07.rst b/doc/guides/rel_notes/release_25_07.rst
> index b8b56510f8..467536fe05 100644
> --- a/doc/guides/rel_notes/release_25_07.rst
> +++ b/doc/guides/rel_notes/release_25_07.rst
> @@ -60,6 +60,10 @@ New Features
>     Added a new network PMD which supports Mucse 10 Gigabit Ethernet NICs.
>     See the :doc:`../nics/rnp` for more details.
>   
> +* **Updated Solarflare network PMD.**
> +
> +  Added support for AMD Solarflare X45xx adapters.
> +
>   
>   Removed Items
>   -------------

Re: [PATCH v2 00/45] Support AMD Solarflare X45xx adaptors

[Andrew Rybchenko]

On 4/23/25 18:59, Ivan Malov wrote:
> New X4522 (dual port SFP56) and X4542 (dual port QSFP56) adaptors are
> Medford4 (X4) chips that are based on EF10 architecture. An X4 NIC
> supports multiple network engine types. This series provides support
> only for the Medford2-alike, 'full-feature' (FF) network engine. This
> shall not be confused with the concept of 'datapath FW variants': the
> FF network engine supports both 'full-feature' and 'ultra-low-latency'
> datapath FW variants, with corresponding Medford2-alike feature sets.
> 
> The first part of the series provides general support for the adaptors,
> whilst the second one adds support for the new management controller
> interface for configuration of network port features (netport MCDI).
> 
> For now, only support for physical functions (PFs) is concerned. There
> is a small number of TODO and FIXME markings in the code. Those are
> normal at this development stage and will be removed by future patches
> when VF support has fleshed out.
> 
> v2:
> - squashed respective parts of commit [1] into commits [2] and [3]
> - dropped irrelevant TODO and FIXME markings from the patches
> - applied review notes and tested build in FreeBSD14-64
> 
> [1] https://mails.dpdk.org/archives/dev/2025-April/317109.html
> [2] https://mails.dpdk.org/archives/dev/2025-April/317096.html
> [3] https://mails.dpdk.org/archives/dev/2025-April/317098.html
> 
> 
> Andy Moreton (2):
>    net/sfc: add Medford4 with only full feature datapath engine
>    common/sfc_efx/base: add port mode for 8 port hardware
> 
> Denis Pryazhennikov (15):
>    common/sfc_efx/base: add Medford4 PCI IDs to common code
>    common/sfc_efx/base: add efsys option for Medford4
>    common/sfc_efx/base: add Medford4 support to NIC module
>    common/sfc_efx/base: add Medford4 support to EV module
>    common/sfc_efx/base: add Medford4 support to FILTER module
>    common/sfc_efx/base: add Medford4 support to INTR module
>    common/sfc_efx/base: add Medford4 support to MAC module
>    common/sfc_efx/base: add Medford4 support to PHY module
>    common/sfc_efx/base: add Medford4 support to TUNNEL module
>    common/sfc_efx/base: add Medford4 support to MCDI module
>    common/sfc_efx/base: add Medford4 support to Rx module
>    common/sfc_efx/base: add Medford4 support to Tx module
>    drivers: enable support for AMD Solarflare X4 adapter family
>    common/sfc_efx/base: add new X4 port mode
>    common/sfc_efx/base: extend list of supported X4 port modes
> 
> Ivan Malov (28):
>    common/sfc_efx/base: update MCDI headers
>    common/sfc_efx/base: provide a stub for basic netport attach
>    common/sfc_efx/base: provide defaults on netport attach path
>    common/sfc_efx/base: obtain assigned netport handle from NIC
>    common/sfc_efx/base: allow for const in MCDI struct accessor
>    common/sfc_efx/base: get netport fixed capabilities on probe
>    common/sfc_efx/base: decode netport link state on probe path
>    common/sfc_efx/base: fill in loopback modes on netport probe
>    common/sfc_efx/base: introduce Medford4 stub for PHY methods
>    common/sfc_efx/base: refactor EF10 link mode decoding helper
>    common/sfc_efx/base: provide PHY link get method on Medford4
>    common/sfc_efx/base: implement PHY link control for Medford4
>    common/sfc_efx/base: introduce Medford4 stub for MAC methods
>    common/sfc_efx/base: add MAC reconfigure method for Medford4
>    common/sfc_efx/base: fill in software LUT for MAC statistics
>    common/sfc_efx/base: fill in MAC statistics mask on Medford4
>    common/sfc_efx/base: support MAC statistics on Medford4 NICs
>    common/sfc_efx/base: implement MAC PDU controls for Medford4
>    common/sfc_efx/base: correct MAC PDU calculation on Medford4
>    net/sfc: make use of generic EFX MAC PDU calculation helpers
>    common/sfc_efx/base: ignore legacy link events on new boards
>    common/sfc_efx/base: add link event processing on new boards
>    net/sfc: query link status on link change events on new NICs
>    common/sfc_efx/base: subscribe to netport link change events
>    net/sfc: offer support for 200G link ability on new adaptors
>    common/sfc_efx/base: support controls for netport lane count
>    net/sfc: add support for control of physical port lane count
>    doc: advertise support for AMD Solarflare X45xx adapters
> 
>   .mailmap                                      |    3 +-
>   doc/guides/nics/sfc_efx.rst                   |    9 +-
>   doc/guides/rel_notes/release_25_07.rst        |    4 +
>   drivers/common/sfc_efx/base/ef10_ev.c         |   39 +
>   drivers/common/sfc_efx/base/ef10_impl.h       |   19 +
>   drivers/common/sfc_efx/base/ef10_nic.c        |   93 +-
>   drivers/common/sfc_efx/base/ef10_phy.c        |   43 +-
>   drivers/common/sfc_efx/base/ef10_tlv_layout.h |    9 +-
>   drivers/common/sfc_efx/base/efx.h             |   98 +-
>   drivers/common/sfc_efx/base/efx_check.h       |   25 +-
>   drivers/common/sfc_efx/base/efx_ev.c          |    6 +
>   drivers/common/sfc_efx/base/efx_filter.c      |    6 +
>   drivers/common/sfc_efx/base/efx_impl.h        |  115 +-
>   drivers/common/sfc_efx/base/efx_intr.c        |    6 +
>   drivers/common/sfc_efx/base/efx_mac.c         |   56 +-
>   drivers/common/sfc_efx/base/efx_mcdi.c        |   18 +-
>   drivers/common/sfc_efx/base/efx_mcdi.h        |    2 +-
>   drivers/common/sfc_efx/base/efx_nic.c         |   60 +
>   drivers/common/sfc_efx/base/efx_np.c          | 1591 +++++
>   drivers/common/sfc_efx/base/efx_phy.c         |   88 +-
>   drivers/common/sfc_efx/base/efx_port.c        |    1 +
>   drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5868 ++++++++++++++++-
>   drivers/common/sfc_efx/base/efx_rx.c          |    6 +
>   drivers/common/sfc_efx/base/efx_tunnel.c      |   18 +-
>   drivers/common/sfc_efx/base/efx_tx.c          |   33 +
>   drivers/common/sfc_efx/base/medford4_impl.h   |  105 +
>   drivers/common/sfc_efx/base/medford4_mac.c    |  286 +
>   drivers/common/sfc_efx/base/medford4_phy.c    |  156 +
>   drivers/common/sfc_efx/base/meson.build       |    3 +
>   drivers/common/sfc_efx/efsys.h                |    2 +
>   drivers/common/sfc_efx/sfc_base_symbols.c     |    2 +
>   drivers/net/sfc/sfc.c                         |    5 +-
>   drivers/net/sfc/sfc.h                         |    4 +
>   drivers/net/sfc/sfc_dp_tx.h                   |    3 +
>   drivers/net/sfc/sfc_ef10_tx.c                 |   13 +-
>   drivers/net/sfc/sfc_ethdev.c                  |  186 +-
>   drivers/net/sfc/sfc_ev.c                      |   51 +-
>   drivers/net/sfc/sfc_port.c                    |   27 +-
>   drivers/net/sfc/sfc_repr.c                    |    7 +-
>   drivers/net/sfc/sfc_repr.h                    |    1 +
>   drivers/net/sfc/sfc_tx.c                      |    2 +
>   41 files changed, 8944 insertions(+), 125 deletions(-)
>   create mode 100644 drivers/common/sfc_efx/base/efx_np.c
>   create mode 100644 drivers/common/sfc_efx/base/medford4_impl.h
>   create mode 100644 drivers/common/sfc_efx/base/medford4_mac.c
>   create mode 100644 drivers/common/sfc_efx/base/medford4_phy.c
> 

With few nits fixed
Series-acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>

Frankly speaking I'd squash trivial patches which add M4 support to
various modules inheriting ef10 ops.

Also it is always better to update documentation in patches with
corresponding code (when support is really added and starts to work).