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Sun, 27 Apr 2025 04:19:39 -0700 From: Maayan Kashani To: CC: , , , Viacheslav Ovsiienko , Bing Zhao , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH 2/2] net/mlx5: update devarg according to SWS support Date: Sun, 27 Apr 2025 14:19:15 +0300 Message-ID: <20250427111916.108276-2-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20250427111916.108276-1-mkashani@nvidia.com> References: <20250427111916.108276-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|SJ0PR12MB6853:EE_ X-MS-Office365-Filtering-Correlation-Id: 930e01b7-20c1-4d3c-d6c5-08dd857d69a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gVkZAtL8tQwxz3VGerz+OAnB2Wg2UY4NwuOKBALHS4/j/c+wuwQqke3BbMM6?= =?us-ascii?Q?Naq+Ucb2BWAKuF+hnKCUm4UCA3bgEdS0x5+kQVTLNgcMzWNsizgSNQgDgb4u?= =?us-ascii?Q?zy7+8yD60ZfSzTdveb+HzB8EmQUqzJq4EEoB9wJY/N1577vAnhU3vteKUg/J?= =?us-ascii?Q?OfKPLq8neY1mCvyJi7h7fuyXU7n+PGax+/fpTusSFKvwc0EWHODM09gHJ6V9?= =?us-ascii?Q?vFfLEt8cLfze3gOFYXTHKcc5qAfFUauZpABnd6paaYBoLKvLY3aCoMbaP/Be?= =?us-ascii?Q?MoFhm3GTc2pO93S4OPrakgLOITZhNJdkfF8TNyBfucyrrgjFjKoe1fW1f4YH?= =?us-ascii?Q?ncE5QkNdzL9oS9UlOEE0XyaAuEVDNxblnInB8XZE3sD9K++SP60aRDsGB4X7?= =?us-ascii?Q?+1/hYqepl1h8QVVkBmAggOiIRKgO+SPeVxxZNofsXx9sL6H5ohd+y++dDmC8?= =?us-ascii?Q?NFoRCkRpZ0jhgFxSjVeBkFXuxNVDtkFhZQSH+dVN2W6KtivDQ/UW0q4J/VTI?= =?us-ascii?Q?SCZa64kV8EtQ0N833C5qyedBg+IxMDPM6tsxjlc0vROTbJOCSb2ujK5AIKnE?= =?us-ascii?Q?ZBMzl7IY0w0xXcQSKfiPs1HoMHq0vILMoMj7cWjTFRMsdT/u9CskkCUJoh3o?= =?us-ascii?Q?EAACMwidYz4hGvZ6yWP+EnLqQ0/DlnkeOjoumI1AfKsvmpzRMj44tEH3PgPp?= =?us-ascii?Q?+a5RXb7eLTuP25tFH5gURB/Pt09HAhjpZC7AYG2+rvYqhzc3ZKfPAZTQIh7y?= =?us-ascii?Q?HF6t1hmjmtXFXQoIiiNL6qkJYuZC/fW/ly7dSPJrkaiIgBlnQHZz8LY7dFut?= =?us-ascii?Q?OpUmPNHiBMkhrL54bhXDdcMkB8Pj243vZcNONeXkMaEpLmVxrXyoXN0foOAP?= =?us-ascii?Q?Pr9TD4Hc0QBIp4YYcdYVQjyZOk+72PBXIZduVs0XoswX8w9QBBUSMv0vkY0n?= =?us-ascii?Q?Ssncc7ly4dVdGi00GOij9TVanPqrwzcdXs29LxMg+CY/veH8E3HMOl/COB7R?= =?us-ascii?Q?qw1NlUmP/akF7bijIGObqNBQKY5qSvk1oZBnCedzIiCcKD2uAnHXfn1lGpjV?= =?us-ascii?Q?SE5QlNW+kJakZ+M6FpphizQaix5zMcZ83DRQaRgjsk55UzfW49ihh4zHuVs3?= =?us-ascii?Q?OXKADvl7zmQeAg2zDWt/8jJ6gdoWxMWFo9e+9z1REsmKNaUpMkM6ltvqj3Q5?= =?us-ascii?Q?CEWdslxc8GQXxoOOsithugtkUIHqrY8ySx3LBezy24IEBXHC4ryvMP/CsPr+?= =?us-ascii?Q?Vs0Oliuin48v7X9ZkgHJ2c/nA/nnz+PHUchj+q2FUPF8cfASYihJTquxn9NA?= =?us-ascii?Q?aGSYTjGUxMpINPGtrwZ6l37PnodhcIp9LFZ+e9g6Z5C1LcpOhy58EYQGacmd?= =?us-ascii?Q?t9/yOrJJizaC4mkedkzI7px3mC0+EhajVeQmmU4dgp3TgWeb2YwzbI5NKAYK?= =?us-ascii?Q?25p/90gWTRPvaRGlhk8RB4U2+u26UH251bRpPjKSfVmMvd+GdkopNGEYkt5C?= =?us-ascii?Q?UDr4fEAhGBn8MJLo5j4m0J4yjpK6yedTYDJU?= X-Forefront-Antispam-Report: CIP:216.228.118.233; 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Update default for dv_flow_en/allow_duplicate_pattern devargs and return relevant error if user configuration is not supported. Signed-off-by: Maayan Kashani Acked-by: Dariusz Sosnowski --- doc/guides/nics/mlx5.rst | 10 +++++++--- drivers/net/mlx5/mlx5.c | 25 +++++++++++++++++++++++-- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 08f3648e993..3a8879939f9 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1546,8 +1546,11 @@ for an additional list of options shared with other mlx5 drivers. Value 2 enables the WQE based hardware steering. In this mode, only queue-based flow management is supported. - It is configured by default to 1 (DV flow steering) if supported. - Otherwise, the value is 0 which indicates legacy Verbs flow offloading. + Default configuration depends on HW capabilities: + + - If DV flow steering is supported, it will be set to 1. + - Otherwise, if HW steering is supported, it will be set to 2. + - Otherwise, PMD will fallback to legacy Verbs and it will be set to 0. - ``dv_esw_en`` parameter [int] @@ -1680,7 +1683,8 @@ for an additional list of options shared with other mlx5 drivers. In this case, all rules are inserted but only the first rule takes effect, the next rule takes effect only if the previous rules are deleted. - By default, the PMD will set this value to 1. + By default, the PMD will set this value according to capability + (For NICs supporting DV flow steering, it will be set 1. Otherwise, it will be set to 0.). Multiport E-Switch diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 646da8e846c..03f6db5ecd7 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1488,14 +1488,23 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, NULL, }; int ret = 0; + struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; + bool sws_is_supported = (attr->sw_owner || + (attr->sw_owner_v2 && + attr->steering_format_version <= MLX5_STEERING_LOGIC_FORMAT_CONNECTX_8)); /* Default configuration. */ memset(config, 0, sizeof(*config)); config->vf_nl_en = 1; config->dv_esw_en = 1; - config->dv_flow_en = 1; + if (sws_is_supported) { + config->dv_flow_en = 1; + config->allow_duplicate_pattern = 1; + } else { + config->dv_flow_en = 2; + config->allow_duplicate_pattern = 0; + } config->decap_en = 1; - config->allow_duplicate_pattern = 1; config->fdb_def_rule = 1; config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT; config->cnt_svc.service_core = rte_get_main_lcore(); @@ -1510,6 +1519,18 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, return -rte_errno; } } + if (!sws_is_supported) { + if (config->dv_flow_en == 1) { + DRV_LOG(ERR, "DV flow steering is not supported."); + rte_errno = ENODEV; + return -rte_errno; + } + if (config->allow_duplicate_pattern == 1) { + DRV_LOG(ERR, "Duplicate pattern is not allowed."); + rte_errno = ENODEV; + return -rte_errno; + } + } /* Adjust parameters according to device capabilities. */ if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { DRV_LOG(WARNING, "DV flow is not supported."); -- 2.21.0