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Sun, 27 Apr 2025 04:23:05 -0700 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14 via Frontend Transport; Sun, 27 Apr 2025 04:23:01 -0700 From: Maayan Kashani To: CC: , , , , Bing Zhao , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad , Gregory Etelson Subject: [PATCH 1/2] net/mlx5: non template - fix validation for GENEVE options Date: Sun, 27 Apr 2025 14:22:56 +0300 Message-ID: <20250427112257.108544-1-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C6:EE_|IA0PR12MB8325:EE_ X-MS-Office365-Filtering-Correlation-Id: 2daa60d9-9fe9-4905-eab6-08dd857de21b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2025 11:23:06.6115 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2daa60d9-9fe9-4905-eab6-08dd857de21b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8325 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For non-template API on top of HWS, geneve options parser is created by the pmd and not by the user, therefore during validation , the parser is not yet created. The fix is to ignore the validation of geneve options in case the rule is a non-template rule. The parser will be created later during rule create. Fixes: 80c676259a04 ("net/mlx5: validate HWS template items") Cc: stable@dpdk.org Signed-off-by: Maayan Kashani Acked-by: Bing Zhao --- drivers/net/mlx5/mlx5_flow_hw.c | 35 ++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 20d38ce4141..09157e30090 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8475,10 +8475,11 @@ struct mlx5_hw_pattern_validation_ctx { }; static int -flow_hw_pattern_validate(struct rte_eth_dev *dev, +__flow_hw_pattern_validate(struct rte_eth_dev *dev, const struct rte_flow_pattern_template_attr *attr, const struct rte_flow_item items[], uint64_t *item_flags, + bool nt_flow, struct rte_flow_error *error) { struct mlx5_priv *priv = dev->data->dev_private; @@ -8646,10 +8647,16 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_GENEVE_OPT: { last_item = MLX5_FLOW_LAYER_GENEVE_OPT; - ret = mlx5_flow_geneve_tlv_option_validate(priv, item, - error); - if (ret < 0) - return ret; + /* + * For non template the parser is internally created before + * the flow creation. + */ + if (!nt_flow) { + ret = mlx5_flow_geneve_tlv_option_validate(priv, item, + error); + if (ret < 0) + return ret; + } break; } case RTE_FLOW_ITEM_TYPE_COMPARE: @@ -8913,6 +8920,16 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]); } +static int +flow_hw_pattern_validate(struct rte_eth_dev *dev, + const struct rte_flow_pattern_template_attr *attr, + const struct rte_flow_item items[], + uint64_t *item_flags, + struct rte_flow_error *error) +{ + return __flow_hw_pattern_validate(dev, attr, items, item_flags, false, error); +} + /* * Verify that the tested flow patterns fits STE size limit in HWS group. * @@ -14252,8 +14269,8 @@ static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev, }; /* Validate application items only */ - ret = flow_hw_pattern_validate(dev, &pattern_template_attr, items, - &item_flags, error); + ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items, + &item_flags, true, error); if (ret < 0) return 0; @@ -15388,8 +15405,8 @@ flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, if (external) { /* Validate application items only */ - ret = flow_hw_pattern_validate(dev, &pattern_template_attr, items, - &item_flags, error); + ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items, + &item_flags, true, error); if (ret < 0) return -rte_errno; } -- 2.21.0