* [PATCH v1 0/7] event/dlb2: dlb2 hw resource management
@ 2025-05-09 4:20 Pravin Pathak
2025-05-09 4:20 ` [PATCH v1 1/7] event/dlb2: addresses deq failure when CQ depth <= 16 Pravin Pathak
0 siblings, 1 reply; 3+ messages in thread
From: Pravin Pathak @ 2025-05-09 4:20 UTC (permalink / raw)
To: dev
Cc: jerinj, mike.ximing.chen, bruce.richardson, thomas,
david.marchand, nipun.gupta, chenbox, tirthendu.sarkar,
Pravin Pathak
This patchset introduces various fixes related to dlb2 hw resource
management. The dlb2 hw has limited resources, which are configurable
using command line options. This patch allows managing History list,
scheduling bandwidth and credits using command line options. It also
fixes some issues with resources management.
Pravin Pathak (6):
event/dlb2: addresses deq failure when CQ depth <= 16
event/dlb2: changes to correctly validate COS ID arguments
event/dlb2: return 96 single link ports for DLB2.5
event/dlb2: support managing history list resource
event/dlb2: avoid credit release race condition
event/dlb2: update qid depth xstat in vector path
Tirthendu Sarkar (1):
event/dlb2: fix default credits in dlb2_eventdev_info_get()
drivers/event/dlb2/dlb2.c | 274 +++++++++++++++++----
drivers/event/dlb2/dlb2_iface.c | 5 +-
drivers/event/dlb2/dlb2_iface.h | 4 +-
drivers/event/dlb2/dlb2_priv.h | 20 +-
drivers/event/dlb2/dlb2_user.h | 24 ++
drivers/event/dlb2/pf/base/dlb2_regs.h | 9 +
drivers/event/dlb2/pf/base/dlb2_resource.c | 74 ++++++
drivers/event/dlb2/pf/base/dlb2_resource.h | 18 ++
drivers/event/dlb2/pf/dlb2_pf.c | 33 ++-
drivers/event/dlb2/rte_pmd_dlb2.c | 23 ++
drivers/event/dlb2/rte_pmd_dlb2.h | 40 +++
drivers/event/dlb2/version.map | 1 +
12 files changed, 463 insertions(+), 62 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v1 1/7] event/dlb2: addresses deq failure when CQ depth <= 16
2025-05-09 4:20 [PATCH v1 0/7] event/dlb2: dlb2 hw resource management Pravin Pathak
@ 2025-05-09 4:20 ` Pravin Pathak
0 siblings, 0 replies; 3+ messages in thread
From: Pravin Pathak @ 2025-05-09 4:20 UTC (permalink / raw)
To: dev
Cc: jerinj, mike.ximing.chen, bruce.richardson, thomas,
david.marchand, nipun.gupta, chenbox, tirthendu.sarkar,
Pravin Pathak
When application configures a DIR port with CQ depth less than 8, DLB PMD
sets port's cq_depth as 8 and token reservation is used to make the
effective cq_depth smaller. However, while setting port's cq_depth_mask
application configured CQ depth was used resulting in reading incorrect
cachelines while dequeuing. Use PMD calculated CQ depth for cq_depth_mask
calculation.
Signed-off-by: Pravin Pathak <pravin.pathak@intel.com>
Signed-off-by: Tirthendu Sarkar <tirthendu.sarkar@intel.com>
---
drivers/event/dlb2/dlb2.c | 4 ++--
drivers/event/dlb2/pf/dlb2_pf.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index 286241ea41..a0e673b96b 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -1951,9 +1951,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
qm_port->cq_idx_unmasked = 0;
if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
- qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
+ qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
else
- qm_port->cq_depth_mask = cfg.cq_depth - 1;
+ qm_port->cq_depth_mask = qm_port->cq_depth - 1;
qm_port->gen_bit_shift = rte_popcount32(qm_port->cq_depth_mask);
/* starting value of gen bit - it toggles at wrap time */
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
index ed4e6e424c..31b5487d85 100644
--- a/drivers/event/dlb2/pf/dlb2_pf.c
+++ b/drivers/event/dlb2/pf/dlb2_pf.c
@@ -400,7 +400,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
/* Calculate the port memory required, and round up to the nearest
* cache line.
*/
- alloc_sz = cfg->cq_depth * qe_sz;
+ alloc_sz = RTE_MAX(cfg->cq_depth, DLB2_MIN_HARDWARE_CQ_DEPTH) * qe_sz;
alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
port_base = dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz,
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v1 0/7] event/dlb2: dlb2 hw resource management
@ 2025-05-09 4:23 Pravin Pathak
0 siblings, 0 replies; 3+ messages in thread
From: Pravin Pathak @ 2025-05-09 4:23 UTC (permalink / raw)
To: dev
Cc: jerinj, mike.ximing.chen, bruce.richardson, thomas,
david.marchand, nipun.gupta, chenbox, tirthendu.sarkar,
Pravin Pathak
This patchset introduces various fixes related to dlb2 hw resource
management. The dlb2 hw has limited resources, which are configurable
using command line options. This patch allows managing History list,
scheduling bandwidth and credits using command line options. It also
fixes some issues with resources management.
Pravin Pathak (6):
event/dlb2: addresses deq failure when CQ depth <= 16
event/dlb2: changes to correctly validate COS ID arguments
event/dlb2: return 96 single link ports for DLB2.5
event/dlb2: support managing history list resource
event/dlb2: avoid credit release race condition
event/dlb2: update qid depth xstat in vector path
Tirthendu Sarkar (1):
event/dlb2: fix default credits in dlb2_eventdev_info_get()
drivers/event/dlb2/dlb2.c | 274 +++++++++++++++++----
drivers/event/dlb2/dlb2_iface.c | 5 +-
drivers/event/dlb2/dlb2_iface.h | 4 +-
drivers/event/dlb2/dlb2_priv.h | 20 +-
drivers/event/dlb2/dlb2_user.h | 24 ++
drivers/event/dlb2/pf/base/dlb2_regs.h | 9 +
drivers/event/dlb2/pf/base/dlb2_resource.c | 74 ++++++
drivers/event/dlb2/pf/base/dlb2_resource.h | 18 ++
drivers/event/dlb2/pf/dlb2_pf.c | 33 ++-
drivers/event/dlb2/rte_pmd_dlb2.c | 23 ++
drivers/event/dlb2/rte_pmd_dlb2.h | 40 +++
drivers/event/dlb2/version.map | 1 +
12 files changed, 463 insertions(+), 62 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-05-09 4:24 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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