From: Pravin Pathak <pravin.pathak@intel.com>
To: dev@dpdk.org
Cc: jerinj@marvell.com, mike.ximing.chen@intel.com,
bruce.richardson@intel.com, thomas@monjalon.net,
david.marchand@redhat.com, nipun.gupta@amd.com,
chenbox@nvidia.com, tirthendu.sarkar@intel.com,
Pravin Pathak <pravin.pathak@intel.com>
Subject: [PATCH v1 6/7] event/dlb2: update qid depth xstat in vector path
Date: Thu, 8 May 2025 23:24:00 -0500 [thread overview]
Message-ID: <20250509042401.2634765-7-pravin.pathak@intel.com> (raw)
In-Reply-To: <20250509042401.2634765-1-pravin.pathak@intel.com>
update QID depth xstats counter in vector dequeue path
Signed-off-by: Pravin Pathak <pravin.pathak@intel.com>
---
drivers/event/dlb2/dlb2.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index 5f3b816665..19fe973bff 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -4138,6 +4138,8 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port,
_mm_storeu_si128((__m128i *)&events[3], v_ev_3);
DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched3],
1);
+ DLB2_INC_STAT(qm_port->ev_port->stats.queue[ev_qid3].\
+ qid_depth[RTE_PMD_DLB2_GET_QID_DEPTH(&events[3])], 1);
/* fallthrough */
case 3:
v_ev_2 = _mm_unpacklo_epi64(v_unpk_ev_23, v_qe_2);
@@ -4145,6 +4147,8 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port,
_mm_storeu_si128((__m128i *)&events[2], v_ev_2);
DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched2],
1);
+ DLB2_INC_STAT(qm_port->ev_port->stats.queue[ev_qid2].\
+ qid_depth[RTE_PMD_DLB2_GET_QID_DEPTH(&events[2])], 1);
/* fallthrough */
case 2:
v_ev_1 = _mm_blend_epi16(v_unpk_ev_01, v_qe_1, 0x0F);
@@ -4153,6 +4157,8 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port,
_mm_storeu_si128((__m128i *)&events[1], v_ev_1);
DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched1],
1);
+ DLB2_INC_STAT(qm_port->ev_port->stats.queue[ev_qid1].\
+ qid_depth[RTE_PMD_DLB2_GET_QID_DEPTH(&events[1])], 1);
/* fallthrough */
case 1:
v_ev_0 = _mm_unpacklo_epi64(v_unpk_ev_01, v_qe_0);
@@ -4160,6 +4166,8 @@ _process_deq_qes_vec_impl(struct dlb2_port *qm_port,
_mm_storeu_si128((__m128i *)&events[0], v_ev_0);
DLB2_INC_STAT(qm_port->ev_port->stats.rx_sched_cnt[hw_sched0],
1);
+ DLB2_INC_STAT(qm_port->ev_port->stats.queue[ev_qid0].\
+ qid_depth[RTE_PMD_DLB2_GET_QID_DEPTH(&events[0])], 1);
}
qm_port->reorder_id += valid_events;
}
--
2.25.1
next prev parent reply other threads:[~2025-05-09 4:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 4:23 [PATCH v1 0/7] event/dlb2: dlb2 hw resource management Pravin Pathak
2025-05-09 4:23 ` [PATCH v1 1/7] event/dlb2: addresses deq failure when CQ depth <= 16 Pravin Pathak
2025-05-09 4:23 ` [PATCH v1 2/7] event/dlb2: changes to correctly validate COS ID arguments Pravin Pathak
2025-05-09 4:23 ` [PATCH v1 3/7] event/dlb2: return 96 single link ports for DLB2.5 Pravin Pathak
2025-05-09 4:23 ` [PATCH v1 4/7] event/dlb2: support managing history list resource Pravin Pathak
2025-05-09 4:23 ` [PATCH v1 5/7] event/dlb2: avoid credit release race condition Pravin Pathak
2025-05-09 4:24 ` Pravin Pathak [this message]
2025-05-09 4:24 ` [PATCH v1 7/7] event/dlb2: fix default credits in dlb2_eventdev_info_get() Pravin Pathak
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