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From: Rahul Bhansali <rbhansali@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
	Kiran Kumar K <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>,
	Harman Kalra <hkalra@marvell.com>
Cc: <jerinj@marvell.com>, Rahul Bhansali <rbhansali@marvell.com>
Subject: [PATCH 3/6] common/cnxk: update CPT parse header for O20
Date: Mon, 19 May 2025 18:24:21 +0530	[thread overview]
Message-ID: <20250519125424.1435140-3-rbhansali@marvell.com> (raw)
In-Reply-To: <20250519125424.1435140-1-rbhansali@marvell.com>

Updates CPT parse header HW structure for O20.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/hw/cpt.h        | 12 +++++++-----
 drivers/common/cnxk/roc_cpt_debug.c |  8 ++++----
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 40987abbb9..e542f3a3d4 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -358,11 +358,11 @@ union cpt_parse_hdr_u {
 			struct {
 				uint64_t rsvd_134_128 : 7;
 				uint64_t pkt_inline : 1;
-				uint64_t new_pkt_aura : 20;
+				uint64_t rsvd_155_136 : 20;
 				uint64_t orig_pkt_aura : 20;
 				uint64_t il3_off : 8;
-				uint64_t ptr_pad : 3;
-				uint64_t ptr_offset : 5;
+				uint64_t ptr_pad : 5;
+				uint64_t ptr_offset : 3;
 			};
 		} w2;
 
@@ -383,10 +383,12 @@ union cpt_parse_hdr_u {
 			uint64_t u64;
 			struct {
 				uint32_t l4_chksum;
-				uint32_t l4_chksum_type : 1;
-				uint32_t rsvd_298_289 : 10;
+				uint32_t l4_chksum_type : 2;
+				uint32_t rsvd_292_290 : 3;
 				uint32_t channel : 12;
+				uint32_t rsvd_308_305 : 4;
 				uint32_t sctr_size : 4;
+				uint32_t rsvd_314_313 : 2;
 				uint32_t gthr_size : 5;
 			};
 		} w4;
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 35a2cf6b3a..28aedf088e 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -36,8 +36,8 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
 	cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t", cpth->wqe_ptr);
 
 	/* W2 */
-	cpt_dump(file, "W2: pkt_inline \t0x%x\t\tnew_pkt_aura \t0x%x\t\torig_pkt_aura \t0x%x",
-		 cpth->w2.pkt_inline, cpth->w2.new_pkt_aura, cpth->w2.orig_pkt_aura);
+	cpt_dump(file, "W2: pkt_inline \t0x%x\t\torig_pkt_aura \t0x%x", cpth->w2.pkt_inline,
+		 cpth->w2.orig_pkt_aura);
 	cpt_dump(file, "W2: il3_off \t0x%x\t\tptr_pad \t0x%x \t", cpth->w2.il3_off,
 		 cpth->w2.ptr_pad);
 	cpt_dump(file, "W2: ptr_offset \t0x%x \t", cpth->w2.ptr_offset);
@@ -53,9 +53,9 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
 	cpt_dump(file, "W4: channel \t0x%x\t\tsctr_size \t0x%08x\t\tgthr_size \t0x%08x",
 		 cpth->w4.channel, cpth->w4.sctr_size, cpth->w4.gthr_size);
 
-	/* offset of 0 implies 256B, otherwise it implies offset*8B */
+	/* offset of 0 implies 256B, otherwise it implies offset*32B */
 	offset = cpth->w2.ptr_offset;
-	offset = (((offset - 1) & 0x1f) + 1) * 8;
+	offset = (((offset - 1) & 0x7) + 1) * 32;
 	frag_info = PLT_PTR_ADD(cpth, offset);
 
 	if (cpth->w0.num_frags > 0) {
-- 
2.25.1


  parent reply	other threads:[~2025-05-19 12:54 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
2025-05-19 12:54 ` [PATCH 2/6] common/cnxk: config CPT result address for cn20k Rahul Bhansali
2025-05-19 12:54 ` Rahul Bhansali [this message]
2025-05-19 12:54 ` [PATCH 4/6] common/cnxk: update inbound CPT LF ID Rahul Bhansali
2025-05-19 12:54 ` [PATCH 5/6] net/cnxk: update frag offset calculation Rahul Bhansali
2025-05-19 12:54 ` [PATCH 6/6] net/cnxk: update bufsize in lookup memory Rahul Bhansali

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