From: Rahul Bhansali <rbhansali@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>
Cc: <jerinj@marvell.com>, Rahul Bhansali <rbhansali@marvell.com>
Subject: [PATCH 5/6] net/cnxk: update frag offset calculation
Date: Mon, 19 May 2025 18:24:23 +0530 [thread overview]
Message-ID: <20250519125424.1435140-5-rbhansali@marvell.com> (raw)
In-Reply-To: <20250519125424.1435140-1-rbhansali@marvell.com>
Update frag offset calculation based on CSR change.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/net/cnxk/cn20k_rx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index 09042e384d..5682631815 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -337,7 +337,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
cq_w5 = *((const uint64_t *)rx + 4);
len = rlen + ((cq_w5 >> 16) & 0xFF) - (cq_w5 & 0xFF);
num_frags = hdr->w0.num_frags;
- sg_base = cpth + (offset ? (offset << 3) : 256);
+ sg_base = cpth + (offset ? (offset << 5) : 256);
finfo = (const struct cpt_frag_info_s *)sg_base;
sg_base += num_frags ? (num_frags > 4 ? 32 : 16) : 0;
sg = *(uint64_t *)sg_base;
--
2.25.1
next prev parent reply other threads:[~2025-05-19 12:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
2025-05-19 12:54 ` [PATCH 2/6] common/cnxk: config CPT result address for cn20k Rahul Bhansali
2025-05-19 12:54 ` [PATCH 3/6] common/cnxk: update CPT parse header for O20 Rahul Bhansali
2025-05-19 12:54 ` [PATCH 4/6] common/cnxk: update inbound CPT LF ID Rahul Bhansali
2025-05-19 12:54 ` Rahul Bhansali [this message]
2025-05-19 12:54 ` [PATCH 6/6] net/cnxk: update bufsize in lookup memory Rahul Bhansali
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