* [PATCH 2/6] common/cnxk: config CPT result address for cn20k
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
@ 2025-05-19 12:54 ` Rahul Bhansali
2025-05-19 12:54 ` [PATCH 3/6] common/cnxk: update CPT parse header for O20 Rahul Bhansali
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Rahul Bhansali @ 2025-05-19 12:54 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
This configures the CPT result address offset from WQE pointer
in RX_INLINE_CFG0. CPT result address offset is a signed
number in multiple of 16 bytes and configured to the
corresponding reserved space in packet meta area itself.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_inl.c | 27 ++++++++++++++++++++++++---
drivers/common/cnxk/roc_nix_inl_dev.c | 19 +++++++++++++++----
2 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 6afdfb6b85..7e47151eee 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -399,6 +399,7 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
struct nix_inl_dev *inl_dev = NULL;
uint64_t max_sa, i, sa_pow2_sz;
uint64_t sa_idx_w, lenm1_max;
+ uint64_t res_addr_offset;
uint8_t profile_id = 0;
struct mbox *mbox;
size_t inb_sa_sz;
@@ -497,11 +498,16 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
def_cptq = inl_dev->nix_inb_qids[0];
}
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id; /* IPsec profile is 0th one */
lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base[profile_id];
- lf_cfg->rx_inline_cfg0 = ((def_cptq << 57) | ((uint64_t)SSO_TT_ORDERED << 44) |
- (sa_pow2_sz << 16) | lenm1_max);
+ lf_cfg->rx_inline_cfg0 =
+ ((def_cptq << 57) | res_addr_offset | ((uint64_t)SSO_TT_ORDERED << 44) |
+ (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_idx_w << 32);
}
@@ -570,9 +576,13 @@ static int
nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
{
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ struct idev_cfg *idev = idev_get_cfg();
struct nix_rx_inl_lf_cfg_req *lf_cfg;
+ struct nix_inl_dev *inl_dev = NULL;
uint64_t max_sa = 1, sa_pow2_sz;
uint64_t sa_idx_w, lenm1_max;
+ uint64_t res_addr_offset;
+ uint64_t def_cptq = 0;
size_t inb_sa_sz = 1;
uint8_t profile_id;
struct mbox *mbox;
@@ -612,11 +622,22 @@ nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
sa_idx_w = plt_log2_u32(max_sa);
lenm1_max = roc_nix_max_pkt_len(roc_nix) - 1;
+ if (idev && idev->nix_inl_dev) {
+ inl_dev = idev->nix_inl_dev;
+ if (inl_dev->nb_inb_cptlfs)
+ def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
+ }
+
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base[profile_id];
lf_cfg->rx_inline_cfg0 =
- (((uint64_t)SSO_TT_ORDERED << 44) | (sa_pow2_sz << 16) | lenm1_max);
+ ((def_cptq << 57) | res_addr_offset | ((uint64_t)SSO_TT_ORDERED << 44) |
+ (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_idx_w << 32);
rc = mbox_process(mbox);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1db05741ad..1f071df8ea 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -376,6 +376,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
}
} else {
struct nix_rx_inl_lf_cfg_req *lf_cfg;
+ uint64_t res_addr_offset;
uint64_t def_cptq;
lf_cfg = mbox_alloc_msg_nix_rx_inl_lf_cfg(mbox);
@@ -390,13 +391,17 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
else
def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->profile_id = inl_dev->ipsec_prof_id;
if (ena) {
lf_cfg->enable = 1;
lf_cfg->rx_inline_sa_base = (uintptr_t)inl_dev->inb_sa_base[profile_id];
lf_cfg->rx_inline_cfg0 =
- ((def_cptq << 57) | ((uint64_t)SSO_TT_ORDERED << 44) |
- (sa_pow2_sz << 16) | lenm1_max);
+ ((def_cptq << 57) | res_addr_offset |
+ ((uint64_t)SSO_TT_ORDERED << 44) | (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_w << 32);
} else {
lf_cfg->enable = 0;
@@ -611,6 +616,7 @@ nix_inl_nix_profile_config(struct nix_inl_dev *inl_dev, uint8_t profile_id)
struct mbox *mbox = mbox_get((&inl_dev->dev)->mbox);
uint64_t max_sa, sa_w, sa_pow2_sz, lenm1_max;
struct nix_rx_inl_lf_cfg_req *lf_cfg;
+ uint64_t res_addr_offset;
uint64_t def_cptq;
size_t inb_sa_sz;
void *sa;
@@ -646,11 +652,16 @@ nix_inl_nix_profile_config(struct nix_inl_dev *inl_dev, uint8_t profile_id)
else
def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id + 1];
+ res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
+ if (res_addr_offset)
+ res_addr_offset |= (1UL << 56);
+
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)inl_dev->inb_sa_base[profile_id];
- lf_cfg->rx_inline_cfg0 = ((def_cptq << 57) | ((uint64_t)SSO_TT_ORDERED << 44) |
- (sa_pow2_sz << 16) | lenm1_max);
+ lf_cfg->rx_inline_cfg0 =
+ ((def_cptq << 57) | res_addr_offset | ((uint64_t)SSO_TT_ORDERED << 44) |
+ (sa_pow2_sz << 16) | lenm1_max);
lf_cfg->rx_inline_cfg1 = (max_sa - 1) | (sa_w << 32);
rc = mbox_process(mbox);
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 3/6] common/cnxk: update CPT parse header for O20
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
2025-05-19 12:54 ` [PATCH 2/6] common/cnxk: config CPT result address for cn20k Rahul Bhansali
@ 2025-05-19 12:54 ` Rahul Bhansali
2025-05-19 12:54 ` [PATCH 4/6] common/cnxk: update inbound CPT LF ID Rahul Bhansali
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Rahul Bhansali @ 2025-05-19 12:54 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Updates CPT parse header HW structure for O20.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/hw/cpt.h | 12 +++++++-----
drivers/common/cnxk/roc_cpt_debug.c | 8 ++++----
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 40987abbb9..e542f3a3d4 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -358,11 +358,11 @@ union cpt_parse_hdr_u {
struct {
uint64_t rsvd_134_128 : 7;
uint64_t pkt_inline : 1;
- uint64_t new_pkt_aura : 20;
+ uint64_t rsvd_155_136 : 20;
uint64_t orig_pkt_aura : 20;
uint64_t il3_off : 8;
- uint64_t ptr_pad : 3;
- uint64_t ptr_offset : 5;
+ uint64_t ptr_pad : 5;
+ uint64_t ptr_offset : 3;
};
} w2;
@@ -383,10 +383,12 @@ union cpt_parse_hdr_u {
uint64_t u64;
struct {
uint32_t l4_chksum;
- uint32_t l4_chksum_type : 1;
- uint32_t rsvd_298_289 : 10;
+ uint32_t l4_chksum_type : 2;
+ uint32_t rsvd_292_290 : 3;
uint32_t channel : 12;
+ uint32_t rsvd_308_305 : 4;
uint32_t sctr_size : 4;
+ uint32_t rsvd_314_313 : 2;
uint32_t gthr_size : 5;
};
} w4;
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 35a2cf6b3a..28aedf088e 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -36,8 +36,8 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t", cpth->wqe_ptr);
/* W2 */
- cpt_dump(file, "W2: pkt_inline \t0x%x\t\tnew_pkt_aura \t0x%x\t\torig_pkt_aura \t0x%x",
- cpth->w2.pkt_inline, cpth->w2.new_pkt_aura, cpth->w2.orig_pkt_aura);
+ cpt_dump(file, "W2: pkt_inline \t0x%x\t\torig_pkt_aura \t0x%x", cpth->w2.pkt_inline,
+ cpth->w2.orig_pkt_aura);
cpt_dump(file, "W2: il3_off \t0x%x\t\tptr_pad \t0x%x \t", cpth->w2.il3_off,
cpth->w2.ptr_pad);
cpt_dump(file, "W2: ptr_offset \t0x%x \t", cpth->w2.ptr_offset);
@@ -53,9 +53,9 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
cpt_dump(file, "W4: channel \t0x%x\t\tsctr_size \t0x%08x\t\tgthr_size \t0x%08x",
cpth->w4.channel, cpth->w4.sctr_size, cpth->w4.gthr_size);
- /* offset of 0 implies 256B, otherwise it implies offset*8B */
+ /* offset of 0 implies 256B, otherwise it implies offset*32B */
offset = cpth->w2.ptr_offset;
- offset = (((offset - 1) & 0x1f) + 1) * 8;
+ offset = (((offset - 1) & 0x7) + 1) * 32;
frag_info = PLT_PTR_ADD(cpth, offset);
if (cpth->w0.num_frags > 0) {
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 4/6] common/cnxk: update inbound CPT LF ID
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
2025-05-19 12:54 ` [PATCH 2/6] common/cnxk: config CPT result address for cn20k Rahul Bhansali
2025-05-19 12:54 ` [PATCH 3/6] common/cnxk: update CPT parse header for O20 Rahul Bhansali
@ 2025-05-19 12:54 ` Rahul Bhansali
2025-05-19 12:54 ` [PATCH 5/6] net/cnxk: update frag offset calculation Rahul Bhansali
2025-05-19 12:54 ` [PATCH 6/6] net/cnxk: update bufsize in lookup memory Rahul Bhansali
4 siblings, 0 replies; 6+ messages in thread
From: Rahul Bhansali @ 2025-05-19 12:54 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Inbound CPT LF ID update for Rx inline config.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_inl.c | 10 +++++++++-
drivers/common/cnxk/roc_nix_inl_dev.c | 4 +---
drivers/common/cnxk/roc_nix_inl_priv.h | 2 +-
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 7e47151eee..bee8e25c7c 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -495,7 +495,7 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
if (!inl_dev->nb_inb_cptlfs)
def_cptq = 0;
else
- def_cptq = inl_dev->nix_inb_qids[0];
+ def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
}
res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
@@ -1997,6 +1997,14 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable)
inl_dev = idev->nix_inl_dev;
+ if (!roc_model_is_cn10k()) {
+ if (inl_rq->spb_ena) {
+ rc = -EINVAL;
+ plt_err("inline RQ enable is not supported rc=%d", rc);
+ return rc;
+ }
+ }
+
rc = nix_rq_ena_dis(&inl_dev->dev, inl_rq, enable);
if (rc)
return rc;
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1f071df8ea..75d03c1077 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -385,7 +385,6 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
goto exit;
}
- /*TODO default cptq */
if (!inl_dev->nb_inb_cptlfs)
def_cptq = 0;
else
@@ -646,11 +645,10 @@ nix_inl_nix_profile_config(struct nix_inl_dev *inl_dev, uint8_t profile_id)
sa_w = plt_log2_u32(max_sa);
sa_pow2_sz = plt_log2_u32(inb_sa_sz);
- /*TODO default cptq, Assuming Reassembly cpt lf ID at inl_dev->inb_cpt_lf_id + 1 */
if (!inl_dev->nb_inb_cptlfs)
def_cptq = 0;
else
- def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id + 1];
+ def_cptq = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
if (res_addr_offset)
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 33073b2f34..5c12fb1160 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -134,7 +134,7 @@ struct nix_inl_dev {
#define NIX_INL_REASS_GEN_CFG \
(BIT_ULL(51) | (ROC_CPT_DFLT_ENG_GRP_SE << 48) | \
- (ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_REASS << 32))
+ (ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_REASS << 32 | ROC_IE_OW_INPLACE_BIT << 32))
int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);
void nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev);
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 5/6] net/cnxk: update frag offset calculation
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
` (2 preceding siblings ...)
2025-05-19 12:54 ` [PATCH 4/6] common/cnxk: update inbound CPT LF ID Rahul Bhansali
@ 2025-05-19 12:54 ` Rahul Bhansali
2025-05-19 12:54 ` [PATCH 6/6] net/cnxk: update bufsize in lookup memory Rahul Bhansali
4 siblings, 0 replies; 6+ messages in thread
From: Rahul Bhansali @ 2025-05-19 12:54 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Update frag offset calculation based on CSR change.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/net/cnxk/cn20k_rx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index 09042e384d..5682631815 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -337,7 +337,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
cq_w5 = *((const uint64_t *)rx + 4);
len = rlen + ((cq_w5 >> 16) & 0xFF) - (cq_w5 & 0xFF);
num_frags = hdr->w0.num_frags;
- sg_base = cpth + (offset ? (offset << 3) : 256);
+ sg_base = cpth + (offset ? (offset << 5) : 256);
finfo = (const struct cpt_frag_info_s *)sg_base;
sg_base += num_frags ? (num_frags > 4 ? 32 : 16) : 0;
sg = *(uint64_t *)sg_base;
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 6/6] net/cnxk: update bufsize in lookup memory
2025-05-19 12:54 [PATCH 1/6] common/cnxk: config of CPT result address offset Rahul Bhansali
` (3 preceding siblings ...)
2025-05-19 12:54 ` [PATCH 5/6] net/cnxk: update frag offset calculation Rahul Bhansali
@ 2025-05-19 12:54 ` Rahul Bhansali
4 siblings, 0 replies; 6+ messages in thread
From: Rahul Bhansali @ 2025-05-19 12:54 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Update bufsize in lookup-mem by default to maintain
data order.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/net/cnxk/cn20k_ethdev.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index 740fdb7f76..159ce39e97 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -604,8 +604,7 @@ cn20k_nix_dev_start(struct rte_eth_dev *eth_dev)
if (roc_idev_nix_rx_inject_get(nix->port_id))
dev->rx_offload_flags |= NIX_RX_SEC_REASSEMBLY_F;
- if (dev->rx_offload_flags & NIX_RX_REAS_F)
- cn20k_nix_rx_queue_bufsize_update(eth_dev);
+ cn20k_nix_rx_queue_bufsize_update(eth_dev);
cn20k_eth_set_tx_function(eth_dev);
cn20k_eth_set_rx_function(eth_dev);
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread