From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Vidya Sagar Velumuri <vvelumuri@marvell.com>,
Anoob Joseph <anoobj@marvell.com>, <dev@dpdk.org>
Subject: [PATCH 24/25] crypto/cnxk: add model check for cn20k
Date: Tue, 27 May 2025 16:32:04 +0530 [thread overview]
Message-ID: <20250527110205.2300800-25-ktejasree@marvell.com> (raw)
In-Reply-To: <20250527110205.2300800-1-ktejasree@marvell.com>
From: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Add model checks for cn20k.
Enable crypto and security capabilities for cn20k
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
drivers/crypto/cnxk/cnxk_cryptodev.c | 14 ++++++++------
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 10 +++++-----
drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 16 ++++++++++++----
3 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.c b/drivers/crypto/cnxk/cnxk_cryptodev.c
index 1eede2e59c..96b5121097 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.c
@@ -21,10 +21,10 @@ cnxk_cpt_default_ff_get(void)
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | RTE_CRYPTODEV_FF_SYM_SESSIONLESS |
RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED | RTE_CRYPTODEV_FF_SECURITY;
- if (roc_model_is_cn10k())
+ if (roc_model_is_cn10k() || roc_model_is_cn20k())
ff |= RTE_CRYPTODEV_FF_SECURITY_INNER_CSUM | RTE_CRYPTODEV_FF_SYM_RAW_DP;
- if (roc_model_is_cn10ka_b0() || roc_model_is_cn10kb())
+ if (roc_model_is_cn10ka_b0() || roc_model_is_cn10kb() || roc_model_is_cn20k())
ff |= RTE_CRYPTODEV_FF_SECURITY_RX_INJECT;
return ff;
@@ -41,10 +41,12 @@ cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt)
return -ENOTSUP;
}
- ret = roc_cpt_eng_grp_add(roc_cpt, CPT_ENG_TYPE_IE);
- if (ret < 0) {
- plt_err("Could not add CPT IE engines");
- return -ENOTSUP;
+ if (!roc_model_is_cn20k()) {
+ ret = roc_cpt_eng_grp_add(roc_cpt, CPT_ENG_TYPE_IE);
+ if (ret < 0) {
+ plt_err("Could not add CPT IE engines");
+ return -ENOTSUP;
+ }
}
ret = roc_cpt_eng_grp_add(roc_cpt, CPT_ENG_TYPE_AE);
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
index 63d2eef349..d2747878d3 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
@@ -1976,16 +1976,16 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, kasumi);
CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, des);
- if (!roc_model_is_cn10k())
+ if (roc_model_is_cn9k())
cn9k_crypto_caps_add(cnxk_caps, &cur_pos);
- if (roc_model_is_cn10k())
+ if (roc_model_is_cn10k() || roc_model_is_cn20k())
cn10k_crypto_caps_add(cnxk_caps, hw_caps, &cur_pos);
cpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null));
cpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end));
- if (roc_model_is_cn10k())
+ if (roc_model_is_cn10k() || roc_model_is_cn20k())
cn10k_crypto_caps_update(cnxk_caps);
}
@@ -2060,7 +2060,7 @@ sec_ipsec_crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
SEC_IPSEC_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, des);
SEC_IPSEC_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, sha1_sha2);
- if (roc_model_is_cn10k())
+ if (roc_model_is_cn10k() || roc_model_is_cn20k())
cn10k_sec_ipsec_crypto_caps_update(cnxk_caps, &cur_pos);
else
cn9k_sec_ipsec_crypto_caps_update(cnxk_caps);
@@ -2189,7 +2189,7 @@ cnxk_cpt_caps_populate(struct cnxk_cpt_vf *vf)
cnxk_sec_ipsec_caps_update(&vf->sec_caps[i]);
- if (roc_model_is_cn10k())
+ if (roc_model_is_cn10k() || roc_model_is_cn20k())
cn10k_sec_ipsec_caps_update(&vf->sec_caps[i]);
if (roc_model_is_cn9k())
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 982fbe991f..e5ca082e10 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -741,8 +741,10 @@ cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt)
inst_w7.s.cptr += 8;
/* Set the engine group */
- if (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3 || sess->is_sm3 ||
- sess->passthrough || sess->is_sm4)
+ if (roc_model_is_cn20k())
+ inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_SE];
+ else if (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3 || sess->is_sm3 ||
+ sess->passthrough || sess->is_sm4)
inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_SE];
else
inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];
@@ -1043,7 +1045,7 @@ RTE_EXPORT_EXPERIMENTAL_SYMBOL(rte_pmd_cnxk_crypto_submit, 24.03)
void
rte_pmd_cnxk_crypto_submit(struct rte_pmd_cnxk_crypto_qptr *qptr, void *inst, uint16_t nb_inst)
{
- if (roc_model_is_cn10k())
+ if (roc_model_is_cn10k() || roc_model_is_cn20k())
return cnxk_crypto_cn10k_submit(qptr, inst, nb_inst);
else if (roc_model_is_cn9k())
return cnxk_crypto_cn9k_submit(qptr, inst, nb_inst);
@@ -1068,7 +1070,7 @@ rte_pmd_cnxk_crypto_cptr_flush(struct rte_pmd_cnxk_crypto_qptr *qptr,
return -EINVAL;
}
- if (unlikely(!roc_model_is_cn10k())) {
+ if (unlikely(roc_model_is_cn9k())) {
plt_err("Invalid cnxk model");
return -EINVAL;
}
@@ -1106,6 +1108,12 @@ rte_pmd_cnxk_crypto_cptr_get(struct rte_pmd_cnxk_crypto_sess *rte_sess)
}
if (rte_sess->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
+ if (roc_model_is_cn20k()) {
+ struct cn20k_sec_session *sec_sess = PLT_PTR_CAST(rte_sess->sec_sess);
+
+ return PLT_PTR_CAST(&sec_sess->sa);
+ }
+
if (roc_model_is_cn10k()) {
struct cn10k_sec_session *sec_sess = PLT_PTR_CAST(rte_sess->sec_sess);
return PLT_PTR_CAST(&sec_sess->sa);
--
2.25.1
next prev parent reply other threads:[~2025-05-27 11:05 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-27 11:01 [PATCH 00/25] add CN20K support to cnxk crypto PMD Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 01/25] crypto/cnxk: add probe for cn20k crypto device Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 02/25] crypto/cnxk: add ops skeleton for cn20k Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 03/25] crypto/cnxk: add dev info get Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 04/25] crypto/cnxk: add skeletion for enq deq functions Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 05/25] crypto/cnxk: add lmtst routines for cn20k Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 06/25] crypto/cnxk: add enqueue function support Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 07/25] crypto/cnxk: add cryptodev dequeue support for cn20k Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 08/25] crypto/cnxk: move debug dumps to common Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 09/25] crypto/cnxk: add rte security skeletion for cn20k Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 10/25] crypto/cnxk: add security session creation Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 11/25] crypto/cnxk: add security session destroy Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 12/25] crypto/cnxk: move code to common Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 13/25] crypto/cnxk: add rte sec session update Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 14/25] crypto/cnxk: add rte security datapath handling Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 15/25] crypto/cnxk: add Rx inject in security lookaside Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 16/25] crypto/cnxk: add skeleton for tls Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 17/25] crypto/cnxk: add tls write session creation Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 18/25] crypto/cnxk: add tls read " Tejasree Kondoj
2025-05-27 11:01 ` [PATCH 19/25] crypto/cnxk: add tls session destroy Tejasree Kondoj
2025-05-27 11:02 ` [PATCH 20/25] crypto/cnxk: add enq and dequeue support for TLS Tejasree Kondoj
2025-05-27 11:02 ` [PATCH 21/25] crypto/cnxk: tls post process Tejasree Kondoj
2025-05-27 11:02 ` [PATCH 22/25] crypto/cnxk: add tls session update Tejasree Kondoj
2025-05-27 11:02 ` [PATCH 23/25] crypto/cnxk: support raw API for cn20k Tejasree Kondoj
2025-05-27 11:02 ` Tejasree Kondoj [this message]
2025-05-27 11:02 ` [PATCH 25/25] doc: update CN20K CPT documentation Tejasree Kondoj
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