From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Rupesh Chiluka <rchiluka@marvell.com>,
Anoob Joseph <anoobj@marvell.com>,
Nithinsen Kaithakadan <nkaithakadan@marvell.com>,
Vidya Sagar Velumuri <vvelumuri@marvell.com>, <dev@dpdk.org>
Subject: [PATCH 6/9] crypto/cnxk: add asym sessionless handling
Date: Tue, 27 May 2025 18:31:32 +0530 [thread overview]
Message-ID: <20250527130135.2301726-7-ktejasree@marvell.com> (raw)
In-Reply-To: <20250527130135.2301726-1-ktejasree@marvell.com>
From: Rupesh Chiluka <rchiluka@marvell.com>
Add asymmetric sessionless handling for cnxk
Signed-off-by: Rupesh Chiluka <rchiluka@marvell.com>
---
drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 19 +++++++++++++++++--
drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 20 ++++++++++++++++++--
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
index 9ad0629519..813a2deb66 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
@@ -417,8 +417,23 @@ cn10k_ca_meta_info_extract(struct rte_crypto_op *op, struct cnxk_cpt_qp **qp, ui
priv = (struct cnxk_ae_sess *)op->asym->session;
*qp = priv->qp;
*w2 = priv->cpt_inst_w2;
- } else
- return -EINVAL;
+ } else {
+ union rte_event_crypto_metadata *ec_mdata;
+ struct rte_event *rsp_info;
+ uint8_t cdev_id;
+ uint16_t qp_id;
+
+ if (unlikely(op->private_data_offset == 0))
+ return -EINVAL;
+ ec_mdata = (union rte_event_crypto_metadata *)((uint8_t *)op +
+ op->private_data_offset);
+ rsp_info = &ec_mdata->response_info;
+ cdev_id = ec_mdata->request_info.cdev_id;
+ qp_id = ec_mdata->request_info.queue_pair_id;
+ *qp = rte_cryptodevs[cdev_id].data->queue_pairs[qp_id];
+ *w2 = CNXK_CPT_INST_W2((RTE_EVENT_TYPE_CRYPTODEV << 28) | rsp_info->flow_id,
+ rsp_info->sched_type, rsp_info->queue_id, 0);
+ }
} else
return -EINVAL;
diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
index ee35ed1eba..fa22b5ce44 100644
--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
@@ -333,8 +333,24 @@ cn9k_ca_meta_info_extract(struct rte_crypto_op *op,
priv = (struct cnxk_ae_sess *)op->asym->session;
*qp = priv->qp;
inst->w2.u64 = priv->cpt_inst_w2;
- } else
- return -EINVAL;
+ } else {
+ union rte_event_crypto_metadata *ec_mdata;
+ struct rte_event *rsp_info;
+ uint8_t cdev_id;
+ uint16_t qp_id;
+
+ if (unlikely(op->private_data_offset == 0))
+ return -EINVAL;
+ ec_mdata = (union rte_event_crypto_metadata *)((uint8_t *)op +
+ op->private_data_offset);
+ rsp_info = &ec_mdata->response_info;
+ cdev_id = ec_mdata->request_info.cdev_id;
+ qp_id = ec_mdata->request_info.queue_pair_id;
+ *qp = rte_cryptodevs[cdev_id].data->queue_pairs[qp_id];
+ inst->w2.u64 = CNXK_CPT_INST_W2(
+ (RTE_EVENT_TYPE_CRYPTODEV << 28) | rsp_info->flow_id,
+ rsp_info->sched_type, rsp_info->queue_id, 0);
+ }
} else
return -EINVAL;
--
2.25.1
next prev parent reply other threads:[~2025-05-27 13:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-27 13:01 [PATCH 0/9] fixes and new features to cnxk crypto PMD Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 1/9] crypto/cnxk: include required headers Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 2/9] common/cnxk: fix salt handling with aes-ctr Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 3/9] common/cnxk: set correct salt value for ctr algos Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 4/9] crypto/cnxk: extend check for max supported gather entries Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 5/9] crypto/cnxk: add struct variable for custom metadata Tejasree Kondoj
2025-05-27 13:01 ` Tejasree Kondoj [this message]
2025-05-27 13:01 ` [PATCH 7/9] crypto/cnxk: add support for sessionless asym Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 8/9] common/cnxk: update qsize in CPT iq enable Tejasree Kondoj
2025-05-27 13:01 ` [PATCH 9/9] crypto/cnxk: copy 8B iv into sess in aes ctr Tejasree Kondoj
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