From: <skori@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH 4/7] net/cnxk: get speed capability from firmware
Date: Thu, 5 Jun 2025 14:36:39 +0530 [thread overview]
Message-ID: <20250605090657.3032918-4-skori@marvell.com> (raw)
In-Reply-To: <20250605090657.3032918-1-skori@marvell.com>
From: Sunil Kumar Kori <skori@marvell.com>
Currently speed capability is hardcoded to support defined
modes and speeds but MAC can support others modes and speed
too. This information is populated by firmware.
Hence fetching firmware data to provide actual supported
modes and speeds by the port.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
drivers/net/cnxk/cnxk_ethdev.c | 75 ++++++++++++++++++++++++++++++++--
1 file changed, 72 insertions(+), 3 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index fc17841bca..89d304be7e 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -7,6 +7,60 @@
#include <rte_eventdev.h>
#include <rte_pmd_cnxk.h>
+static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = {
+ [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G,
+ [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G,
+ [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G,
+ [CGX_MODE_10G_C2C] = RTE_ETH_LINK_SPEED_10G,
+ [CGX_MODE_10G_C2M] = RTE_ETH_LINK_SPEED_10G,
+ [CGX_MODE_10G_KR] = RTE_ETH_LINK_SPEED_10G,
+ [CGX_MODE_20G_C2C] = RTE_ETH_LINK_SPEED_20G,
+ [CGX_MODE_25G_C2C] = RTE_ETH_LINK_SPEED_25G,
+ [CGX_MODE_25G_C2M] = RTE_ETH_LINK_SPEED_25G,
+ [CGX_MODE_25G_2_C2C] = RTE_ETH_LINK_SPEED_25G,
+ [CGX_MODE_25G_CR] = RTE_ETH_LINK_SPEED_25G,
+ [CGX_MODE_25G_KR] = RTE_ETH_LINK_SPEED_25G,
+ [CGX_MODE_40G_C2C] = RTE_ETH_LINK_SPEED_40G,
+ [CGX_MODE_40G_C2M] = RTE_ETH_LINK_SPEED_40G,
+ [CGX_MODE_40G_CR4] = RTE_ETH_LINK_SPEED_40G,
+ [CGX_MODE_40G_KR4] = RTE_ETH_LINK_SPEED_40G,
+ [CGX_MODE_40GAUI_C2C] = RTE_ETH_LINK_SPEED_40G,
+ [CGX_MODE_50G_C2C] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_50G_C2M] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_50G_4_C2C] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_50G_CR] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_50G_KR] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_80GAUI_C2C] = 0, /* No define for 80G */
+ [CGX_MODE_100G_C2C] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_100G_C2M] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_100G_CR4] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_100G_KR4] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_LAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_LAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_50GBASE_CR2_C_BIT] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_50GBASE_KR2_C_BIT] = RTE_ETH_LINK_SPEED_50G,
+ [CGX_MODE_100GAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_100GAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_100GBASE_CR2_BIT] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_100GBASE_KR2_BIT] = RTE_ETH_LINK_SPEED_100G,
+ [CGX_MODE_SFI_1G_BIT] = RTE_ETH_LINK_SPEED_1G,
+ [CGX_MODE_25GBASE_CR_C_BIT] = RTE_ETH_LINK_SPEED_25G,
+ [CGX_MODE_25GBASE_KR_C_BIT] = RTE_ETH_LINK_SPEED_25G,
+ [ETH_MODE_SGMII_10M_BIT] = RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_10M_HD,
+ [ETH_MODE_SGMII_100M_BIT] = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD,
+ [40] = 0,
+ [41] = 0,
+ [ETH_MODE_2500_BASEX_BIT] = RTE_ETH_LINK_SPEED_2_5G,
+ [ETH_MODE_5000_BASEX_BIT] = RTE_ETH_LINK_SPEED_5G,
+ [ETH_MODE_O_USGMII_BIT] = RTE_ETH_LINK_SPEED_100M,
+ [ETH_MODE_Q_USGMII_BIT] = RTE_ETH_LINK_SPEED_1G,
+ [ETH_MODE_2_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_2_5G,
+ [ETH_MODE_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_5G,
+ [ETH_MODE_10G_SXGMII_BIT] = RTE_ETH_LINK_SPEED_10G,
+ [ETH_MODE_10G_DXGMII_BIT] = RTE_ETH_LINK_SPEED_10G,
+ [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G,
+};
+
cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb;
#define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL)
@@ -42,14 +96,29 @@ nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
static inline uint32_t
nix_get_speed_capa(struct cnxk_eth_dev *dev)
{
+ struct roc_nix_mac_fwdata fwdata;
uint32_t speed_capa;
+ uint8_t mode;
+ int rc;
/* Auto negotiation disabled */
speed_capa = RTE_ETH_LINK_SPEED_FIXED;
if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
- speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
- RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
- RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
+ memset(&fwdata, 0, sizeof(fwdata));
+ rc = roc_nix_mac_fwdata_get(&dev->nix, &fwdata);
+ if (rc) {
+ plt_err("Failed to get MAC firmware data");
+ return 0;
+ }
+
+ if (fwdata.supported_an)
+ speed_capa = 0;
+
+ /* Translate advertised modes to speed_capa */
+ for (mode = 0; mode < CGX_MODE_MAX; mode++) {
+ if (fwdata.supported_link_modes & BIT_ULL(mode))
+ speed_capa |= cnxk_mac_modes[mode];
+ }
}
return speed_capa;
--
2.43.0
next prev parent reply other threads:[~2025-06-05 9:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-05 9:06 [PATCH 1/7] ethdev: add support to provide link type skori
2025-06-05 9:06 ` [PATCH 2/7] common/cnxk: support link mode configuration skori
2025-06-05 9:06 ` [PATCH 3/7] common/cnxk: provide port type from fwdata skori
2025-06-05 9:06 ` skori [this message]
2025-06-05 9:06 ` [PATCH 5/7] net/cnxk: support link mode configuration skori
2025-06-05 9:06 ` [PATCH 6/7] net/cnxk: report link type and status skori
2025-06-05 9:06 ` [PATCH 7/7] net/cnxk: report link mode skori
2025-06-05 15:22 ` [PATCH 1/7] ethdev: add support to provide link type Stephen Hemminger
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