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([10.233.181.123]) by fmviesa006.fm.intel.com with ESMTP; 26 Aug 2025 12:43:15 -0700 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hemant.agrawal@nxp.com, hernan.vargas@intel.com, Nicolas Chautru Subject: [PATCH v1 1/2] doc: clarify CB vs TB level device support Date: Tue, 26 Aug 2025 12:43:23 -0700 Message-Id: <20250826194324.95284-2-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250826194324.95284-1-nicolas.chautru@intel.com> References: <20250826194324.95284-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Clarify the support for different bbdev devices with regards to code block vs transport block level processing which was not explicit enough. Signed-off-by: Nicolas Chautru --- doc/guides/bbdevs/acc100.rst | 1 + doc/guides/bbdevs/fpga_5gnr_fec.rst | 1 + doc/guides/bbdevs/fpga_lte_fec.rst | 1 + doc/guides/bbdevs/vrb1.rst | 1 + doc/guides/bbdevs/vrb2.rst | 2 ++ 5 files changed, 6 insertions(+) diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst index 6843e38c55..1621cc782f 100644 --- a/doc/guides/bbdevs/acc100.rst +++ b/doc/guides/bbdevs/acc100.rst @@ -17,6 +17,7 @@ ACC100 5G/4G FEC PMDs support the following features: - LDPC Decode in the UL (5GNR) - Turbo Encode in the DL (4G) - Turbo Decode in the UL (4G) +- Support for code block level processing - 16 VFs per PF (physical device) - Maximum of 128 queues per VF - PCIe Gen-3 x16 Interface diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst index 58d19ffbd2..b181527c45 100644 --- a/doc/guides/bbdevs/fpga_5gnr_fec.rst +++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst @@ -16,6 +16,7 @@ FPGA 5GNR FEC PMD supports the following BBDEV capabilities: - LDPC Encode in the DL - LDPC Decode in the UL +- Support for code block level processing - 8 VFs per PF (physical device) - Maximum of 32 UL queues per VF - Maximum of 32 DL queues per VF diff --git a/doc/guides/bbdevs/fpga_lte_fec.rst b/doc/guides/bbdevs/fpga_lte_fec.rst index 7e3748222c..990eeb087b 100644 --- a/doc/guides/bbdevs/fpga_lte_fec.rst +++ b/doc/guides/bbdevs/fpga_lte_fec.rst @@ -15,6 +15,7 @@ FPGA LTE FEC PMD supports the following features: - Turbo Encode in the DL with total throughput of 4.5 Gbits/s - Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations +- Support for code block level processing - 8 VFs per PF (physical device) - Maximum of 32 UL queues per VF - Maximum of 32 DL queues per VF diff --git a/doc/guides/bbdevs/vrb1.rst b/doc/guides/bbdevs/vrb1.rst index 255c4ea040..134dc246e7 100644 --- a/doc/guides/bbdevs/vrb1.rst +++ b/doc/guides/bbdevs/vrb1.rst @@ -30,6 +30,7 @@ These hardware blocks provide the following features exposed by the PMD: - LDPC Decode in the Uplink (5GNR) - Turbo Encode in the Downlink (4G) - Turbo Decode in the Uplink (4G) +- Support for code block level processing - FFT processing - Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF) - Maximum of 256 queues per VF diff --git a/doc/guides/bbdevs/vrb2.rst b/doc/guides/bbdevs/vrb2.rst index 45c83e875f..ad67cc36a4 100644 --- a/doc/guides/bbdevs/vrb2.rst +++ b/doc/guides/bbdevs/vrb2.rst @@ -29,6 +29,8 @@ These hardware blocks provide the following features exposed by the PMD: - LDPC Decode in the Uplink (5GNR) - Turbo Encode in the Downlink (4G) - Turbo Decode in the Uplink (4G) +- Support for code block level processing +- Support for TB level processing for the LDPC Encode processing including CB concatenation. - FFT processing - MLD-TS processing - Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF) -- 2.34.1