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Mon, 8 Sep 2025 23:29:04 -0700 From: Maayan Kashani To: CC: , , , Viacheslav Ovsiienko , , Matan Azrad , Bing Zhao , Ori Kam , Suanming Mou , Raja Zidane Subject: [PATCH v2 2/3] net/mlx5: fix ESP item validation to match on seqnum Date: Tue, 9 Sep 2025 09:28:52 +0300 Message-ID: <20250909062853.60592-2-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20250909062853.60592-1-mkashani@nvidia.com> References: <20250804050514.244896-1-viacheslavo@nvidia.com> <20250909062853.60592-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|IA1PR12MB6305:EE_ X-MS-Office365-Filtering-Correlation-Id: 54cbbc53-260d-45df-1319-08ddef6a3c68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VAOZLmu3hdyUmsz3XD6zbVAdiOu5id93J1NhDUDPdFJ2luoWVerIfWd6Paq4?= =?us-ascii?Q?h5EuLmYuL7amCjesVtEbqk0tIzdv/OHvzXSVgeGwzi+2YPkRIABaX3vuZjDs?= =?us-ascii?Q?7vR05Eb1N4XJ/bvmnWK0OsbiZR6MZDddufHaZNRKOa02d8tamkbvgr1zAM1c?= =?us-ascii?Q?Up7k7f7Gwt67yjk19j60nbD3Kh7u79hLeLBtRnWJKfMyVtLx5+Va97SBmYQ9?= =?us-ascii?Q?wGNjiocKXAlGf3bgp+VQYGpX3HmN2YAgpBT8O66BPD609toI+KIJXZCj9xnv?= =?us-ascii?Q?3QD4M+jK/9kmRP8O96dWqS4ryAwMkEsETJE4q7AbKDB72HCNhHCAIE2s4S2L?= =?us-ascii?Q?HLNZcrIxvBkA9cXRCy10/RUiowrwp0Nxi2xl35yAwcd56a8XSyjDslp65h4C?= =?us-ascii?Q?prwk7BeHyAr1nw3QzWBR1o8mjpNS1P2R+IfDEjh3x8IsWkc9bsSMmWE7btYb?= =?us-ascii?Q?Kwu4Q4lvpGzGnaJhBRbdeJ+//8QcWi18hFr0fy1cUD8QvHIuUolaaMrv/wMQ?= =?us-ascii?Q?RV9ajx+wg44ciOIURtSPdxHapCY0px8+nu7ifocFbe+1umoojUwRBkGG1xi8?= =?us-ascii?Q?8JeahkLL3yFxD1uaLEvNWfwxcFC8KHT7Wk0Wwpd/qwkDMTKWEoHDSuODfXR7?= =?us-ascii?Q?7CFGshrBCmb+ZuGlrfO/YvsCWbYMpZacLbq4btHBQzIkEjIte7MX3Bzljrzi?= =?us-ascii?Q?w0qIQa0uV84jS2iG3MBxi2mCqnPQ+W9prQjEl9weVftWnZt3KAEyw870wE2h?= =?us-ascii?Q?lJhcNbO31l0l08VaM4ZMV3APYYrGicKlCGVFOuMgNZI7FJgXz6M0gS80Tsn3?= =?us-ascii?Q?Gn0MaAez2RBMFN+ngPXIKTMY8wp9+taJ5UpblWLxnMqMIAiJGi1V3MpQeaAY?= =?us-ascii?Q?z6DFJGJ1Oj1+AJSRfWbgI7inqTybAW2Q79z84XadNDe+lBVlKEzX5PeFQZ8/?= =?us-ascii?Q?m9hAEyOG0PwAwhd57PWElZRBls3774a5/oHAg+fX5/5lBUPrVq2eBOAtSKea?= =?us-ascii?Q?idcEhviHZtQKc8cCKMC9Hf30Tt+GD00H+W4TqWFCfsiz2XgiuO9sKhj4zlC2?= =?us-ascii?Q?lPN8UgZ/Y3UdFOUOjjPXhQMzZixWPp4wmnB9VLPTGTaIM1NFyGq3mWGeBMoi?= =?us-ascii?Q?/+sTV6Rs0CFMkbL/UIs52nuM06Sfupx04++DCEBhOxswMaJ7LWVMfYe2pGP2?= =?us-ascii?Q?8QRl5f8S7e+NqnpTozS7tAvqE9vbwC/NhIT4oDiAmTw7dnLIjYFw+HMYIVIo?= =?us-ascii?Q?/F1UsmD7kVjWDDOv11a79aHUIbyLohyXQOAjqHrvDNMwSt6pekU57x6ljXul?= =?us-ascii?Q?r8zAOXZXZYVb65pXVG5Uqzf5XUP4r114pQxOukHmGnfOCfd54+KD236HRTJ9?= =?us-ascii?Q?Phr4vebp68StFnncsSg5CFVdm0K53LmiXSVhDXWEKUQlZAjF8XSmoFyb7HmJ?= =?us-ascii?Q?1ysu+42VbWHysx05yXr/ggecyVb0qDBgVRpmf0XfWwWnvuioUNYfC3oQP4DL?= =?us-ascii?Q?f7ZKmYUsOdF6ZPAr5vtgR06FsKygoDubM49a?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2025 06:29:31.4433 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54cbbc53-260d-45df-1319-08ddef6a3c68 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6305 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Viacheslav Ovsiienko The match on ESP sequence number is supported by hardware steering implementation but was rejected in validation routine shared by all steering engines. This patch allows validation to pass with requested match on ESP sequence number for hardware steering engine. Fixes: fb96caa56aab ("net/mlx5: support ESP item on Windows") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_flow_os.c | 10 +++++++++- drivers/net/mlx5/linux/mlx5_flow_os.h | 3 +++ drivers/net/mlx5/mlx5_flow_dv.c | 6 ++---- drivers/net/mlx5/mlx5_flow_hw.c | 5 ++--- drivers/net/mlx5/mlx5_flow_verbs.c | 6 ++---- drivers/net/mlx5/windows/mlx5_flow_os.c | 10 +++++++++- drivers/net/mlx5/windows/mlx5_flow_os.h | 3 +++ 7 files changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.c b/drivers/net/mlx5/linux/mlx5_flow_os.c index af8c02c38b8..777125e9a87 100644 --- a/drivers/net/mlx5/linux/mlx5_flow_os.c +++ b/drivers/net/mlx5/linux/mlx5_flow_os.c @@ -18,6 +18,7 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, + bool allow_seq, struct rte_flow_error *error) { const struct rte_flow_item_esp *mask = item->mask; @@ -26,6 +27,12 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, MLX5_FLOW_LAYER_OUTER_L3; const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : MLX5_FLOW_LAYER_OUTER_L4; + static const struct rte_flow_item_esp mlx5_flow_item_esp_mask = { + .hdr = { + .spi = RTE_BE32(0xffffffff), + .seq = RTE_BE32(0xffffffff), + }, + }; int ret; if (!mlx5_hws_active(dev)) { @@ -47,7 +54,8 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, mask = &rte_flow_item_esp_mask; ret = mlx5_flow_item_acceptable (dev, item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_esp_mask, + allow_seq ? (const uint8_t *)&mlx5_flow_item_esp_mask : + (const uint8_t *)&rte_flow_item_esp_mask, sizeof(struct rte_flow_item_esp), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); if (ret < 0) diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h index 35b5871ab91..21a2ed5bec0 100644 --- a/drivers/net/mlx5/linux/mlx5_flow_os.h +++ b/drivers/net/mlx5/linux/mlx5_flow_os.h @@ -514,6 +514,8 @@ mlx5_os_flow_dr_sync_domain(void *domain, uint32_t flags) * Bit-fields that holds the items detected until now. * @param[in] target_protocol * The next protocol in the previous item. + * @param[in] allow_seq + * The match on sequence number is supported. * @param[out] error * Pointer to error structure. * @@ -525,6 +527,7 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, + bool allow_seq, struct rte_flow_error *error); /** diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index abfd54da1a9..18d0d293770 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7859,10 +7859,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, case RTE_FLOW_ITEM_TYPE_VOID: break; case RTE_FLOW_ITEM_TYPE_ESP: - ret = mlx5_flow_os_validate_item_esp(dev, items, - item_flags, - next_protocol, - error); + ret = mlx5_flow_os_validate_item_esp(dev, items, item_flags, + next_protocol, false, error); if (ret < 0) return ret; last_item = MLX5_FLOW_ITEM_ESP; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index c84ae726a74..2ca40b41465 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8818,9 +8818,8 @@ __flow_hw_pattern_validate(struct rte_eth_dev *dev, last_item = MLX5_FLOW_ITEM_QUOTA; break; case RTE_FLOW_ITEM_TYPE_ESP: - ret = mlx5_flow_os_validate_item_esp(dev, item, - *item_flags, 0xff, - error); + ret = mlx5_flow_os_validate_item_esp(dev, item, *item_flags, + 0xff, true, error); if (ret < 0) return ret; last_item = MLX5_FLOW_ITEM_ESP; diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index 5b4a4eda3bb..67d199ce15e 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -1332,10 +1332,8 @@ flow_verbs_validate(struct rte_eth_dev *dev, switch (items->type) { #ifdef HAVE_IBV_FLOW_SPEC_ESP case RTE_FLOW_ITEM_TYPE_ESP: - ret = mlx5_flow_os_validate_item_esp(dev, items, - item_flags, - next_protocol, - error); + ret = mlx5_flow_os_validate_item_esp(dev, items, item_flags, + next_protocol, false, error); if (ret < 0) return ret; last_item = MLX5_FLOW_ITEM_ESP; diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c index bf93da9f1e1..7a625fb880a 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.c +++ b/drivers/net/mlx5/windows/mlx5_flow_os.c @@ -428,6 +428,7 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, + bool allow_seq, struct rte_flow_error *error) { const struct rte_flow_item_esp *mask = item->mask; @@ -437,6 +438,12 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, MLX5_FLOW_LAYER_OUTER_L3; const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : MLX5_FLOW_LAYER_OUTER_L4; + static const struct rte_flow_item_esp mlx5_flow_item_esp_mask = { + .hdr = { + .spi = RTE_BE32(0xffffffff), + .seq = RTE_BE32(0xffffffff), + }, + }; int ret; if (!(item_flags & l3m)) @@ -461,7 +468,8 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, " supported on Windows"); ret = mlx5_flow_item_acceptable (dev, item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_esp_mask, + allow_seq ? (const uint8_t *)&mlx5_flow_item_esp_mask : + (const uint8_t *)&rte_flow_item_esp_mask, sizeof(struct rte_flow_item_esp), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); if (ret < 0) diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.h b/drivers/net/mlx5/windows/mlx5_flow_os.h index 36edc3d5328..2cd4e953256 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.h +++ b/drivers/net/mlx5/windows/mlx5_flow_os.h @@ -461,6 +461,8 @@ int mlx5_flow_os_destroy_flow(void *drv_flow_ptr); * Bit-fields that holds the items detected until now. * @param[in] target_protocol * The next protocol in the previous item. + * @param[in] allow_seq + * The match on sequence number is supported. * @param[out] error * Pointer to error structure. * @@ -472,6 +474,7 @@ mlx5_flow_os_validate_item_esp(const struct rte_eth_dev *dev, const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, + bool allow_seq, struct rte_flow_error *error); /** -- 2.21.0