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Wed, 17 Sep 2025 23:48:01 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14 via Frontend Transport; Wed, 17 Sep 2025 23:47:59 -0700 From: Shani Peretz To: CC: , Shani Peretz , , Bruce Richardson , "Dmitry Kozlyuk" , Tyler Retzlaff , Alejandro Lucero Subject: [PATCH v2] eal: fix DMA mask validation inconsistency in IOVA VA Date: Thu, 18 Sep 2025 09:47:54 +0300 Message-ID: <20250918064754.6116-1-shperetz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908163456.420268-1-shperetz@nvidia.com> References: <20250908163456.420268-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|SA1PR12MB8699:EE_ X-MS-Office365-Filtering-Correlation-Id: 61bcf294-c658-4f66-0831-08ddf67f56e0 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2025 06:48:13.3970 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61bcf294-c658-4f66-0831-08ddf67f56e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8699 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When --iova-mode is explicitly specified in command line, DMA mask constraints were not being validated, leading to potential runtime failures when device DMA capabilities are exceeded. The issue occurred because rte_bus_get_iommu_class() was only called during IOVA mode auto-detection, but this function has the important side effect of triggering DMA mask detection (e.g., Intel IOMMU address width checking via pci_device_iommu_support_va()). This created an inconsistency, when choosing explicit mode, the DMA checks are bypassed, but when choosing auto-detection mode, the constraints are checked and enforced. The fix moves rte_bus_get_iommu_class() outside the conditional logic to ensure it's always called during EAL initialization. Fixes: 4374ebc24bc1 ("malloc: modify error message for DMA mask check") Cc: stable@dpdk.org Signed-off-by: Shani Peretz --- lib/eal/freebsd/eal.c | 6 +++++- lib/eal/linux/eal.c | 5 ++++- lib/eal/windows/eal.c | 5 ++++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/lib/eal/freebsd/eal.c b/lib/eal/freebsd/eal.c index c1ab8d86d2..0f957919d3 100644 --- a/lib/eal/freebsd/eal.c +++ b/lib/eal/freebsd/eal.c @@ -670,12 +670,16 @@ rte_eal_init(int argc, char **argv) * with a message describing the cause. */ has_phys_addr = internal_conf->no_hugetlbfs == 0; + + /* Always call rte_bus_get_iommu_class() to trigger DMA mask detection and validation */ + enum rte_iova_mode bus_iova_mode = rte_bus_get_iommu_class(); + iova_mode = internal_conf->iova_mode; if (iova_mode == RTE_IOVA_DC) { EAL_LOG(DEBUG, "Specific IOVA mode is not requested, autodetecting"); if (has_phys_addr) { EAL_LOG(DEBUG, "Selecting IOVA mode according to bus requests"); - iova_mode = rte_bus_get_iommu_class(); + iova_mode = bus_iova_mode; if (iova_mode == RTE_IOVA_DC) { if (!RTE_IOVA_IN_MBUF) { iova_mode = RTE_IOVA_VA; diff --git a/lib/eal/linux/eal.c b/lib/eal/linux/eal.c index 52efb8626b..3a0c9c9db6 100644 --- a/lib/eal/linux/eal.c +++ b/lib/eal/linux/eal.c @@ -1042,10 +1042,13 @@ rte_eal_init(int argc, char **argv) phys_addrs = rte_eal_using_phys_addrs() != 0; + /* Always call rte_bus_get_iommu_class() to trigger DMA mask detection and validation */ + enum rte_iova_mode bus_iova_mode = rte_bus_get_iommu_class(); + /* if no EAL option "--iova-mode=", use bus IOVA scheme */ if (internal_conf->iova_mode == RTE_IOVA_DC) { /* autodetect the IOVA mapping mode */ - enum rte_iova_mode iova_mode = rte_bus_get_iommu_class(); + enum rte_iova_mode iova_mode = bus_iova_mode; if (iova_mode == RTE_IOVA_DC) { EAL_LOG(DEBUG, "Buses did not request a specific IOVA mode."); diff --git a/lib/eal/windows/eal.c b/lib/eal/windows/eal.c index 4f0a164d9b..2502ec3c3d 100644 --- a/lib/eal/windows/eal.c +++ b/lib/eal/windows/eal.c @@ -348,12 +348,15 @@ rte_eal_init(int argc, char **argv) has_phys_addr = false; } + /* Always call rte_bus_get_iommu_class() to trigger DMA mask detection and validation */ + enum rte_iova_mode bus_iova_mode = rte_bus_get_iommu_class(); + iova_mode = internal_conf->iova_mode; if (iova_mode == RTE_IOVA_DC) { EAL_LOG(DEBUG, "Specific IOVA mode is not requested, autodetecting"); if (has_phys_addr) { EAL_LOG(DEBUG, "Selecting IOVA mode according to bus requests"); - iova_mode = rte_bus_get_iommu_class(); + iova_mode = bus_iova_mode; if (iova_mode == RTE_IOVA_DC) { if (!RTE_IOVA_IN_MBUF) { iova_mode = RTE_IOVA_VA; -- 2.34.1