From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Anoob Joseph <anoobj@marvell.com>,
Aakash Sasidharan <asasidharan@marvell.com>,
Nithinsen Kaithakadan <nkaithakadan@marvell.com>,
Rupesh Chiluka <rchiluka@marvell.com>,
Sucharitha Sarananaga <ssarananaga@marvell.com>,
Vidya Sagar Velumuri <vvelumuri@marvell.com>, <dev@dpdk.org>
Subject: [PATCH v3 09/10] common/cnxk: optimize ROC layer
Date: Mon, 29 Sep 2025 15:13:52 +0530 [thread overview]
Message-ID: <20250929094353.1027744-10-ktejasree@marvell.com> (raw)
In-Reply-To: <20250929094353.1027744-1-ktejasree@marvell.com>
Adding ROC layer optimizations.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/cnxk/roc_cpt.c | 4 ++--
drivers/common/cnxk/roc_cpt_sg.h | 1 +
drivers/common/cnxk/roc_se.c | 10 +++++++++-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index c310d6432b..c467b55139 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -1173,10 +1173,10 @@ roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline, i
lmtline->io_addr = lf->io_addr;
lmtline->fc_thresh = lf->nb_desc - CPT_LF_FC_MIN_THRESHOLD;
- if (roc_model_is_cn10k()) {
+ if (roc_model_is_cn10k() || roc_model_is_cn20k()) {
if (is_dual) {
lmtline->io_addr |= ROC_CN10K_TWO_CPT_INST_DW_M1 << 4;
- lmtline->fc_thresh = lf->nb_desc - 2 * CPT_LF_FC_MIN_THRESHOLD;
+ lmtline->fc_thresh = lf->nb_desc - 2 * CPT_LF_FC_MIN_THRESHOLD;
} else {
lmtline->io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4;
}
diff --git a/drivers/common/cnxk/roc_cpt_sg.h b/drivers/common/cnxk/roc_cpt_sg.h
index 7c3caf94d7..d513bd7b7b 100644
--- a/drivers/common/cnxk/roc_cpt_sg.h
+++ b/drivers/common/cnxk/roc_cpt_sg.h
@@ -14,6 +14,7 @@
#define ROC_SG_ENTRY_SIZE sizeof(struct roc_sglist_comp)
#define ROC_SG_MAX_COMP 25
#define ROC_SG_MAX_DLEN_SIZE (ROC_SG_LIST_HDR_SIZE + (ROC_SG_MAX_COMP * ROC_SG_ENTRY_SIZE))
+
#define ROC_SG2_MAX_PTRS 48
#define ROC_SG1_MAX_PTRS 32
diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index 5a3ed0b647..f71832ff3a 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -268,10 +268,10 @@ int
roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint8_t *key,
uint16_t key_len, uint16_t mac_len)
{
+ uint8_t opcode_minor, opcode_major = 0;
struct roc_se_kasumi_ctx *k_ctx;
struct roc_se_pdcp_ctx *pctx;
struct roc_se_context *fctx;
- uint8_t opcode_minor;
bool chained_op;
if (se_ctx == NULL)
@@ -310,6 +310,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint
se_ctx->fc_type = ROC_SE_PDCP;
se_ctx->pdcp_auth_alg = ROC_SE_PDCP_ALG_TYPE_SNOW3G;
se_ctx->zsk_flags = 0x1;
+ opcode_major = ROC_SE_MAJOR_OP_PDCP_CHAIN;
break;
case ROC_SE_ZUC_EIA3:
if (unlikely(key_len != 16)) {
@@ -339,6 +340,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint
se_ctx->fc_type = ROC_SE_PDCP;
se_ctx->pdcp_auth_alg = ROC_SE_PDCP_ALG_TYPE_ZUC;
se_ctx->zsk_flags = 0x1;
+ opcode_major = ROC_SE_MAJOR_OP_PDCP_CHAIN;
break;
case ROC_SE_AES_CMAC_EIA2:
key_type = cpt_pdcp_chain_key_type_get(key_len);
@@ -356,6 +358,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint
se_ctx->pdcp_auth_alg = ROC_SE_PDCP_ALG_TYPE_AES_CMAC;
se_ctx->eia2 = 1;
se_ctx->zsk_flags = 0x1;
+ opcode_major = ROC_SE_MAJOR_OP_PDCP_CHAIN;
break;
case ROC_SE_KASUMI_F9_ECB:
/* Kasumi ECB mode */
@@ -363,11 +366,13 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint
memcpy(k_ctx->ci_key, key, key_len);
se_ctx->fc_type = ROC_SE_KASUMI;
se_ctx->zsk_flags = 0x1;
+ opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_DMA_MODE_SG;
break;
case ROC_SE_KASUMI_F9_CBC:
memcpy(k_ctx->ci_key, key, key_len);
se_ctx->fc_type = ROC_SE_KASUMI;
se_ctx->zsk_flags = 0x1;
+ opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_DMA_MODE_SG;
break;
default:
return -1;
@@ -385,6 +390,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint
else
opcode_minor = ((1 << 4) | 1);
+ se_ctx->template_w4.s.opcode_major = opcode_major;
se_ctx->template_w4.s.opcode_minor = opcode_minor;
return 0;
}
@@ -587,6 +593,7 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
success:
se_ctx->enc_cipher = type;
if (se_ctx->fc_type == ROC_SE_PDCP_CHAIN) {
+ se_ctx->template_w4.s.opcode_major = ROC_SE_MAJOR_OP_PDCP_CHAIN;
se_ctx->template_w4.s.opcode_minor = se_ctx->ciph_then_auth ? 2 : 3;
} else if (se_ctx->fc_type == ROC_SE_PDCP) {
if (roc_model_is_cn9k())
@@ -594,6 +601,7 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
((1 << 7) | (se_ctx->pdcp_ci_alg << 5) | (se_ctx->zsk_flags & 0x7));
else
opcode_minor = ((1 << 4));
+ se_ctx->template_w4.s.opcode_major = ROC_SE_MAJOR_OP_PDCP_CHAIN;
se_ctx->template_w4.s.opcode_minor = opcode_minor;
}
return 0;
--
2.25.1
next prev parent reply other threads:[~2025-09-29 9:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 9:43 [PATCH v3 00/10] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 01/10] common/cnxk: get context ilen as devarg Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 02/10] crypto/cnxk: fix compilation error and warnings Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 03/10] crypto/cnxk: add new API to get fpm tbl address Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 04/10] crypto/cnxk: add new API to get EC grp " Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 05/10] crypto/cnxk: align cptr to 256B in cn20k Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 06/10] crypto/cnxk: refactor rsa verification Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 07/10] crypto/cnxk: align PDCP API with latest firmware Tejasree Kondoj
2025-09-29 9:43 ` [PATCH v3 08/10] crypto/cnxk: support custom metadata with CN20K Tejasree Kondoj
2025-09-29 9:43 ` Tejasree Kondoj [this message]
2025-09-29 9:43 ` [PATCH v3 10/10] crypto/cnxk: fix tls mbuf sanity failures Tejasree Kondoj
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