From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
stephen@networkplumber.org
Subject: [PATCH v1 02/20] net/ntnic: add reset setup for NT400D11
Date: Wed, 1 Oct 2025 17:09:44 +0200 [thread overview]
Message-ID: <20251001151018.250671-3-sil-plv@napatech.com> (raw)
In-Reply-To: <20251001151018.250671-1-sil-plv@napatech.com>
Add base register initialization.
Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
.../nthw/core/nt400dxx/nthw_fpga_nt400dxx.c | 2 +-
.../core/nt400dxx/reset/nthw_fpga_rst9569.c | 54 ++++++++++++++++++-
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../supported/nthw_fpga_reg_defs_rst9569.h | 35 ++++++++++++
drivers/net/ntnic/ntnic_mod_reg.h | 3 +-
6 files changed, 93 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9569.h
diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c b/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c
index 99b317d916..8ae06417b8 100644
--- a/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/nthw_fpga_nt400dxx.c
@@ -132,7 +132,7 @@ static int nthw_fpga_nt400dxx_init(struct fpga_info_s *p_fpga_info)
return -1;
}
- res = rst9569_ops->nthw_fpga_rst9569_setup();
+ res = rst9569_ops->nthw_fpga_rst9569_setup(p_fpga, &rst);
if (res) {
NT_LOG(ERR,
diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9569.c b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9569.c
index 3d1c09fe2d..254703bae9 100644
--- a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9569.c
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst9569.c
@@ -4,10 +4,62 @@
*/
#include "ntnic_mod_reg.h"
+#include "nthw_register.h"
+#include "nthw_drv.h"
-static int nthw_fpga_rst9569_setup(void)
+static int nthw_fpga_rst9569_setup(nthw_fpga_t *p_fpga, struct nthw_fpga_rst_nt400dxx *const p)
{
+ RTE_ASSERT(p_fpga);
+ RTE_ASSERT(p);
+
+ const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+ const int n_fpga_product_id = p_fpga->mn_product_id;
+ const int n_fpga_version = p_fpga->mn_fpga_version;
+ const int n_fpga_revision = p_fpga->mn_fpga_revision;
+
+ nthw_module_t *p_mod_rst;
+ nthw_register_t *p_curr_reg;
+
+ p->n_fpga_product_id = n_fpga_product_id;
+ p->n_fpga_version = n_fpga_version;
+ p->n_fpga_revision = n_fpga_revision;
+
+ NT_LOG(DBG, NTHW, "%s: %s: FPGA reset setup: FPGA %04d-%02d-%02d", p_adapter_id_str,
+ __func__, n_fpga_product_id, n_fpga_version, n_fpga_revision);
+
+ p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9569, 0);
+
+ if (p_mod_rst == NULL) {
+ NT_LOG(ERR, NTHW, "%s: RST %d: no such instance", p_adapter_id_str, 0);
+ return -1;
+ }
+
+ /* RST register field pointers */
+ p_curr_reg = nthw_module_get_register(p_mod_rst, RST9569_RST);
+ p->p_fld_rst_sys = nthw_register_get_field(p_curr_reg, RST9569_RST_SYS);
+ p->p_fld_rst_ddr4 = nthw_register_get_field(p_curr_reg, RST9569_RST_DDR4);
+ p->p_fld_rst_phy_ftile = nthw_register_get_field(p_curr_reg, RST9569_RST_PHY_FTILE);
+ nthw_register_update(p_curr_reg);
+
+ p_curr_reg = nthw_module_get_register(p_mod_rst, RST9569_STAT);
+ p->p_fld_stat_ddr4_calib_complete =
+ nthw_register_get_field(p_curr_reg, RST9569_STAT_DDR4_CALIB_COMPLETE);
+ p->p_fld_stat_phy_ftile_rst_done =
+ nthw_register_get_field(p_curr_reg, RST9569_STAT_PHY_FTILE_RST_DONE);
+ p->p_fld_stat_phy_ftile_rdy =
+ nthw_register_get_field(p_curr_reg, RST9569_STAT_PHY_FTILE_RDY);
+ nthw_register_update(p_curr_reg);
+
+ p_curr_reg = nthw_module_get_register(p_mod_rst, RST9569_LATCH);
+ p->p_fld_latch_ddr4_calib_complete =
+ nthw_register_get_field(p_curr_reg, RST9569_LATCH_DDR4_CALIB_COMPLETE);
+ p->p_fld_latch_phy_ftile_rst_done =
+ nthw_register_get_field(p_curr_reg, RST9569_LATCH_PHY_FTILE_RST_DONE);
+ p->p_fld_latch_phy_ftile_rdy =
+ nthw_register_get_field(p_curr_reg, RST9569_LATCH_PHY_FTILE_RDY);
+ nthw_register_update(p_curr_reg);
+
return 0;
};
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index e2a98a737a..8d5837bac1 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -51,6 +51,7 @@
#define MOD_RPF (0x8d30dcddUL)
#define MOD_RPP_LR (0xba7f945cUL)
#define MOD_RST9563 (0x385d6d1dUL)
+#define MOD_RST9569 (0xd8888403UL)
#define MOD_RST9574 (0xbf22c9ffUL)
#define MOD_SDC (0xd2369530UL)
#define MOD_SLC (0x1aef1f38UL)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
index 5b824ef3e5..c16beb5faf 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -50,6 +50,7 @@
#include "nthw_fpga_reg_defs_rpl.h"
#include "nthw_fpga_reg_defs_rpp_lr.h"
#include "nthw_fpga_reg_defs_rst9563.h"
+#include "nthw_fpga_reg_defs_rst9569.h"
#include "nthw_fpga_reg_defs_rst9574.h"
#include "nthw_fpga_reg_defs_sdc.h"
#include "nthw_fpga_reg_defs_tsm.h"
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9569.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9569.h
new file mode 100644
index 0000000000..27e52b0b85
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9569.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2025 Napatech A/S
+ */
+
+/*
+ * nthw_fpga_reg_defs_rst9569.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RST9569_
+#define _NTHW_FPGA_REG_DEFS_RST9569_
+
+/* RST9569 */
+#define NTHW_MOD_RST9569 (0xd8888403UL)
+#define RST9569_LATCH (0x93ac825dUL)
+#define RST9569_LATCH_DDR4_CALIB_COMPLETE (0xf7a3f47eUL)
+#define RST9569_LATCH_PHY_FTILE_RDY (0xf189f59cUL)
+#define RST9569_LATCH_PHY_FTILE_RST_DONE (0x237710edUL)
+#define RST9569_RST (0x7cda32a2UL)
+#define RST9569_RST_DDR4 (0x215e3dadUL)
+#define RST9569_RST_PHY_FTILE (0xd633010bUL)
+#define RST9569_RST_SYS (0x74a18159UL)
+#define RST9569_STAT (0xce6f562UL)
+#define RST9569_STAT_DDR4_CALIB_COMPLETE (0x80a181a3UL)
+#define RST9569_STAT_PHY_FTILE_RDY (0x5bf72501UL)
+#define RST9569_STAT_PHY_FTILE_RST_DONE (0x26325becUL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_RST9569_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
index 62f69d239d..a4ea4f8f76 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.h
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -271,7 +271,8 @@ struct rst9574_ops {
struct rst9569_ops {
int (*nthw_fpga_rst9569_init)(void);
- int (*nthw_fpga_rst9569_setup)(void);
+ int (*nthw_fpga_rst9569_setup)(nthw_fpga_t *p_fpga,
+ struct nthw_fpga_rst_nt400dxx *const p);
};
void nthw_reg_rst9569_ops(struct rst9569_ops *ops);
--
2.45.0
next prev parent reply other threads:[~2025-10-01 15:10 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 15:09 [PATCH v1 00/20] Add NT400D11 support and new features Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 01/20] net/ntnic: add stubs for init NT400D11 Serhii Iliushyk
2025-10-01 15:09 ` Serhii Iliushyk [this message]
2025-10-01 15:09 ` [PATCH v1 03/20] net/ntnic: add reset init stage 0 for NT400D11 Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 04/20] net/ntnic: add reset init stage 1 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 05/20] net/ntnic: add reset init stage 2 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 06/20] net/ntnic: add reset init stage 3 and 4 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 07/20] net/ntnic: add reset init stage 5 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 08/20] net/ntnic: add reset init stage 6 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 09/20] net/ntnic: add reset init stage 7 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 10/20] net/ntnic: add reset init stage 8 " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 11/20] net/ntnic: add fpga registers " Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 12/20] net/ntnic: add support pattern matching on inner ETH headers Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 13/20] net/ntnic: add support pattern matching on inner VLAN header Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 14/20] net/ntnic: add handling exception path option Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 15/20] net/ntnic: add flow query with count action Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 16/20] net/ntnic: add flow pull Serhii Iliushyk
2025-10-01 15:09 ` [PATCH v1 17/20] net/ntnic: extend flow dump with MBR configuration Serhii Iliushyk
2025-10-01 15:10 ` [PATCH v1 18/20] net/ntnic: make flow lock local Serhii Iliushyk
2025-10-01 15:10 ` [PATCH v1 19/20] net/ntnic: rename hwlock Serhii Iliushyk
2025-10-01 15:10 ` [PATCH v1 20/20] net/ntnic: rename nt log types Serhii Iliushyk
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