From: Ciara Loftus <ciara.loftus@intel.com>
To: dev@dpdk.org
Cc: Ciara Loftus <ciara.loftus@intel.com>
Subject: [PATCH v2 6/7] net/i40e: reformat the Rx path infos array
Date: Wed, 15 Oct 2025 10:07:22 +0000 [thread overview]
Message-ID: <20251015100723.1603296-7-ciara.loftus@intel.com> (raw)
In-Reply-To: <20251015100723.1603296-1-ciara.loftus@intel.com>
In order to improve readability, reformat the rx path infos array.
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
v2:
* Newline for closing braces.
* Removed assignment of RTE_VECT_SIMD_DISABLED to simd_width, the
selection logic can work when this is set to zero for the scalar path.
---
drivers/net/intel/i40e/i40e_rxtx.c | 149 +++++++++++++++++++++++------
1 file changed, 118 insertions(+), 31 deletions(-)
diff --git a/drivers/net/intel/i40e/i40e_rxtx.c b/drivers/net/intel/i40e/i40e_rxtx.c
index 2bd0955225..255414dd03 100644
--- a/drivers/net/intel/i40e/i40e_rxtx.c
+++ b/drivers/net/intel/i40e/i40e_rxtx.c
@@ -3290,42 +3290,129 @@ i40e_recycle_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
}
static const struct ci_rx_path_info i40e_rx_path_infos[] = {
- [I40E_RX_DEFAULT] = { i40e_recv_pkts, "Scalar",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED}},
- [I40E_RX_SCATTERED] = { i40e_recv_scattered_pkts, "Scalar Scattered",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.scattered = true}}},
- [I40E_RX_BULK_ALLOC] = { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.bulk_alloc = true}}},
+ [I40E_RX_DEFAULT] = {
+ .pkt_burst = i40e_recv_pkts,
+ .info = "Scalar",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS
+ }
+ },
+ [I40E_RX_SCATTERED] = {
+ .pkt_burst = i40e_recv_scattered_pkts,
+ .info = "Scalar Scattered",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS,
+ .extra.scattered = true
+ }
+ },
+ [I40E_RX_BULK_ALLOC] = {
+ .pkt_burst = i40e_recv_pkts_bulk_alloc,
+ .info = "Scalar Bulk Alloc",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS,
+ .extra.bulk_alloc = true
+ }
+ },
#ifdef RTE_ARCH_X86
- [I40E_RX_SSE] = { i40e_recv_pkts_vec, "Vector SSE",
- {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}},
- [I40E_RX_SSE_SCATTERED] = { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered",
- {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_128,
- {.scattered = true, .bulk_alloc = true}}},
- [I40E_RX_AVX2] = { i40e_recv_pkts_vec_avx2, "Vector AVX2",
- {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, {.bulk_alloc = true}}},
- [I40E_RX_AVX2_SCATTERED] = { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered",
- {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256,
- {.scattered = true, .bulk_alloc = true}}},
+ [I40E_RX_SSE] = {
+ .pkt_burst = i40e_recv_pkts_vec,
+ .info = "Vector SSE",
+ .features = {
+ .rx_offloads = I40E_RX_VECTOR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_128,
+ .extra.bulk_alloc = true
+ }
+ },
+ [I40E_RX_SSE_SCATTERED] = {
+ .pkt_burst = i40e_recv_scattered_pkts_vec,
+ .info = "Vector SSE Scattered",
+ .features = {
+ .rx_offloads = I40E_RX_VECTOR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_128,
+ .extra.scattered = true,
+ .extra.bulk_alloc = true
+ }
+ },
+ [I40E_RX_AVX2] = {
+ .pkt_burst = i40e_recv_pkts_vec_avx2,
+ .info = "Vector AVX2",
+ .features = {
+ .rx_offloads = I40E_RX_VECTOR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_256,
+ .extra.bulk_alloc = true
+ }
+ },
+ [I40E_RX_AVX2_SCATTERED] = {
+ .pkt_burst = i40e_recv_scattered_pkts_vec_avx2,
+ .info = "Vector AVX2 Scattered",
+ .features = {
+ .rx_offloads = I40E_RX_VECTOR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_256,
+ .extra.scattered = true,
+ .extra.bulk_alloc = true
+ }
+ },
#ifdef CC_AVX512_SUPPORT
- [I40E_RX_AVX512] = { i40e_recv_pkts_vec_avx512, "Vector AVX512",
- {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}},
- [I40E_RX_AVX512_SCATTERED] = { i40e_recv_scattered_pkts_vec_avx512,
- "Vector AVX512 Scattered", {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512,
- {.scattered = true, .bulk_alloc = true}}},
+ [I40E_RX_AVX512] = {
+ .pkt_burst = i40e_recv_pkts_vec_avx512,
+ .info = "Vector AVX512",
+ .features = {
+ .rx_offloads = I40E_RX_VECTOR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_512,
+ .extra.bulk_alloc = true
+ }
+ },
+ [I40E_RX_AVX512_SCATTERED] = {
+ .pkt_burst = i40e_recv_scattered_pkts_vec_avx512,
+ .info = "Vector AVX512 Scattered",
+ .features = {
+ .rx_offloads = I40E_RX_VECTOR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_512,
+ .extra.scattered = true,
+ .extra.bulk_alloc = true
+ }
+ },
#endif
#elif defined(RTE_ARCH_ARM64)
- [I40E_RX_NEON] = { i40e_recv_pkts_vec, "Vector Neon",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}},
- [I40E_RX_NEON_SCATTERED] = { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128,
- {.scattered = true, .bulk_alloc = true}}},
+ [I40E_RX_NEON] = {
+ .pkt_burst = i40e_recv_pkts_vec,
+ .info = "Vector Neon",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_128,
+ .extra.bulk_alloc = true
+ }
+ },
+ [I40E_RX_NEON_SCATTERED] = {
+ .pkt_burst = i40e_recv_scattered_pkts_vec,
+ .info = "Vector Neon Scattered",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_128,
+ .extra.scattered = true,
+ .extra.bulk_alloc = true
+ }
+ },
#elif defined(RTE_ARCH_PPC_64)
- [I40E_RX_ALTIVEC] = { i40e_recv_pkts_vec, "Vector AltiVec",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}},
- [I40E_RX_ALTIVEC_SCATTERED] = { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered",
- {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128,
- {.scattered = true, .bulk_alloc = true}}},
+ [I40E_RX_ALTIVEC] = {
+ .pkt_burst = i40e_recv_pkts_vec,
+ .info = "Vector AltiVec",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_128,
+ .extra.bulk_alloc = true
+ }
+ },
+ [I40E_RX_ALTIVEC_SCATTERED] = {
+ .pkt_burst = i40e_recv_scattered_pkts_vec,
+ .info = "Vector AltiVec Scattered",
+ .features = {
+ .rx_offloads = I40E_RX_SCALAR_OFFLOADS,
+ .simd_width = RTE_VECT_SIMD_128,
+ .extra.scattered = true,
+ .extra.bulk_alloc = true
+ }
+ },
#endif
};
--
2.34.1
next prev parent reply other threads:[~2025-10-15 10:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-14 8:45 [PATCH 0/6] net/intel: fixes and improvements to rx path selection Ciara Loftus
2025-10-14 8:45 ` [PATCH 1/6] net/intel: fix Rx vector capability detection Ciara Loftus
2025-10-14 14:16 ` Bruce Richardson
2025-10-14 14:59 ` Loftus, Ciara
2025-10-14 8:45 ` [PATCH 2/6] net/iavf: fix Rx paths feature definitions Ciara Loftus
2025-10-14 14:26 ` Bruce Richardson
2025-10-14 8:45 ` [PATCH 3/6] net/iavf: fix Rx path selection for scalar flex bulk alloc Ciara Loftus
2025-10-14 14:33 ` Bruce Richardson
2025-10-14 8:45 ` [PATCH 4/6] net/iavf: reformat the Rx path infos array Ciara Loftus
2025-10-14 14:38 ` Bruce Richardson
2025-10-14 8:45 ` [PATCH 5/6] net/i40e: " Ciara Loftus
2025-10-14 14:38 ` Bruce Richardson
2025-10-14 8:45 ` [PATCH 6/6] net/ice: " Ciara Loftus
2025-10-14 14:39 ` Bruce Richardson
2025-10-15 10:07 ` [PATCH v2 0/7] net/intel: fixes and improvements to rx path selection Ciara Loftus
2025-10-15 10:07 ` [PATCH v2 1/7] net/intel: fix Rx vector capability detection Ciara Loftus
2025-10-15 10:07 ` [PATCH v2 2/7] net/intel: remove redundant Rx offload check Ciara Loftus
2025-10-15 10:07 ` [PATCH v2 3/7] net/iavf: fix Rx paths feature definitions Ciara Loftus
2025-10-15 10:07 ` [PATCH v2 4/7] net/iavf: fix Rx path selection for scalar flex bulk alloc Ciara Loftus
2025-10-15 10:07 ` [PATCH v2 5/7] net/iavf: reformat the Rx path infos array Ciara Loftus
2025-10-15 10:07 ` Ciara Loftus [this message]
2025-10-15 10:07 ` [PATCH v2 7/7] net/ice: " Ciara Loftus
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