From: Qiguo Chen <chen.qiguo@zte.com.cn>
To: stanislaw.kardach@gmail.com, sunyuechi@iscas.ac.cn,
stephen@networkplumber.org
Cc: dev@dpdk.org, bruce.richardson@intel.com,
Qiguo Chen <chen.qiguo@zte.com.cn>
Subject: [PATCH v1 0/2] Optimization Summary for RISC-V rte_memcpy
Date: Thu, 16 Oct 2025 17:09:32 +0800 [thread overview]
Message-ID: <20251016090934.1166954-1-chen.qiguo@zte.com.cn> (raw)
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I've implemented optimizations to rte_memcpy targeting RISC-V architectures,
achieving an average 10%~15% reduction in execution time for data sizes between
129 to 1024 bytes( 1025~1600 gains little).
These enhancements draw inspiration from x86 implementations,
specifically focusing on:
1)Alignment Handling for Unaligned Scenarios
2)Vector Configuration Tuning
3)Strategic Prefetching
- Patch 1: Cover letter
- Patch 2: Base implementation
- Patch 3: Benchmark report
Tested on Tested on SG2044 (VLEN=128)
Qiguo Chen (2):
riscv support rte_memcpy in vector
benchmark report for rte_memcpy
.mailmap | 1 +
benchmark_report.txt | 149 ++++++++++++++
config/riscv/meson.build | 14 ++
lib/eal/riscv/include/rte_memcpy.h | 310 ++++++++++++++++++++++++++++-
4 files changed, 472 insertions(+), 2 deletions(-)
create mode 100644 benchmark_report.txt
--
2.21.0.windows.1
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next reply other threads:[~2025-10-16 9:25 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 9:09 Qiguo Chen [this message]
2025-10-16 9:09 ` [PATCH v1 1/2] riscv support rte_memcpy in vector Qiguo Chen
2025-10-16 9:09 ` [PATCH v1 2/2] benchmark report for rte_memcpy Qiguo Chen
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