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(unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 6C6E93F704C; Wed, 22 Oct 2025 22:37:38 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v4 3/6] net/cnxk: get speed capability from firmware Date: Thu, 23 Oct 2025 11:07:15 +0530 Message-ID: <20251023053728.4091023-3-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023053728.4091023-1-skori@marvell.com> References: <20250814081637.1905660-6-skori@marvell.com> <20251023053728.4091023-1-skori@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: r4b71H1HK7DcHuU8G9vFBX2IX5QhtnhJ X-Proofpoint-GUID: r4b71H1HK7DcHuU8G9vFBX2IX5QhtnhJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIzMDAzMCBTYWx0ZWRfX4+vTK3biYd2u cDhuRyfC0GRcWuf5ItXhfz/Wvcaheu2xfC5wAG9FwjCgTnzkKnOdN5z5tfVYKu4C+tNq9Ju96oU VtSlzK5bd5gZ+Vx08feWMD8Qcjt2z5h6DfyGvs2llC7IBfII644z25h1Dda5o6HNPbZiumM/liD CLs0czP5l1oMIqr2w828HaiGqPCbHcATyFoD51MEWSFzsat4/lfTgqw0u4nw/KANNYcdSVlM74q EIMPoJ540nAvkIBxu5AY3kDE3JcFYWcNg0IVwNuJiR1x6kmK9Aj/QvOLWZ3wE3M2rmloagrVp9p cnkXq6qAdcVOHpZINVFg27cYhrffn5Oj8xrATkSKc7dlnmKvxm4P6TY7FFV8QGYAI9j9MqoJYCR l5+cPi+oM2CUdpUr2EFH8bhWTxQegQ== X-Authority-Analysis: v=2.4 cv=CtSys34D c=1 sm=1 tr=0 ts=68f9bf25 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=3CMRPe03__idA2T9rPcA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_08,2025-10-22_01,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Currently speed capability is hardcoded to support defined modes and speeds but MAC can support others modes and speed too. This information is populated by firmware. Hence fetching firmware data to provide actual supported modes and speeds by the port. Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 75 ++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 6c723c9cec..14e9707fcb 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -7,6 +7,60 @@ #include #include +static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { + [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_10G_C2C] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_C2M] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_KR] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_20G_C2C] = RTE_ETH_LINK_SPEED_20G, + [CGX_MODE_25G_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_C2M] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_2_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_CR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_KR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_40G_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_C2M] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_CR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_KR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40GAUI_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_50G_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_C2M] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_4_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_CR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_KR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_80GAUI_C2C] = 0, /* No define for 80G */ + [CGX_MODE_100G_C2C] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_C2M] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_CR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_KR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_LAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_LAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_CR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_KR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_100GAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_CR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_KR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_SFI_1G_BIT] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_25GBASE_CR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25GBASE_KR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [ETH_MODE_SGMII_10M_BIT] = RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_10M_HD, + [ETH_MODE_SGMII_100M_BIT] = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD, + [40] = 0, + [41] = 0, + [ETH_MODE_2500_BASEX_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5000_BASEX_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_O_USGMII_BIT] = RTE_ETH_LINK_SPEED_100M, + [ETH_MODE_Q_USGMII_BIT] = RTE_ETH_LINK_SPEED_1G, + [ETH_MODE_2_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_10G_SXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_DXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -42,14 +96,29 @@ nix_get_tx_offload_capa(struct cnxk_eth_dev *dev) static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { + struct roc_nix_mac_fwdata fwdata; uint32_t speed_capa; + uint8_t mode; + int rc; /* Auto negotiation disabled */ speed_capa = RTE_ETH_LINK_SPEED_FIXED; if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) { - speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G | - RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G | - RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G; + memset(&fwdata, 0, sizeof(fwdata)); + rc = roc_nix_mac_fwdata_get(&dev->nix, &fwdata); + if (rc) { + plt_err("Failed to get MAC firmware data"); + return 0; + } + + if (fwdata.supported_an) + speed_capa = 0; + + /* Translate advertised modes to speed_capa */ + for (mode = 0; mode < CGX_MODE_MAX; mode++) { + if (fwdata.supported_link_modes & BIT_ULL(mode)) + speed_capa |= cnxk_mac_modes[mode]; + } } return speed_capa; -- 2.43.0