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From: Soumyadeep Hore <soumyadeep.hore@intel.com>
To: dev@dpdk.org, bruce.richardson@intel.com
Cc: rajesh3.kumar@intel.com, aman.deep.singh@intel.com,
	manoj.kumar.subbarao@intel.com, stable@dpdk.org
Subject: [PATCH v1 1/3] net/ice: restrict testpmd to scalar path for TxPP
Date: Mon, 27 Oct 2025 14:27:59 -0400	[thread overview]
Message-ID: <20251027182801.191295-2-soumyadeep.hore@intel.com> (raw)
In-Reply-To: <20251027182801.191295-1-soumyadeep.hore@intel.com>

ICE PMD supports TxPP feature only in scalar path. Hence restricted
testpmd to scalar path when the feature is enabled.

Fixes: 0b6ff09a1f19 ("net/intel: support Tx packet pacing for E830")
Cc: stable@dpdk.org

Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/intel/ice/ice_rxtx.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/ice_rxtx.c
index fd0b3a7532..33d82cd46d 100644
--- a/drivers/net/intel/ice/ice_rxtx.c
+++ b/drivers/net/intel/ice/ice_rxtx.c
@@ -4103,8 +4103,11 @@ ice_set_tx_function(struct rte_eth_dev *dev)
 	struct ci_tx_queue *txq;
 	int i;
 	int tx_check_ret = -1;
+	uint64_t offloads;
 
-	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
+	offloads = dev->data->dev_conf.txmode.offloads;
+	if ((offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) == 0 &&
+		rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		ad->tx_simd_width = RTE_VECT_SIMD_DISABLED;
 		tx_check_ret = ice_tx_vec_dev_check(dev);
 		ad->tx_simd_width = ice_get_max_simd_bitwidth();
-- 
2.47.1


  reply	other threads:[~2025-10-27  5:47 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 18:27 [PATCH v1 0/3] Update TxPP feature Soumyadeep Hore
2025-10-27 18:27 ` Soumyadeep Hore [this message]
2025-10-27 18:28 ` [PATCH v1 2/3] net/ice: fix PTP clock corruption with TxPP Soumyadeep Hore
2025-10-27 18:28 ` [PATCH v1 3/3] doc: update TxPP documentation Soumyadeep Hore

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