From: Rongwei Liu <rongweil@nvidia.com>
To: <dev@dpdk.org>, <matan@nvidia.com>, <viacheslavo@nvidia.com>,
<orika@nvidia.com>, <suanmingm@nvidia.com>, <thomas@monjalon.net>
Cc: Dariusz Sosnowski <dsosnowski@nvidia.com>, Bing Zhao <bingz@nvidia.com>
Subject: [PATCH v1] net/mlx5: remove counter alignment
Date: Tue, 28 Oct 2025 11:26:11 +0200 [thread overview]
Message-ID: <20251028092611.1755141-1-rongweil@nvidia.com> (raw)
The memory footprint was increased due to the alignment.
Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
---
drivers/net/mlx5/mlx5_hws_cnt.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h
index f5b7e8f643..d19a7bf37e 100644
--- a/drivers/net/mlx5/mlx5_hws_cnt.h
+++ b/drivers/net/mlx5/mlx5_hws_cnt.h
@@ -43,7 +43,7 @@ struct mlx5_hws_cnt_dcs_mng {
};
union mlx5_hws_cnt_state {
- alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(uint32_t)data;
+ RTE_ATOMIC(uint32_t)data;
struct {
uint32_t in_used:1;
/* Indicator whether this counter in used or in pool. */
@@ -64,7 +64,7 @@ struct mlx5_hws_cnt {
struct flow_counter_stats reset;
union mlx5_hws_cnt_state cnt_state;
/* This struct is only meaningful when user own this counter. */
- alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(uint32_t)query_gen_when_free;
+ RTE_ATOMIC(uint32_t)query_gen_when_free;
/*
* When PMD own this counter (user put back counter to PMD
* counter pool, i.e), this field recorded value of counter
--
2.27.0
next reply other threads:[~2025-10-28 9:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 9:26 Rongwei Liu [this message]
2025-10-28 10:14 ` Dariusz Sosnowski
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