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(unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id B4CE65B6962; Tue, 4 Nov 2025 00:09:09 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v7 3/6] net/cnxk: get speed capability from firmware Date: Tue, 4 Nov 2025 13:38:51 +0530 Message-ID: <20251104080901.1610706-3-skori@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251104080901.1610706-1-skori@marvell.com> References: <20251023110332.6231-6-skori@marvell.com> <20251104080901.1610706-1-skori@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: BzkvhVTxe9txTtLkIRGO4WicjV8Z5T9B X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA0MDA2NiBTYWx0ZWRfX9Ke+owxoMZK9 I9wZcbSFXyms11cAMsKM+9meuOj7MxvUeI/5kGiL2wqVi3FsW4ENvltTCVV73J9DMBkh7ULA32t WWMBTXv/1Tut7rJGa5vdKNtSKn9yPhfrGg541E/hLxFGHUmbslWXupyzs1C2+eyj7ItCEK9tLuH +8M6LnqmFGfnlsw6FfMpD9xGkEKqKPQ0V3jPu02o41QAbdFQb+AcM6dtDLFhXkG9blFZWKBRnEw MrBPONZXfPCA+DNCd/r7aS1CzvOb68UQlNWqS8t+fbmFMZdS8JD2ybMLWayM4Jplzdkl8u5bebk qiU3X++ijNXhKg5yXdEoLXoZIfxN+2+vMdh2qS2vg8WZbzkRaD30iRaByPxLvkEDSUCx0LhpN2X wK1h8efoXvLgZCPaWDvtYxGvKV/j5w== X-Proofpoint-GUID: BzkvhVTxe9txTtLkIRGO4WicjV8Z5T9B X-Authority-Analysis: v=2.4 cv=N8Yk1m9B c=1 sm=1 tr=0 ts=6909b4ae cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=3CMRPe03__idA2T9rPcA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-03_06,2025-11-03_03,2025-10-01_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Currently speed capability is hardcoded to support defined modes and speeds but MAC can support others modes and speed too. This information is populated by firmware. Hence fetching firmware data to provide actual supported modes and speeds by the port. Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 75 ++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 6c723c9cec..14e9707fcb 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -7,6 +7,60 @@ #include #include +static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { + [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_10G_C2C] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_C2M] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_KR] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_20G_C2C] = RTE_ETH_LINK_SPEED_20G, + [CGX_MODE_25G_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_C2M] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_2_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_CR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_KR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_40G_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_C2M] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_CR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_KR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40GAUI_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_50G_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_C2M] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_4_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_CR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_KR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_80GAUI_C2C] = 0, /* No define for 80G */ + [CGX_MODE_100G_C2C] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_C2M] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_CR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_KR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_LAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_LAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_CR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_KR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_100GAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_CR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_KR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_SFI_1G_BIT] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_25GBASE_CR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25GBASE_KR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [ETH_MODE_SGMII_10M_BIT] = RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_10M_HD, + [ETH_MODE_SGMII_100M_BIT] = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD, + [40] = 0, + [41] = 0, + [ETH_MODE_2500_BASEX_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5000_BASEX_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_O_USGMII_BIT] = RTE_ETH_LINK_SPEED_100M, + [ETH_MODE_Q_USGMII_BIT] = RTE_ETH_LINK_SPEED_1G, + [ETH_MODE_2_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_10G_SXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_DXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -42,14 +96,29 @@ nix_get_tx_offload_capa(struct cnxk_eth_dev *dev) static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { + struct roc_nix_mac_fwdata fwdata; uint32_t speed_capa; + uint8_t mode; + int rc; /* Auto negotiation disabled */ speed_capa = RTE_ETH_LINK_SPEED_FIXED; if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) { - speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G | - RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G | - RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G; + memset(&fwdata, 0, sizeof(fwdata)); + rc = roc_nix_mac_fwdata_get(&dev->nix, &fwdata); + if (rc) { + plt_err("Failed to get MAC firmware data"); + return 0; + } + + if (fwdata.supported_an) + speed_capa = 0; + + /* Translate advertised modes to speed_capa */ + for (mode = 0; mode < CGX_MODE_MAX; mode++) { + if (fwdata.supported_link_modes & BIT_ULL(mode)) + speed_capa |= cnxk_mac_modes[mode]; + } } return speed_capa; -- 2.43.0