[PATCH 1/2] common/mlx5: read SWS capability bits

[PATCH 1/2] common/mlx5: read SWS capability bits

[Maayan Kashani]

SWS will be disabled in future HW generation.
Checking SWS capability bits and returning relevant error.
if user configuration is not supported,
will be added in the follow up commit.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 18 ++++++++++++++++++
 drivers/common/mlx5/mlx5_devx_cmds.h |  6 ++++++
 drivers/common/mlx5/mlx5_prm.h       | 14 ++++++++++----
 3 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 385759230a2..22f6b29089e 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1300,6 +1300,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 		rx_reg |= ((0xff & reg_c_8_15) << 8);
 		attr->set_reg_c &= (rx_reg & tx_reg);
 
+		attr->rx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
+						flow_table_properties_nic_receive.sw_owner_v2);
+		if (!attr->rx_sw_owner_v2)
+			attr->rx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
+						flow_table_properties_nic_receive.sw_owner);
+
+		attr->tx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
+						flow_table_properties_nic_transmit.sw_owner_v2);
+		if (!attr->tx_sw_owner_v2)
+			attr->tx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
+						flow_table_properties_nic_transmit.sw_owner);
+
 #undef GET_RX_REG_X_BITS
 #undef GET_TX_REG_X_BITS
 	}
@@ -1452,6 +1464,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 		reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
 				      ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
 		attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
+
+		attr->esw_sw_owner_v2 = MLX5_GET(flow_table_esw_cap, hcattr,
+						 flow_table_properties_nic_esw_fdb.sw_owner_v2);
+		if (!attr->esw_sw_owner_v2)
+			attr->esw_sw_owner = MLX5_GET(flow_table_esw_cap, hcattr,
+						 flow_table_properties_nic_esw_fdb.sw_owner);
 	}
 	return 0;
 error:
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index efae6826dcf..4c7747cbeca 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -336,6 +336,12 @@ struct mlx5_hca_attr {
 	uint8_t max_header_modify_pattern_length;
 	uint64_t system_image_guid;
 	uint32_t log_max_conn_track_offload:5;
+	uint8_t rx_sw_owner:1;
+	uint8_t rx_sw_owner_v2:1;
+	uint8_t tx_sw_owner:1;
+	uint8_t tx_sw_owner_v2:1;
+	uint8_t esw_sw_owner:1;
+	uint8_t esw_sw_owner_v2:1;
 };
 
 /* LAG Context. */
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 5db8d67cfc1..6cde3f8f1a1 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1593,9 +1593,13 @@ enum {
 #define MLX5_HCA_FLEX_GTPU_DW_0_ENABLED (1UL << 18)
 #define MLX5_HCA_FLEX_GTPU_TEID_ENABLED (1UL << 19)
 
-/* The device steering logic format. */
-#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
-#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
+/* The device steering logic format version. */
+enum {
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 = 0,
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX = 1,
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_7 = 2,
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_8 = 3,
+};
 
 struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 access_other_hca_roce[0x1];
@@ -2342,7 +2346,9 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
 };
 
 struct mlx5_ifc_flow_table_esw_cap_bits {
-	u8 reserved_at_0[0x800];
+	u8 reserved_at_0[0x200];
+	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
+	u8 reserved_at_400[0x400];
 	struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb;
 	u8 reserved_at_C00[0x800];
 	struct mlx5_ifc_ft_fields_support_2_bits
-- 
2.21.0

[PATCH 2/2] net/mlx5: update flow devarg handling for future HW

[Maayan Kashani]

SWS (software steering) will be disabled on future hardware generations.
Update the defaults for the dv_flow_en and allow_duplicate_pattern
devargs accordingly.

- Default dv_flow_en devarg value will be chosen based on whether
  NIC supports SW steering and/or HW steering.
- If DV flow is not supported and allow_duplicate_pattern is
  set by the user, forcibly disable it and emit a clear log message.

This change improves reliability by ensuring only valid
configurations are applied, and provides clear feedback to
the user when fallbacks are triggered.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/nics/mlx5.rst | 11 +++++--
 drivers/net/mlx5/mlx5.c  | 71 ++++++++++++++++++++++++++++++++++++++--
 2 files changed, 77 insertions(+), 5 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 37495359d4f..91983089702 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -694,8 +694,11 @@ for an additional list of options shared with other mlx5 drivers.
   Value 2 enables the WQE based hardware steering.
   In this mode, only queue-based flow management is supported.
 
-  It is configured by default to 1 (DV flow steering) if supported.
-  Otherwise, the value is 0 which indicates legacy Verbs flow offloading.
+  By default, the PMD will set this value according to capability.
+  If DV flow steering is supported, it will be set to 1.
+  If DV flow steering is not supported and HW steering is supported,
+  then it will be set to 2.
+  Otherwise, it will be set to 0.
 
 - ``dv_esw_en`` parameter [int]
 
@@ -838,8 +841,10 @@ for an additional list of options shared with other mlx5 drivers.
   - 1. Allow insertion of rules with the same pattern items.
     In this case, all rules are inserted but only the first rule takes effect,
     the next rule takes effect only if the previous rules are deleted.
+    This option is not supported in :ref:`HWS mode <mlx5_hws>`.
+    If this option is set to 1 in HWS mode, it will be set to 0.
 
-  By default, the PMD will set this value to 1.
+  By default, the PMD will set this value according to capability.
 
 
 .. _mlx5_net_stats:
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index ea235cf36be..dd3460f8d4b 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1443,6 +1443,45 @@ mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque)
 	return 0;
 }
 
+static bool
+mlx5_hws_is_supported(struct mlx5_dev_ctx_shared *sh)
+{
+	return (sh->cdev->config.devx &&
+	       sh->cdev->config.hca_attr.wqe_based_flow_table_sup);
+}
+
+static bool
+mlx5_sws_is_any_supported(struct mlx5_dev_ctx_shared *sh)
+{
+	struct mlx5_common_device *cdev = sh->cdev;
+	struct mlx5_hca_attr *hca_attr = &cdev->config.hca_attr;
+
+	if (hca_attr->rx_sw_owner_v2 || hca_attr->rx_sw_owner)
+		return true;
+
+	if (hca_attr->tx_sw_owner_v2 || hca_attr->tx_sw_owner)
+		return true;
+
+	if (hca_attr->eswitch_manager && (hca_attr->esw_sw_owner_v2 || hca_attr->esw_sw_owner))
+		return true;
+
+	return false;
+}
+
+static bool
+mlx5_kvargs_is_used(struct mlx5_kvargs_ctrl *mkvlist, const char *key)
+{
+	const struct rte_kvargs_pair *pair;
+	uint32_t i;
+
+	for (i = 0; i < mkvlist->kvlist->count; ++i) {
+		pair = &mkvlist->kvlist->pairs[i];
+		if (strcmp(pair->key, key) == 0 && mkvlist->is_used[i])
+			return true;
+	}
+	return false;
+}
+
 /**
  * Parse user device parameters and adjust them according to device
  * capabilities.
@@ -1484,6 +1523,8 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
 	int ret = 0;
 	size_t alignment = rte_mem_page_size();
 	uint32_t max_queue_umem_size = MLX5_WQE_SIZE * mlx5_dev_get_max_wq_size(sh);
+	bool hws_is_supported = mlx5_hws_is_supported(sh);
+	bool sws_is_supported = mlx5_sws_is_any_supported(sh);
 
 	if (alignment == (size_t)-1) {
 		alignment = (1 << MLX5_LOG_PAGE_SIZE);
@@ -1494,9 +1535,15 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
 	memset(config, 0, sizeof(*config));
 	config->vf_nl_en = 1;
 	config->dv_esw_en = 1;
-	config->dv_flow_en = 1;
+	if (!sws_is_supported && hws_is_supported)
+		config->dv_flow_en = 2;
+	else
+		config->dv_flow_en = 1;
 	config->decap_en = 1;
-	config->allow_duplicate_pattern = 1;
+	if (config->dv_flow_en == 2)
+		config->allow_duplicate_pattern = 0;
+	else
+		config->allow_duplicate_pattern = 1;
 	config->fdb_def_rule = 1;
 	config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT;
 	config->cnt_svc.service_core = rte_get_main_lcore();
@@ -1517,6 +1564,26 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
 		DRV_LOG(WARNING, "DV flow is not supported.");
 		config->dv_flow_en = 0;
 	}
+	/* Inform user if DV flow is not supported. */
+	if (config->dv_flow_en == 1 && !sws_is_supported && hws_is_supported) {
+		DRV_LOG(WARNING, "DV flow is not supported. Changing to HWS mode.");
+		config->dv_flow_en = 2;
+	}
+	/* Handle allow_duplicate_pattern based on final dv_flow_en mode.
+	 * HWS mode (dv_flow_en=2) doesn't support duplicate patterns.
+	 * Warn only if user explicitly requested an incompatible setting.
+	 */
+	bool allow_dup_pattern_set = mkvlist != NULL &&
+		mlx5_kvargs_is_used(mkvlist, MLX5_ALLOW_DUPLICATE_PATTERN);
+	if (config->dv_flow_en == 2) {
+		if (config->allow_duplicate_pattern == 1 && allow_dup_pattern_set)
+			DRV_LOG(WARNING, "Duplicate pattern is not supported with HWS. Disabling it.");
+		config->allow_duplicate_pattern = 0;
+	} else if (!allow_dup_pattern_set) {
+		/* Non-HWS mode: set default to 1 only if not explicitly set by user */
+		config->allow_duplicate_pattern = 1;
+	}
+
 	if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) {
 		DRV_LOG(DEBUG, "E-Switch DV flow is not supported.");
 		config->dv_esw_en = 0;
-- 
2.21.0

[PATCH 1/2] common/mlx5: read SWS capability bits

[Maayan Kashani]

SWS will be disabled in future HW generation.
Checking SWS capability bits and returning relevant error.
if user configuration is not supported,
will be added in the follow up commit.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |  2 ++
 drivers/common/mlx5/mlx5_devx_cmds.h |  2 ++
 drivers/common/mlx5/mlx5_prm.h       | 10 +++++++---
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 440820fd4ff..e1302a472aa 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1406,6 +1406,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 				      ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
 		attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
 	}
+	attr->sw_owner = MLX5_GET(flow_table_prop_layout, hcattr, sw_owner);
+	attr->sw_owner_v2 = MLX5_GET(flow_table_prop_layout, hcattr, sw_owner_v2);
 	return 0;
 error:
 	rc = (rc > 0) ? -rc : rc;
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 6c726a0d465..4a7879742ba 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -330,6 +330,8 @@ struct mlx5_hca_attr {
 	uint8_t max_header_modify_pattern_length;
 	uint64_t system_image_guid;
 	uint32_t log_max_conn_track_offload:5;
+	uint8_t sw_owner:1;
+	uint8_t sw_owner_v2:1;
 };
 
 /* LAG Context. */
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 742c274a856..86b09b6d0b1 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1591,9 +1591,13 @@ enum {
 #define MLX5_HCA_FLEX_GTPU_DW_0_ENABLED (1UL << 18)
 #define MLX5_HCA_FLEX_GTPU_TEID_ENABLED (1UL << 19)
 
-/* The device steering logic format. */
-#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
-#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
+/* The device steering logic format version. */
+enum {
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 = 0,
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX = 1,
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_7 = 2,
+	MLX5_STEERING_LOGIC_FORMAT_CONNECTX_8 = 3,
+};
 
 struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 access_other_hca_roce[0x1];
-- 
2.21.0

Re: [PATCH 1/2] common/mlx5: read SWS capability bits

[Raslan Darawsheh]

Hi,

On 27/04/2025 2:19 PM, Maayan Kashani wrote:
> SWS will be disabled in future HW generation.
> Checking SWS capability bits and returning relevant error.
> if user configuration is not supported,
> will be added in the follow up commit.
> 
> Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Series applied to next-net-mlx,

-- 
Kindest regards
Raslan Darawsheh

RE: [PATCH 1/2] common/mlx5: read SWS capability bits

[Maayan Kashani]

Hi. 
Please revert this patch as it is causing a degradation(mark SWS as not supported while it is supported).

Regards,
Maayan Kashani

> -----Original Message-----
> From: Raslan Darawsheh <rasland@nvidia.com>
> Sent: Tuesday, 13 May 2025 9:23
> To: Maayan Kashani <mkashani@nvidia.com>; dev@dpdk.org
> Cc: Dariusz Sosnowski <dsosnowski@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Ori Kam
> <orika@nvidia.com>; Suanming Mou <suanmingm@nvidia.com>; Matan
> Azrad <matan@nvidia.com>
> Subject: Re: [PATCH 1/2] common/mlx5: read SWS capability bits
> 
> Hi,
> 
> On 27/04/2025 2:19 PM, Maayan Kashani wrote:
> > SWS will be disabled in future HW generation.
> > Checking SWS capability bits and returning relevant error.
> > if user configuration is not supported, will be added in the follow up
> > commit.
> >
> > Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
> > Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> 
> Series applied to next-net-mlx,
> 
> --
> Kindest regards
> Raslan Darawsheh

Re: [PATCH 1/2] common/mlx5: read SWS capability bits

[Raslan Darawsheh]

Hi,

On 27/05/2025 11:58 AM, Maayan Kashani wrote:
> Hi.
> Please revert this patch as it is causing a degradation(mark SWS as not supported while it is supported).
> 
> Regards,
> Maayan Kashani

as it's not pulled to main tree yet, dropping from next-net-mlx


-- 
Kindest regards
Raslan Darawsheh