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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN3PEPF0000B073.mail.protection.outlook.com (10.167.243.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 05:06:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 16 Nov 2025 21:06:15 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 16 Nov 2025 21:06:11 -0800 From: Bing Zhao To: , , CC: , , , , , Nupur Uttarwar Subject: [PATCH] net/mlx5: skip Rx control flow tables in isolated mode Date: Mon, 17 Nov 2025 07:05:57 +0200 Message-ID: <20251117050557.8481-1-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B073:EE_|SJ2PR12MB8009:EE_ X-MS-Office365-Filtering-Correlation-Id: 060c0cc1-8c7c-4eb2-8cf2-08de25971802 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 05:06:40.4288 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 060c0cc1-8c7c-4eb2-8cf2-08de25971802 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8009 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Nupur Uttarwar If flow isolation is enabled, then skip flow_hw_create_ctrl_rx_tables because these are not used with flow isolation. This is used to save the unneeded resource allocation and also speed up the device startup time. Add Nupur Uttarwar user to mailmap in the meanwhile. Fixes: 9fa7c1cddb85 ("net/mlx5: create control flow rules with HWS") Cc: dsosnowski@nvidia.com Signed-off-by: Nupur Uttarwar Signed-off-by: Bing Zhao Acked-by: Dariusz Sosnowski --- .mailmap | 1 + drivers/net/mlx5/mlx5_flow.h | 2 ++ drivers/net/mlx5/mlx5_flow_hw.c | 17 ++++------------- drivers/net/mlx5/mlx5_trigger.c | 14 +++++++++++++- 4 files changed, 20 insertions(+), 14 deletions(-) diff --git a/.mailmap b/.mailmap index 50a59a596a..c4cfa2ccc5 100644 --- a/.mailmap +++ b/.mailmap @@ -1179,6 +1179,7 @@ Noa Ezra Nobuhiro Miki Norbert Ciosek Norbert Zulinski +Nupur Uttarwar Odi Assli Ofer Dagan Ognjen Joldzic diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 83a4adc971..a33a119b99 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -3056,6 +3056,8 @@ struct mlx5_flow_hw_ctrl_nic { #define MLX5_CTRL_VLAN_FILTER (RTE_BIT32(6)) int mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags); +int mlx5_flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev); +void mlx5_flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev); /** Create a control flow rule for matching unicast DMAC with VLAN (Verbs and DV). */ int mlx5_legacy_dmac_flow_create(struct rte_eth_dev *dev, const struct rte_ether_addr *addr); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index e0f79932a5..e34659abe7 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -11257,8 +11257,8 @@ flow_hw_create_vlan(struct rte_eth_dev *dev) return 0; } -static void -flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev) +void +mlx5_flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; unsigned int i; @@ -11543,8 +11543,8 @@ flow_hw_create_ctrl_rx_pattern_template return flow_hw_pattern_template_create(dev, &attr, items, NULL); } -static int -flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev) +int +mlx5_flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; unsigned int i; @@ -11580,8 +11580,6 @@ flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev) return 0; err: ret = rte_errno; - flow_hw_cleanup_ctrl_rx_tables(dev); - rte_errno = ret; return -ret; } @@ -11780,7 +11778,6 @@ __flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close) flow_hw_cleanup_ctrl_fdb_tables(dev); flow_hw_cleanup_ctrl_nic_tables(dev); flow_hw_cleanup_tx_repr_tagging(dev); - flow_hw_cleanup_ctrl_rx_tables(dev); flow_hw_action_template_drop_release(dev); grp = LIST_FIRST(&priv->flow_hw_grp); while (grp) { @@ -12138,12 +12135,6 @@ __flow_hw_configure(struct rte_eth_dev *dev, ret = flow_hw_action_template_drop_init(dev, error); if (ret) goto err; - ret = flow_hw_create_ctrl_rx_tables(dev); - if (ret) { - rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, - "Failed to set up Rx control flow templates"); - goto err; - } /* Initialize quotas */ if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) { ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas); diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 996c1eb6ac..23b093ca77 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1660,6 +1660,12 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) goto error; if (priv->isolated) return 0; + ret = mlx5_flow_hw_create_ctrl_rx_tables(dev); + if (ret) { + DRV_LOG(ERR, "Failed to set up Rx control flow templates for port %u, %d", + dev->data->port_id, -ret); + goto error; + } if (dev->data->promiscuous) flags |= MLX5_CTRL_PROMISCUOUS; if (dev->data->all_multicast) @@ -1673,6 +1679,7 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) error: ret = rte_errno; mlx5_flow_hw_flush_ctrl_flows(dev); + mlx5_flow_hw_cleanup_ctrl_rx_tables(dev); rte_errno = ret; return -rte_errno; } @@ -1913,8 +1920,13 @@ mlx5_traffic_disable(struct rte_eth_dev *dev) #ifdef HAVE_MLX5_HWS_SUPPORT struct mlx5_priv *priv = dev->data->dev_private; - if (priv->sh->config.dv_flow_en == 2) + if (priv->sh->config.dv_flow_en == 2) { + /* Device started flag was cleared before, this is used to derefer the Rx queues. */ + priv->hws_rule_flushing = true; mlx5_flow_hw_flush_ctrl_flows(dev); + mlx5_flow_hw_cleanup_ctrl_rx_tables(dev); + priv->hws_rule_flushing = false; + } else #endif mlx5_traffic_disable_legacy(dev); -- 2.34.1