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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1PEPF000042AE.mail.protection.outlook.com (10.167.243.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 07:42:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 16 Nov 2025 23:42:17 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 16 Nov 2025 23:42:13 -0800 From: Bing Zhao To: , , CC: , , , , Subject: [PATCH v2 2/2] net/mlx5: use private structure for internal tag item Date: Mon, 17 Nov 2025 09:41:59 +0200 Message-ID: <20251117074159.9480-1-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251117041537.8161-1-bingz@nvidia.com> References: <20251117041537.8161-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AE:EE_|MN2PR12MB4357:EE_ X-MS-Office365-Filtering-Correlation-Id: ca672269-ed26-4722-3a64-08de25acdf91 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 07:42:34.7626 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca672269-ed26-4722-3a64-08de25acdf91 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4357 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The legacy DV API is used to translate the mask of a matcher and the value of a rule on the root table, no matter it is in SWS or HWS mode. The structure "mlx5_rte_flow_item_tag" is used instead of public "rte_flow_item_tag". This is used internally to speed up and simplify the usage of the available REG_Cs. Since the offsets of the fields are different, the DV API would get the incorrect value when constructuing the matcher and value. The private structure should be used for the DV API. Also, in the validation stage, the proper structure should be used. Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching") Fixes: ddb68e47331e ("net/mlx5: add extended metadata mode for HWS") Fixes: 26e1eaf2dac4 ("net/mlx5: support device control for E-Switch default rule") Signed-off-by: Bing Zhao --- v2: fix the building failure of the unknown private structure size by using memcpy --- drivers/net/mlx5/mlx5.h | 4 +-- drivers/net/mlx5/mlx5_flow_hw.c | 46 ++++++++++++++++----------------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 7e4bfacd11..3d1b5371f0 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -469,8 +469,8 @@ struct mlx5_flow_hw_pattern_params { struct rte_flow_item items[MLX5_HW_MAX_ITEMS]; /** Temporary REPRESENTED_PORT item generated by PMD. */ struct rte_flow_item_ethdev port_spec; - /** Temporary TAG item generated by PMD. */ - struct rte_flow_item_tag tag_spec; + /** Temporary internal MLX5_TAG item generated by PMD, no more than 2 DWs. */ + uint8_t mlx5_tag_spec[sizeof(uint32_t) * 2]; }; /* HW steering flow management job descriptor. */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index e0f79932a5..f759a50d36 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3844,6 +3844,10 @@ flow_hw_get_rule_items(struct rte_eth_dev *dev, struct mlx5_flow_hw_pattern_params *pp) { struct rte_flow_pattern_template *pt = table->its[pattern_template_index]; + struct mlx5_rte_flow_item_tag mlx5_tag = { + .id = REG_C_0, /* vport_meta_tag is using C_0 */ + .data = flow_hw_tx_tag_regc_value(dev), + }; /* Only one implicit item can be added to flow rule pattern. */ MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag); @@ -3855,7 +3859,7 @@ flow_hw_get_rule_items(struct rte_eth_dev *dev, return NULL; } /* Set up represented port item in pattern params. */ - pp->port_spec = (struct rte_flow_item_ethdev){ + pp->port_spec = (struct rte_flow_item_ethdev) { .port_id = dev->data->port_id, }; pp->items[0] = (struct rte_flow_item){ @@ -3870,12 +3874,10 @@ flow_hw_get_rule_items(struct rte_eth_dev *dev, return NULL; } /* Set up tag item in pattern params. */ - pp->tag_spec = (struct rte_flow_item_tag){ - .data = flow_hw_tx_tag_regc_value(dev), - }; - pp->items[0] = (struct rte_flow_item){ + rte_memcpy(pp->mlx5_tag_spec, mlx5_tag, sizeof(struct mlx5_rte_flow_item_tag)); + pp->items[0] = (struct rte_flow_item) { .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG, - .spec = &pp->tag_spec, + .spec = (const void *)&pp->mlx5_tag_spec, }; rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb); return pp->items; @@ -8559,21 +8561,21 @@ __flow_hw_pattern_validate(struct rte_eth_dev *dev, } case MLX5_RTE_FLOW_ITEM_TYPE_TAG: { - const struct rte_flow_item_tag *tag = - (const struct rte_flow_item_tag *)item->spec; + const struct mlx5_rte_flow_item_tag *mlx5_tag = + (const struct mlx5_rte_flow_item_tag *)item->spec; uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c; - if (!((1 << (tag->index - REG_C_0)) & regcs)) + if (!((1 << (mlx5_tag->id - REG_C_0)) & regcs)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "Unsupported internal tag index"); - if (tag_bitmap & (1 << tag->index)) + if (tag_bitmap & (1 << mlx5_tag->id)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Duplicated tag index"); - tag_bitmap |= 1 << tag->index; + tag_bitmap |= 1 << mlx5_tag->id; break; } case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: @@ -9028,13 +9030,13 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT, .mask = &rte_flow_item_ethdev_mask, }; - struct rte_flow_item_tag tag_v = { + struct mlx5_rte_flow_item_tag tag_v = { .data = 0, - .index = REG_C_0, + .id = REG_C_0, }; - struct rte_flow_item_tag tag_m = { + struct mlx5_rte_flow_item_tag tag_m = { .data = flow_hw_tx_tag_regc_mask(dev), - .index = 0xff, + .id = (enum modify_reg)0xff, }; struct rte_flow_item tag = { .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG, @@ -10119,11 +10121,11 @@ flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev, .relaxed_matching = 0, .transfer = 1, }; - struct rte_flow_item_tag reg_c0_spec = { - .index = (uint8_t)REG_C_0, + struct mlx5_rte_flow_item_tag reg_c0_spec = { + .id = (uint8_t)REG_C_0, }; - struct rte_flow_item_tag reg_c0_mask = { - .index = 0xff, + struct mlx5_rte_flow_item_tag reg_c0_mask = { + .id = (enum modify_reg)0xff, .data = flow_hw_esw_mgr_regc_marker_mask(dev), }; struct mlx5_rte_flow_item_sq queue_mask = { @@ -10131,14 +10133,12 @@ flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev, }; struct rte_flow_item items[] = { { - .type = (enum rte_flow_item_type) - MLX5_RTE_FLOW_ITEM_TYPE_TAG, + .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG, .spec = ®_c0_spec, .mask = ®_c0_mask, }, { - .type = (enum rte_flow_item_type) - MLX5_RTE_FLOW_ITEM_TYPE_SQ, + .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ, .mask = &queue_mask, }, { -- 2.34.1