[PATCH 2/2] net/mlx5: fix the masked value for a rule for sync API

[Bing Zhao <bingz@nvidia.com>]

When inserting a rule via HWS synchronous API, the underlayer
implementaiton is a bit different from HWS. The template(async)
API calls are re-used. In the template API definition, the user
should ensure that there is no value bit that is not masked by
the template.

In the legacy SWS synchronous API, when translating the item, if a
mask is provided together with the spec. The value is the result of
the spec OP-AND mask. If no mask, a default mask with all 1s are used
and the value of the spec remain the original input.

By introducing the new logic to do the OP-AND and duplicate the
items from the input in the rte_flow layer. The spec field will
be with the correct value after inline OP-AND calculating. The rule
will be inserted with proper value as expected by the user.

Fixes: e38776c36c8a ("net/mlx5: introduce HWS for non-template flow API")
Cc: mkashani@nvidia.com

Signed-off-by: Bing Zhao <bingz@nvidia.com>
---
Depends-on: patch-158854("lib/ethdev: support inline calculating masked item value")
---
 drivers/net/mlx5/mlx5_flow.h    |  2 ++
 drivers/net/mlx5/mlx5_flow_hw.c | 43 ++++++++++++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index e890e732c3..2239f20bbf 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1945,6 +1945,8 @@ struct mlx5_flow_workspace {
 	/* The final policy when meter policy is hierarchy. */
 #ifdef HAVE_MLX5_HWS_SUPPORT
 	struct rte_flow_template_table *table;
+	struct rte_flow_item *masked_items;
+	size_t masked_items_size;
 #endif
 	uint32_t skip_matcher_reg:1;
 	/* Indicates if need to skip matcher register in translate. */
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 6dc16f80d3..4c3056e8b2 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -13952,6 +13952,42 @@ static int flow_hw_apply(const struct rte_flow_item items[],
 }
 
 #ifdef HAVE_MLX5_HWS_SUPPORT
+
+static inline
+int flow_hw_duplicate_items(struct mlx5_flow_workspace *pt_wks,
+			    const struct rte_flow_item items[],
+			    struct rte_flow_error *error)
+{
+	int ret = 0;
+	size_t len;
+
+	/* Only the specs are needed for the rule. */
+	ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, items, error);
+	if (ret <= 0) {
+		DRV_LOG(ERR, "Can't get items length.");
+		return -rte_errno;
+	}
+	len = (size_t)RTE_ALIGN(ret, 16);
+	if (len > pt_wks->masked_items_size) {
+		pt_wks->masked_items = mlx5_realloc(pt_wks->masked_items, MLX5_MEM_ZERO,
+						    len, 0, SOCKET_ID_ANY);
+		if (!pt_wks->masked_items) {
+			rte_flow_error_set(error, ENOMEM,
+					   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+					   NULL,
+					   "No enough memory for items caching.");
+			return -rte_errno;
+		}
+		pt_wks->masked_items_size = len;
+	}
+	ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN_MASKED, pt_wks->masked_items,
+			    len, items, error);
+	if (ret <= 0) {
+		DRV_LOG(ERR, "Can't duplicate items' specs.");
+		return ret;
+	}
+	return 0;
+}
 /**
  * Create a flow.
  *
@@ -14001,6 +14037,8 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
 		.act_flags = action_flags,
 		.tbl_type = 0,
 	};
+	int len;
+	struct mlx5_flow_workspace *pt_wks = mlx5_flow_push_thread_workspace();
 
 	if (attr->transfer)
 		tbl_type = MLX5DR_TABLE_TYPE_FDB;
@@ -14065,7 +14103,10 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
 	if (external || dev->data->dev_started ||
 	    (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
 	     attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
-		ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
+		ret = flow_hw_duplicate_items(pt_wks, items, error);
+		if (ret)
+			goto error;
+		ret = flow_hw_apply(pt_wks->masked_items, hw_act.rule_acts, *flow, error);
 		if (ret)
 			goto error;
 	}
-- 
2.34.1