From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id E6FCF2C18 for ; Fri, 28 Apr 2017 11:21:29 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 02B0B20977; Fri, 28 Apr 2017 05:21:29 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute1.internal (MEProxy); Fri, 28 Apr 2017 05:21:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=tzovK0SxRlTzQgm Skk2D/q+/SGFAakMinQgxQd4dGyM=; b=qUBncvc+mamdAPCUs5r2Vhrd6BmgQhH M1FZ6TdFE3nw/HX4fjnVghmA9n9FLHx2dsllsR2Eia/jKfQf6LNtR6pGdEIlqvNT Li833/tcaDsX37C8+157xDR9Weocqjy3VkKH0YqcJKn8cpB54GGgufX8Gm+zhCFG DR0Ud2hV4adg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=tzovK0SxRlTzQgmSkk2D/q+/SGFAakMinQgxQd4dGyM=; b=jY7KFTIx ZoCnl99vRO25jFjORFc6UN3fSA0erHUBQp4vIzi3Es2GexU3dY0HiIZJ8UBtN5r0 zeN03F4sizDHh0eovdfZwqLolc8d9+2hAqYV1RV/3oEPTYNonbatX61pE01Ks50s huwOle2dhbSdRSJuu6ODmbxPTEsGJQ5JkkvzahgSz4ggUqEwn+wXfp6dr0VhWZ2K +Zo+oSmZU/uRUaR9yVZcR9X2PbSs4ekxEhD7qlfNc4r9hKYR2z+9yhaXRHHLFibf VEj+VULa3TDs0ZGZe9TO6Jb7LmJcC65zm6ZMYccixh4SpXf53ZO/ZVkQeE+A+m7V gm9Hi3NFoDlavA== X-ME-Sender: X-Sasl-enc: rM8xTP3madqHU3xZe66WvLhMVCRhx6XQuv6du4SMDSPF 1493371288 Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id AE0B52415E; Fri, 28 Apr 2017 05:21:28 -0400 (EDT) From: Thomas Monjalon To: Bruce Richardson Cc: dev@dpdk.org, olivier.matz@6wind.com Date: Fri, 28 Apr 2017 11:21:27 +0200 Message-ID: <2039188.oPr2FiSFIW@xps> In-Reply-To: <20170428090306.GA25692@bricha3-MOBL3.ger.corp.intel.com> References: <20170428081551.28954-1-bruce.richardson@intel.com> <1797441.atIi8ZZIaG@xps> <20170428090306.GA25692@bricha3-MOBL3.ger.corp.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] eal: fix 64bit address alignment in 32-bit builds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Apr 2017 09:21:30 -0000 28/04/2017 11:03, Bruce Richardson: > On Fri, Apr 28, 2017 at 10:56:56AM +0200, Thomas Monjalon wrote: > > 28/04/2017 10:15, Bruce Richardson: > > > On i686 builds, the uint64_t type is 64-bits in size but is aligned to > > > 32-bits only. This causes mbuf fields for rearm_data to not be 16-byte > > > aligned on 32-bit builds, which causes errors with some vector PMDs which > > > expect the rearm data to be aligned as on 64-bit. > > > > > > Given that we cannot use the extra space in the data structures anyway, as > > > it's already used on 64-bit builds, we can just force alignment of physical > > > address structure members to 8-bytes in all cases. This has no effect on > > > 64-bit systems, but fixes the updated PMDs on 32-bit. > > > > I agree to align on 64-bit in mbuf. > > > > > Fixes: f4356d7ca168 ("net/i40e: eliminate mbuf write on rearm") > > > Fixes: f160666a1073 ("net/ixgbe: eliminate mbuf write on rearm") > > [...] > > > --- a/lib/librte_eal/common/include/rte_memory.h > > > +++ b/lib/librte_eal/common/include/rte_memory.h > > > -typedef uint64_t phys_addr_t; /**< Physical address definition. */ > > > +/** Physical address definition. */ > > > +typedef uint64_t phys_addr_t __rte_aligned(sizeof(uint64_t)); > > > > Why setting this constraint for everyone? > > > Well, it only has an effect on 32-bit builds, and unless there is a > problem, I don't see why not always align them to the extra 8 bytes. If > this does cause an issue, I'm happy enough to use #ifdefs, but in the > absense of a confirmed problem, I'd rather keep the code clean. Is it expected for everyone to have every physical addresses aligned on 64? I think it can be weird for some applications. Why do you think it is cleaner than adding the alignment to the mbuf fields? PS: It is yet another macro which is not rte_ prefixed.