From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8C4DA04DB; Thu, 15 Oct 2020 22:33:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8522E1DEB6; Thu, 15 Oct 2020 22:33:31 +0200 (CEST) Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by dpdk.org (Postfix) with ESMTP id A51C81DE80 for ; Thu, 15 Oct 2020 22:33:29 +0200 (CEST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.nyi.internal (Postfix) with ESMTP id EC56A5C010A; Thu, 15 Oct 2020 16:33:28 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Thu, 15 Oct 2020 16:33:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= Yv74fZQ7ZJHk424AIpyik/MCV1F27zGucek41+DqkZ8=; b=rdwXRRfdRbsj944X RhPyGSeGqV7huEYehSLmQJcw/snvj5YdrWGx4YjCPVw3hbpkOTnz4vYi1o4jrMUi im6i29adj9QqhE00UkuS6aiDYhkSGVFIPsVOivQNPHT4Qpbj1AcpSQxAXmwYcIL7 6eL2jFS5GrWwB3ncJ+BvAaSbR0cUEjEs/d1L2hYLFi3so5CV8gOZ5u3j4mea6Ner pjaXWgjsVAzVO3OgK7EROowNpMU2TEWvDQKRwIt6C0lKORUxBWFubuH75uM/4TF4 uXdKdvvPazzDTTBCFW53303+yWMKcmyaDgKdfiyFDhOfeA9yYozF6UmxrV2XIIh+ PCnByg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=Yv74fZQ7ZJHk424AIpyik/MCV1F27zGucek41+Dqk Z8=; b=lt6CiStcthAg0gKki49D2fR6ZzduYebDZzbYkeioaKJfQtMvoBu2g1Evf 39mdMDh719qjvZEBoQkA5TNQscGwCpENA3o7Hj6Wpxfc1ueURhsrj8ilrFAxC+65 ie4elwXBzHPE/cruKayi/bYN/ha3xMu/hU7LP7eWulNgPkhA01zu1R3oCERo3isZ VRjusBk82vywDAPKWj+j1AlMCX++PTMAT+htF5ofPcJerCFRnU4tjKkoU7HnxHQU CMS7JlsFTsUhMaPwJ+Ddy8xAtpRkOuq/A7bt8pCZ+34EhcQS3PIPwImOT7Ri7aF2 adecLtjeeqAcxZ6IfVn7ecUEQ96iQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrieefgddugeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepudeggfdvfeduffdtfeeglefghfeukefgfffhueejtdetuedtjeeu ieeivdffgeehnecukfhppeejjedrudefgedrvddtfedrudekgeenucevlhhushhtvghruf hiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghl ohhnrdhnvght X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 83D3E328005D; Thu, 15 Oct 2020 16:33:26 -0400 (EDT) From: Thomas Monjalon To: Viacheslav Ovsiienko Cc: dev@dpdk.org, stephen@networkplumber.org, ferruh.yigit@intel.com, olivier.matz@6wind.com, jerinjacobk@gmail.com, maxime.coquelin@redhat.com, david.marchand@redhat.com, arybchenko@solarflare.com Date: Thu, 15 Oct 2020 22:33:25 +0200 Message-ID: <2268221.MQrTK4cY7P@thomas> In-Reply-To: <1602793044-28736-2-git-send-email-viacheslavo@nvidia.com> References: <1602793044-28736-1-git-send-email-viacheslavo@nvidia.com> <1602793044-28736-2-git-send-email-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v7 1/6] ethdev: introduce Rx buffer split X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 15/10/2020 22:17, Viacheslav Ovsiienko: > /** > + * Ethernet device Rx buffer segmentation capabilities. > + */ > +struct rte_eth_rxseg_capa { > + uint16_t max_seg; /**< Maximum amount of segments to split. */ > + uint8_t multi_pools; /**< Supports receiving to multiple pools.*/ > + uint8_t offset_allowed; /**< Supports buffer offsets. */ > + uint8_t offset_align_log2; /**< Required offset alignment. */ > +}; Why not having bit fields for these last three?