From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2B7EEA053D; Fri, 17 Jul 2020 17:08:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 06B141BF44; Fri, 17 Jul 2020 17:08:13 +0200 (CEST) Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id CEAE31BEE6 for ; Fri, 17 Jul 2020 17:08:10 +0200 (CEST) Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 7E0A05C00FF; Fri, 17 Jul 2020 11:08:09 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); Fri, 17 Jul 2020 11:08:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm1; bh= SV84IdWvWx5kodnuzFEgYB14FCjKUiTRUU/JFboPoDQ=; b=L8deadUaY5JLUsrU VMo/xLysWg1MjPLSlL3NG2fycuA8xnBFXLBKYzCToTY09HWDdWplQKHmXOmDjqvn 1iAxP2yTxBJB229p4r7eqj8E2vaRr5D017hbP1IqWncmKVVT7Wsfwtei4UfcutlO L7yXuGRKHl62Lznnc61/PBZkedJdQ7fts8VTzg5Y7r9UIzuFVIoMq/G8Bm9iN9B5 3QRPG8/NApb8pQwLFqQsLr51JT/DLQ+/oc93gIbxE6UmUlI9gCjaiOUcz/c7Un7t SB0i++B3dVIm1DRFbAX+Gh4CNqgjAAPWVXx6JRFwz2CykI4LPNUvAMlUjiXrdXZi +R2psA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=SV84IdWvWx5kodnuzFEgYB14FCjKUiTRUU/JFboPo DQ=; b=PoKLceecUpEy9KERduW/AexwNDYziX3jGOtZZvuEL426lXybdW2qvwn5V vrUgBy1gAGW0/IjkgvpcBh3fjSYGVHyuOZtawS0H6KCQSqz+P3bkzcF0x+VmqMQv iC+dd3ORDHLj5oLuUsInArQYbEA6JQqI0zK40wfCVHiKyb5ciDhVsHiuUGJR5kua +c5SIxFFKiW40JbZzl0fnln9aRFtqR5qKHRtCgOPOVECen+lVIg80Oa6oOgONsxb PRWH83C2hpAJte1tner888g1PTvQbyD8WNhEyjsHvsAOTrkJd0GonL9K5V4L3Sy5 pL+534wCJMDEUMYTXXAIIGhD2bs3w== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduiedrfeeigdekfecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpedugefgvdefudfftdefgeelgffhueekgfffhfeujedtteeutdejueei iedvffegheenucfkphepjeejrddufeegrddvtdefrddukeegnecuvehluhhsthgvrhfuih iivgepudenucfrrghrrghmpehmrghilhhfrhhomhepthhhohhmrghssehmohhnjhgrlhho nhdrnhgvth X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id BC691328005D; Fri, 17 Jul 2020 11:08:08 -0400 (EDT) From: Thomas Monjalon To: Viacheslav Ovsiienko Cc: dev@dpdk.org, matan@mellanox.com, rasland@mellanox.com Date: Fri, 17 Jul 2020 17:08:07 +0200 Message-ID: <2274386.9mWquJPBei@thomas> In-Reply-To: <1594996104-372-2-git-send-email-viacheslavo@mellanox.com> References: <1591771085-24959-1-git-send-email-viacheslavo@mellanox.com> <1594996104-372-1-git-send-email-viacheslavo@mellanox.com> <1594996104-372-2-git-send-email-viacheslavo@mellanox.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH 2/3] net/mlx5: fix compilation issue with atomic128 exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 17/07/2020 16:28, Viacheslav Ovsiienko: > For naw the rte_atomic128_cmp_exchange() is available on x86-64 Typo: now > and ARM64 architectures. The patch fixes the compilation condition > for the code using this atomic transaction. What is fixed exactly? How "not (ppc or 32)" is different of "x86_64 or arm64"? > -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32) > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > + rte_int128_t src; > + > + memset(&src, 0, sizeof(src)); > + *ts = src; > + /* if (*from == *ts) *from = *src else *ts = *from; */ > + rte_atomic128_cmp_exchange(from, ts, &src, 0, > + __ATOMIC_RELAXED, __ATOMIC_RELAXED); > +#else > rte_atomic64_t *cqe = (rte_atomic64_t *)from; > > /* Power architecture does not support 16B compare-and-swap. */ > @@ -665,14 +673,6 @@ > ps[1] = op; > return; > } > -#else > - rte_int128_t src; > - > - memset(&src, 0, sizeof(src)); > - *ts = src; > - /* if (*from == *ts) *from = *src else *ts = *from; */ > - rte_atomic128_cmp_exchange(from, ts, &src, 0, > - __ATOMIC_RELAXED, __ATOMIC_RELAXED); > #endif