From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7B5145501; Wed, 26 Jun 2024 14:02:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 549A743430; Wed, 26 Jun 2024 13:56:12 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id CEEFE42EF8 for ; Wed, 26 Jun 2024 13:44:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402286; x=1750938286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KFRmSvAwK6XxoMHl6C9thi9kfmNM+3doG47B+1MoPvg=; b=GV6c4vsDP7fT1Dm3i6GGjXoDphqJbWiJj6nH+uRabm4qFqM5Dyb2u5Sg xekfd1Uh+k3TgQ72ovs8oKXZWEl62fFq9l8CeOmvEL/NRKJjTuEy27HIY BNJ1rj4Ro5jq+C3Z421TeGc1NaJ6QNnYcBqhDbVP//LG+fRZtCx9X1h9c aPM+2JpMXFJMOLbYsRwWR5dFruWlyGQscdtkw8x3aKt1v6ER2pKGspFpN YZeFwv71vtfSH8uR2sqyCu7HdZGSerjw4l2hfzuwaaIlk/MxxdrwGD+4p 4rE+V+k7z2+p/SvnBT2N8iB2Js5TszV4tJAwZLMv/JqdTsKSPZwINL5my g==; X-CSE-ConnectionGUID: M41XHBI9SLuaaHag+bgi/g== X-CSE-MsgGUID: njPAbt7KTb25mVZql7rMQA== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979463" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979463" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:44:45 -0700 X-CSE-ConnectionGUID: 5x/TurGQQTKcRi2XNJeXzQ== X-CSE-MsgGUID: KO4P++vlSzO0aJ5ySzaF9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874057" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:44:44 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Sergey Temerkhanov , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 063/103] net/ice/base: enable SB access explicitly before 1st PHY access Date: Wed, 26 Jun 2024 12:41:51 +0100 Message-ID: <230bf3e1548d419baae9ea8d9ab98fbec5fd089d.1719401848.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sergey Temerkhanov Explicitly enable sideband device access before the first PHY access to avoid possible errors for ETH56G. Signed-off-by: Sergey Temerkhanov Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 38 +++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 0eb14c1b41..06e9bec4eb 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2148,6 +2148,33 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass) return 0; } +/** + * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access + * @hw: pointer to HW struct + * @enable: Enable or disable access + * + * Enable sideband devices (PHY and others) access. + */ +static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) +{ + u32 regval; + + /* Enable reading and writing switch and PHY registers over the + * sideband queue. + */ +#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) +#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) + regval = rd32(hw, PF_SB_REM_DEV_CTL); + if (enable) + regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | + PF_SB_REM_DEV_CTL_PHY0); + else + regval &= ~(PF_SB_REM_DEV_CTL_SWITCH_READ | + PF_SB_REM_DEV_CTL_PHY0); + + wr32(hw, PF_SB_REM_DEV_CTL, regval); +} + /** * ice_ptp_init_phc_eth56g - Perform E822 specific PHC initialization * @hw: pointer to HW struct @@ -2157,15 +2184,6 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass) static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) { int err = 0; - u32 regval; - - /* Enable reading switch and PHY registers over the sideband queue */ -#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) -#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) - regval = rd32(hw, PF_SB_REM_DEV_CTL); - regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | - PF_SB_REM_DEV_CTL_PHY0); - wr32(hw, PF_SB_REM_DEV_CTL, regval); /* Initialize the Clock Generation Unit */ err = ice_init_cgu_e82x(hw); @@ -2206,6 +2224,8 @@ int ice_ptp_init_phy_model(struct ice_hw *hw) int err; u32 phy_rev; + ice_sb_access_ena_eth56g(hw, true); + err = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev, true); if (err) -- 2.43.0