From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80219A0C41; Thu, 16 Sep 2021 05:07:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66D204069E; Thu, 16 Sep 2021 05:07:52 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 70D974003C for ; Thu, 16 Sep 2021 05:07:51 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10108"; a="220592017" X-IronPort-AV: E=Sophos;i="5.85,297,1624345200"; d="scan'208";a="220592017" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 20:07:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,297,1624345200"; d="scan'208";a="698706623" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga006.fm.intel.com with ESMTP; 15 Sep 2021 20:07:50 -0700 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Wed, 15 Sep 2021 20:07:49 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX603.ccr.corp.intel.com (10.109.6.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Thu, 16 Sep 2021 11:07:47 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.012; Thu, 16 Sep 2021 11:07:47 +0800 From: "Tu, Lijuan" To: "Zhang, AlvinX" , "Zhang, Qi Z" , "Guo, Junfeng" CC: "dev@dpdk.org" , "Zhang, AlvinX" Thread-Topic: [dpdk-dev] [PATCH] net/ice: add ability to reduce the Rx latency Thread-Index: AQHXqQh6gCP7jSU2lUCrDJUfASHgwaul/RhA Date: Thu, 16 Sep 2021 03:07:47 +0000 Message-ID: <232754d5e7f846af8b884cd4404b8b4a@intel.com> References: <20210914013123.23768-1-alvinx.zhang@intel.com> In-Reply-To: <20210914013123.23768-1-alvinx.zhang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ice: add ability to reduce the Rx latency X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Alvin Zhang > Sent: 2021=1B$BG/=1B(B9=1B$B7n=1B(B14=1B$BF|=1B(B 9:31 > To: Zhang, Qi Z ; Guo, Junfeng > Cc: dev@dpdk.org; Zhang, AlvinX > Subject: [dpdk-dev] [PATCH] net/ice: add ability to reduce the Rx latency >=20 > This patch adds a devarg parameter to enable/disable reducing the Rx late= ncy. >=20 > Signed-off-by: Alvin Zhang > --- > doc/guides/nics/ice.rst | 8 ++++++++ > drivers/net/ice/ice_ethdev.c | 26 +++++++++++++++++++++++--- > drivers/net/ice/ice_ethdev.h | 1 + > 3 files changed, 32 insertions(+), 3 deletions(-) >=20 > diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst index > 5bc472f..3db0430 100644 > --- a/doc/guides/nics/ice.rst > +++ b/doc/guides/nics/ice.rst > @@ -219,6 +219,14 @@ Runtime Config Options >=20 > These ICE_DBG_XXX are defined in ``drivers/net/ice/base/ice_type.h``. >=20 > +- ``Reduce Rx interrupts and latency`` (default ``0``) > + > + vRAN workloads require low latency DPDK interface for the front haul > + interface connection to Radio. Now we can reduce Rx interrupts and > + latency by specify ``1`` for parameter ``rx-low-latency``:: > + > + -a 0000:88:00.0,rx-low-latency=3D1 > + > Driver compilation and testing > ------------------------------ >=20 > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c = index > a4cd39c..85662e4 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -29,12 +29,14 @@ > #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" > #define ICE_PROTO_XTR_ARG "proto_xtr" > #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" > +#define ICE_RX_LOW_LATENCY "rx-low-latency" >=20 > static const char * const ice_valid_args[] =3D { > ICE_SAFE_MODE_SUPPORT_ARG, > ICE_PIPELINE_MODE_SUPPORT_ARG, > ICE_PROTO_XTR_ARG, > ICE_HW_DEBUG_MASK_ARG, > + ICE_RX_LOW_LATENCY, > NULL > }; >=20 > @@ -1827,6 +1829,9 @@ static int ice_parse_devargs(struct rte_eth_dev *de= v) > if (ret) > goto bail; >=20 > + ret =3D rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY, > + &parse_bool, &ad->devargs.rx_low_latency); > + > bail: > rte_kvargs_free(kvlist); > return ret; > @@ -3144,8 +3149,9 @@ static int ice_init_rss(struct ice_pf *pf) { > struct ice_hw *hw =3D ICE_VSI_TO_HW(vsi); > uint32_t val, val_tx; > - int i; > + int rx_low_latency, i; >=20 > + rx_low_latency =3D vsi->adapter->devargs.rx_low_latency; > for (i =3D 0; i < nb_queue; i++) { > /*do actual bind*/ > val =3D (msix_vect & QINT_RQCTL_MSIX_INDX_M) | @@ -3155,8 > +3161,21 @@ static int ice_init_rss(struct ice_pf *pf) >=20 > PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", > base_queue + i, msix_vect); > + > /* set ITR0 value */ > - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); > + if (rx_low_latency) { > + /** > + * Empirical configuration for optimal real time > + * latency reduced interrupt throttling to 2us > + */ > + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1); > + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), > + QRX_ITR_NO_EXPR_M); > + } else { > + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); > + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0); > + } According to commit: 8b20510a042a, the previous value of 0x2 means 2us. > + > ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); > ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); > } > @@ -5314,7 +5333,8 @@ static int ice_xstats_get_names(__rte_unused struct > rte_eth_dev *dev, > ICE_HW_DEBUG_MASK_ARG "=3D0xXXX" > ICE_PROTO_XTR_ARG > "=3D[queue:]" > ICE_SAFE_MODE_SUPPORT_ARG "=3D<0|1>" > - ICE_PIPELINE_MODE_SUPPORT_ARG "=3D<0|1>"); > + ICE_PIPELINE_MODE_SUPPORT_ARG "=3D<0|1>" > + ICE_RX_LOW_LATENCY "=3D<0|1>"); >=20 > RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); > RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE); diff --git > a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index > b4bf651..c61cc1f 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -463,6 +463,7 @@ struct ice_pf { > * Cache devargs parse result. > */ > struct ice_devargs { > + int rx_low_latency; > int safe_mode_support; > uint8_t proto_xtr_dflt; > int pipe_mode_support; > -- > 1.8.3.1