From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE089A0352; Thu, 16 Jan 2020 15:47:19 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D9A811D588; Thu, 16 Jan 2020 15:47:18 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 88D5D1D54B for ; Thu, 16 Jan 2020 15:47:17 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jan 2020 06:47:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,326,1574150400"; d="scan'208";a="220392327" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.35]) ([10.237.221.35]) by fmsmga008.fm.intel.com with ESMTP; 16 Jan 2020 06:47:15 -0800 To: Chenxu Di , dev@dpdk.org Cc: Yang Qiming References: <20191203055134.72874-1-chenxux.di@intel.com> <20200113095708.67598-1-chenxux.di@intel.com> <20200113095708.67598-4-chenxux.di@intel.com> From: Ferruh Yigit Autocrypt: addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; keydata= mQINBFXZCFABEADCujshBOAaqPZpwShdkzkyGpJ15lmxiSr3jVMqOtQS/sB3FYLT0/d3+bvy qbL9YnlbPyRvZfnP3pXiKwkRoR1RJwEo2BOf6hxdzTmLRtGtwWzI9MwrUPj6n/ldiD58VAGQ +iR1I/z9UBUN/ZMksElA2D7Jgg7vZ78iKwNnd+vLBD6I61kVrZ45Vjo3r+pPOByUBXOUlxp9 GWEKKIrJ4eogqkVNSixN16VYK7xR+5OUkBYUO+sE6etSxCr7BahMPKxH+XPlZZjKrxciaWQb +dElz3Ab4Opl+ZT/bK2huX+W+NJBEBVzjTkhjSTjcyRdxvS1gwWRuXqAml/sh+KQjPV1PPHF YK5LcqLkle+OKTCa82OvUb7cr+ALxATIZXQkgmn+zFT8UzSS3aiBBohg3BtbTIWy51jNlYdy ezUZ4UxKSsFuUTPt+JjHQBvF7WKbmNGS3fCid5Iag4tWOfZoqiCNzxApkVugltxoc6rG2TyX CmI2rP0mQ0GOsGXA3+3c1MCdQFzdIn/5tLBZyKy4F54UFo35eOX8/g7OaE+xrgY/4bZjpxC1 1pd66AAtKb3aNXpHvIfkVV6NYloo52H+FUE5ZDPNCGD0/btFGPWmWRmkPybzColTy7fmPaGz cBcEEqHK4T0aY4UJmE7Ylvg255Kz7s6wGZe6IR3N0cKNv++O7QARAQABtCVGZXJydWggWWln aXQgPGZlcnJ1aC55aWdpdEBpbnRlbC5jb20+iQJUBBMBCgA+AhsDAh4BAheABQsJCAcDBRUK CQgLBRYCAwEAFiEE0jZTh0IuwoTjmYHH+TPrQ98TYR8FAl1meboFCQlupOoACgkQ+TPrQ98T YR9ACBAAv2tomhyxY0Tp9Up7mNGLfEdBu/7joB/vIdqMRv63ojkwr9orQq5V16V/25+JEAD0 60cKodBDM6HdUvqLHatS8fooWRueSXHKYwJ3vxyB2tWDyZrLzLI1jxEvunGodoIzUOtum0Ce gPynnfQCelXBja0BwLXJMplM6TY1wXX22ap0ZViC0m714U5U4LQpzjabtFtjT8qOUR6L7hfy YQ72PBuktGb00UR/N5UrR6GqB0x4W41aZBHXfUQnvWIMmmCrRUJX36hOTYBzh+x86ULgg7H2 1499tA4o6rvE13FiGccplBNWCAIroAe/G11rdoN5NBgYVXu++38gTa/MBmIt6zRi6ch15oLA Ln2vHOdqhrgDuxjhMpG2bpNE36DG/V9WWyWdIRlz3NYPCDM/S3anbHlhjStXHOz1uHOnerXM 1jEjcsvmj1vSyYoQMyRcRJmBZLrekvgZeh7nJzbPHxtth8M7AoqiZ/o/BpYU+0xZ+J5/szWZ aYxxmIRu5ejFf+Wn9s5eXNHmyqxBidpCWvcbKYDBnkw2+Y9E5YTpL0mS0dCCOlrO7gca27ux ybtbj84aaW1g0CfIlUnOtHgMCmz6zPXThb+A8H8j3O6qmPoVqT3qnq3Uhy6GOoH8Fdu2Vchh TWiF5yo+pvUagQP6LpslffufSnu+RKAagkj7/RSuZV25Ag0EV9ZMvgEQAKc0Db17xNqtSwEv mfp4tkddwW9XA0tWWKtY4KUdd/jijYqc3fDD54ESYpV8QWj0xK4YM0dLxnDU2IYxjEshSB1T qAatVWz9WtBYvzalsyTqMKP3w34FciuL7orXP4AibPtrHuIXWQOBECcVZTTOdZYGAzaYzxiA ONzF9eTiwIqe9/oaOjTwTLnOarHt16QApTYQSnxDUQljeNvKYt1lZE/gAUUxNLWsYyTT+22/ vU0GDUahsJxs1+f1yEr+OGrFiEAmqrzpF0lCS3f/3HVTU6rS9cK3glVUeaTF4+1SK5ZNO35p iVQCwphmxa+dwTG/DvvHYCtgOZorTJ+OHfvCnSVjsM4kcXGjJPy3JZmUtyL9UxEbYlrffGPQ I3gLXIGD5AN5XdAXFCjjaID/KR1c9RHd7Oaw0Pdcq9UtMLgM1vdX8RlDuMGPrj5sQrRVbgYH fVU/TQCk1C9KhzOwg4Ap2T3tE1umY/DqrXQgsgH71PXFucVjOyHMYXXugLT8YQ0gcBPHy9mZ qw5mgOI5lCl6d4uCcUT0l/OEtPG/rA1lxz8ctdFBVOQOxCvwRG2QCgcJ/UTn5vlivul+cThi 6ERPvjqjblLncQtRg8izj2qgmwQkvfj+h7Ex88bI8iWtu5+I3K3LmNz/UxHBSWEmUnkg4fJl Rr7oItHsZ0ia6wWQ8lQnABEBAAGJAjwEGAEKACYCGwwWIQTSNlOHQi7ChOOZgcf5M+tD3xNh HwUCXWZ5wAUJB3FgggAKCRD5M+tD3xNhH2O+D/9OEz62YuJQLuIuOfL67eFTIB5/1+0j8Tsu o2psca1PUQ61SZJZOMl6VwNxpdvEaolVdrpnSxUF31kPEvR0Igy8HysQ11pj8AcgH0a9FrvU /8k2Roccd2ZIdpNLkirGFZR7LtRw41Kt1Jg+lafI0efkiHKMT/6D/P1EUp1RxOBNtWGV2hrd 0Yg9ds+VMphHHU69fDH02SwgpvXwG8Qm14Zi5WQ66R4CtTkHuYtA63sS17vMl8fDuTCtvfPF HzvdJLIhDYN3Mm1oMjKLlq4PUdYh68Fiwm+boJoBUFGuregJFlO3hM7uHBDhSEnXQr5mqpPM 6R/7Q5BjAxrwVBisH0yQGjsWlnysRWNfExAE2sRePSl0or9q19ddkRYltl6X4FDUXy2DTXa9 a+Fw4e1EvmcF3PjmTYs9IE3Vc64CRQXkhujcN4ZZh5lvOpU8WgyDxFq7bavFnSS6kx7Tk29/ wNJBp+cf9qsQxLbqhW5kfORuZGecus0TLcmpZEFKKjTJBK9gELRBB/zoN3j41hlEl7uTUXTI JQFLhpsFlEdKLujyvT/aCwP3XWT+B2uZDKrMAElF6ltpTxI53JYi22WO7NH7MR16Fhi4R6vh FHNBOkiAhUpoXRZXaCR6+X4qwA8CwHGqHRBfYFSU/Ulq1ZLR+S3hNj2mbnSx0lBs1eEqe2vh cA== Message-ID: <23907f55-d456-69ae-9ee8-02751fda8a11@intel.com> Date: Thu, 16 Jan 2020 14:47:14 +0000 MIME-Version: 1.0 In-Reply-To: <20200113095708.67598-4-chenxux.di@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v9 3/4] net/ixgbe: cleanup Tx buffers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 1/13/2020 9:57 AM, Chenxu Di wrote: > Add support to the ixgbe driver for the API rte_eth_tx_done_cleanup > to force free consumed buffers on Tx ring. > > Signed-off-by: Chenxu Di > --- > drivers/net/ixgbe/ixgbe_ethdev.c | 2 + > drivers/net/ixgbe/ixgbe_rxtx.c | 109 +++++++++++++++++++++++++++++++ > drivers/net/ixgbe/ixgbe_rxtx.h | 2 +- > 3 files changed, 112 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c > index 2c6fd0f13..75bdd391a 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -601,6 +601,7 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = { > .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, > .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, > .tm_ops_get = ixgbe_tm_ops_get, > + .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, > }; > > /* > @@ -649,6 +650,7 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = { > .reta_query = ixgbe_dev_rss_reta_query, > .rss_hash_update = ixgbe_dev_rss_hash_update, > .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, > + .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, > }; > > /* store statistics names and its offset in stats structure */ > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c > index fa572d184..a2e85ed5b 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -2306,6 +2306,115 @@ ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq) > } > } > > +static int > +ixgbe_tx_done_cleanup_full(struct ixgbe_tx_queue *txq, uint32_t free_cnt) > +{ > + struct ixgbe_tx_entry *swr_ring = txq->sw_ring; > + uint16_t i, tx_last, tx_id; > + uint16_t nb_tx_free_last; > + uint16_t nb_tx_to_clean; > + uint32_t pkt_cnt; > + > + /* Start free mbuf from the next of tx_tail */ > + tx_last = txq->tx_tail; > + tx_id = swr_ring[tx_last].next_id; > + > + if (txq->nb_tx_free == 0 && ixgbe_xmit_cleanup(txq)) > + return 0; > + > + nb_tx_to_clean = txq->nb_tx_free; > + nb_tx_free_last = txq->nb_tx_free; > + if (!free_cnt) > + free_cnt = txq->nb_tx_desc; > + > + /* Loop through swr_ring to count the amount of > + * freeable mubfs and packets. > + */ > + for (pkt_cnt = 0; pkt_cnt < free_cnt; ) { > + for (i = 0; i < nb_tx_to_clean && > + pkt_cnt < free_cnt && > + tx_id != tx_last; i++) { > + if (swr_ring[tx_id].mbuf != NULL) { > + rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf); > + swr_ring[tx_id].mbuf = NULL; > + > + /* > + * last segment in the packet, > + * increment packet count > + */ > + pkt_cnt += (swr_ring[tx_id].last_id == tx_id); > + } > + > + tx_id = swr_ring[tx_id].next_id; > + } > + > + if (txq->tx_rs_thresh > txq->nb_tx_desc - > + txq->nb_tx_free || tx_id == tx_last) > + break; > + > + if (pkt_cnt < free_cnt) { > + if (ixgbe_xmit_cleanup(txq)) > + break; > + > + nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last; > + nb_tx_free_last = txq->nb_tx_free; > + } > + } > + > + return (int)pkt_cnt; > +} > + > +static int > +ixgbe_tx_done_cleanup_simple(struct ixgbe_tx_queue *txq, > + uint32_t free_cnt) > +{ > + int i, n, cnt; > + > + if (free_cnt == 0 || free_cnt > txq->nb_tx_desc) > + free_cnt = txq->nb_tx_desc; > + > + cnt = free_cnt - free_cnt % txq->tx_rs_thresh; > + > + for (i = 0; i < cnt; i += n) { > + if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh) > + break; > + > + n = ixgbe_tx_free_bufs(txq); > + > + if (n == 0) > + break; > + } > + > + return i; > +} > + > +static int > +ixgbe_tx_done_cleanup_vec(struct ixgbe_tx_queue *txq __rte_unused, > + uint32_t free_cnt __rte_unused) > +{ > + return -ENOTSUP; > +} > + > +int > +ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) > +{ > + struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue; > + if (txq->offloads == 0 && > +#ifdef RTE_LIBRTE_SECURITY > + !(txq->using_ipsec) && > +#endif > + txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) > +#ifdef RTE_IXGBE_INC_VECTOR > + if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > + (rte_eal_process_type() != RTE_PROC_PRIMARY || > + txq->sw_ring_v != NULL)) > + return ixgbe_tx_done_cleanup_vec(txq, free_cnt); > +#endif > + return ixgbe_tx_done_cleanup_simple(txq, free_cnt); > + > + return ixgbe_tx_done_cleanup_full(txq, free_cnt); > +} > + Missing curly parantheses in the 'if' blocks are causing confusion on which return patch to take. the above code is like this: if (txq->offloads == 0 && ...) if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && ...) return ixgbe_tx_done_cleanup_vec(txq, free_cnt); return ixgbe_tx_done_cleanup_simple(txq, free_cnt); <----- [*] return ixgbe_tx_done_cleanup_full(txq, free_cnt); It is not clear, and looks like wrong based on indentation, when to get the [*] path above. I will add curly parantheses while merging. Btw, why we need "#ifdef RTE_IXGBE_INC_VECTOR" here, can't we remove it?