From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 06C495323; Thu, 20 Dec 2018 00:35:00 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Dec 2018 15:35:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,374,1539673200"; d="scan'208";a="119809720" Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by FMSMGA003.fm.intel.com with ESMTP; 19 Dec 2018 15:34:57 -0800 Received: from irsmsx106.ger.corp.intel.com ([169.254.8.227]) by IRSMSX107.ger.corp.intel.com ([169.254.10.125]) with mapi id 14.03.0415.000; Wed, 19 Dec 2018 23:34:57 +0000 From: "Ananyev, Konstantin" To: Joyce Kong , "dev@dpdk.org" CC: "nd@arm.com" , "thomas@monjalon.net" , "jerin.jacob@caviumnetworks.com" , "hemant.agrawal@nxp.com" , "honnappa.nagarahalli@arm.com" , "gavin.hu@arm.com" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v1 1/2] test/rwlock: add perf test case Thread-Index: AQHUkpVMzxjOrBt7VkGHDmrhlDZSpqWGwLyQ Date: Wed, 19 Dec 2018 23:34:56 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258010D8BCD43@IRSMSX106.ger.corp.intel.com> References: <1544672265-219262-1-git-send-email-joyce.kong@arm.com> <1544672265-219262-2-git-send-email-joyce.kong@arm.com> In-Reply-To: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNWNlODk2YzUtZDY1MC00ZDdmLTkyYjUtZmMzYzAxZTZkMDgxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiTkF0aldQRXZQYzJvUEI3eWRSeDVuVksrcFlKdGM5U0txNEZ4K0R6bUZrMU1ucmZKaFcxenNsMmVxeTVGcUdRViJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1 1/2] test/rwlock: add perf test case X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 23:35:01 -0000 Hi, >=20 > Add performance test on all available cores to benchmark > the scaling up performance and fairness of rw_lock. >=20 > Fixes: af75078faf ("first public release") > Cc: stable@dpdk.org >=20 > Suggested-by: Gavin Hu > Signed-off-by: Joyce Kong > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Ola Liljedahl > Reviewed-by: Gavin Hu > Reviewed-by: Ruifeng Wang > --- > test/test/test_rwlock.c | 71 +++++++++++++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 71 insertions(+) >=20 > diff --git a/test/test/test_rwlock.c b/test/test/test_rwlock.c > index 29171c4..4766c09 100644 > --- a/test/test/test_rwlock.c > +++ b/test/test/test_rwlock.c > @@ -4,6 +4,7 @@ >=20 > #include > #include > +#include > #include > #include >=20 > @@ -44,6 +45,7 @@ >=20 > static rte_rwlock_t sl; > static rte_rwlock_t sl_tab[RTE_MAX_LCORE]; > +static rte_atomic32_t synchro; >=20 > static int > test_rwlock_per_core(__attribute__((unused)) void *arg) > @@ -65,6 +67,72 @@ test_rwlock_per_core(__attribute__((unused)) void *arg= ) > return 0; > } >=20 > +static rte_rwlock_t lk =3D RTE_RWLOCK_INITIALIZER; > +static uint64_t lock_count[RTE_MAX_LCORE] =3D {0}; > + > +#define TIME_MS 100 > + > +static int > +load_loop_fn(__attribute__((unused)) void *arg) > +{ > + uint64_t time_diff =3D 0, begin; > + uint64_t hz =3D rte_get_timer_hz(); > + uint64_t lcount =3D 0; > + const unsigned int lcore =3D rte_lcore_id(); > + > + /* wait synchro for slaves */ > + if (lcore !=3D rte_get_master_lcore()) > + while (rte_atomic32_read(&synchro) =3D=3D 0) > + ; > + > + begin =3D rte_rdtsc_precise(); > + while (time_diff < hz * TIME_MS / 1000) { > + rte_rwlock_write_lock(&lk); > + rte_pause(); Wouldn't it be more realistic to write/read some shared data here? Again extra checking could be done in that case that lock behaves as expect= ed. > + rte_rwlock_write_unlock(&lk); > + rte_rwlock_read_lock(&lk); > + rte_rwlock_read_lock(&lk); Wonder what is the point of double rdlock here? Konstantin > + rte_pause(); > + rte_rwlock_read_unlock(&lk); > + rte_rwlock_read_unlock(&lk); > + lcount++; > + /* delay to make lock duty cycle slightly realistic */ > + rte_pause(); > + time_diff =3D rte_rdtsc_precise() - begin; > + } > + lock_count[lcore] =3D lcount; > + return 0; > +} > +