From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id E0D955320 for ; Fri, 24 Jan 2014 13:48:58 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 24 Jan 2014 04:50:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,712,1384329600"; d="scan'208";a="464108141" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by fmsmga001.fm.intel.com with ESMTP; 24 Jan 2014 04:50:11 -0800 Received: from irsmsx153.ger.corp.intel.com (163.33.192.75) by IRSMSX101.ger.corp.intel.com (163.33.3.153) with Microsoft SMTP Server (TLS) id 14.3.123.3; Fri, 24 Jan 2014 12:48:59 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.215]) by IRSMSX153.ger.corp.intel.com ([169.254.9.156]) with mapi id 14.03.0123.003; Fri, 24 Jan 2014 12:48:59 +0000 From: "Ananyev, Konstantin" To: =?iso-8859-1?Q?Fran=E7ois-Fr=E9d=E9ric_Ozog?= , "'Didier Pallard'" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] timer: add lfence before TSC read Thread-Index: AQHPGPYE9lI9bVhiVky6eOgpuN7ZqpqTwOGAgAAPzHA= Date: Fri, 24 Jan 2014 12:48:59 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725808E5A20B@IRSMSX105.ger.corp.intel.com> References: <1390562277-24769-1-git-send-email-didier.pallard@6wind.com> <00d201cf18f9$67cdaf10$37690d30$@com> In-Reply-To: <00d201cf18f9$67cdaf10$37690d30$@com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH] timer: add lfence before TSC read X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Jan 2014 12:48:59 -0000 Hi, Totally agree with Fran=E7ois-Fr=E9d=E9ric. Actually was going to suggest exactly the same thing. BTW, there is rte_rmb() defined inside rte_atomic.h, that should produce an= lfence instruction. Probably better to use it to keep code consistent. Konstantin = -----Original Message----- From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Fran=E7ois-Fr=E9d=E9ri= c Ozog Sent: Friday, January 24, 2014 11:43 AM To: 'Didier Pallard'; dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH] timer: add lfence before TSC read Hi, Most of the time rdtsc is used for timestamping and a few cycles incorrect = are most of the time not an issue (a precision of 0.1us for session start i= s usually enough). Sometimes you need to serialize because the time you want to measure is ver= y short, in the order of few nanoseconds. If the code is running in a VM, which usually virtualize rdtsc instruction,= then it even make no sense to have more "precision". IMHO, adding the lfence for all cases is introducing an un-necessary perfor= mance penalty. What about adding rte_rdtsc_sync() or rte_rdtsc_serial() with the comment a= bout the rdtsc instruction behavior so that developers can choose which for= m they want? Fran=E7ois-Fr=E9d=E9ric > -----Message d'origine----- > De=A0: dev [mailto:dev-bounces@dpdk.org] De la part de Didier Pallard = > Envoy=E9=A0: vendredi 24 janvier 2014 12:18 =C0=A0: dev@dpdk.org Objet=A0= : = > [dpdk-dev] [PATCH] timer: add lfence before TSC read > = > According to Intel Developer's Manual: > = > "The RDTSC instruction is not a serializing instruction. It does not = > necessarily wait until all previous instructions have been executed before > reading the counter. Simi- larly, subsequent instructions may begin = > execution before the read operation is performed. If software = > requires RDTSC to be executed only after all previous instruc- tions = > have completed > locally, it can either use RDTSCP (if the processor supports that > instruction) or execute the sequence LFENCE;RDTSC." > = > So add a lfence instruction before rdtsc to synchronize read = > operations and > ensure that the read is done at the expected instant. > = > Signed-off-by: Didier Pallard > --- > lib/librte_eal/common/include/rte_cycles.h | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/lib/librte_eal/common/include/rte_cycles.h > b/lib/librte_eal/common/include/rte_cycles.h > index cc6fe71..487dba6 100644 > --- a/lib/librte_eal/common/include/rte_cycles.h > +++ b/lib/librte_eal/common/include/rte_cycles.h > @@ -110,6 +110,9 @@ rte_rdtsc(void) > }; > } tsc; > = > + /* serialize previous load instructions in pipe */ > + asm volatile("lfence"); > + > #ifdef RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT > if (unlikely(rte_cycles_vmware_tsc_map)) { > /* ecx =3D 0x10000 corresponds to the physical TSC for VMware */ > -- > 1.7.10.4 -------------------------------------------------------------- Intel Shannon Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 Business address: Dromore House, East Park, Shannon, Co. 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