From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 2C73AC73E for ; Tue, 23 Jun 2015 02:31:09 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 22 Jun 2015 17:31:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,662,1427785200"; d="scan'208";a="592871969" Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by orsmga003.jf.intel.com with ESMTP; 22 Jun 2015 17:31:07 -0700 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.245]) by IRSMSX107.ger.corp.intel.com ([169.254.10.39]) with mapi id 14.03.0224.002; Tue, 23 Jun 2015 01:31:06 +0100 From: "Ananyev, Konstantin" To: Cyril Chemparathy , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 08/12] mempool: allow config override on element alignment Thread-Index: AQHQrR2o1p8rQVbhjkq9F3BSU4GI1p25ODMg Date: Tue, 23 Jun 2015 00:31:06 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836A1CDB8@irsmsx105.ger.corp.intel.com> References: <1434999524-26528-1-git-send-email-cchemparathy@ezchip.com> <1434999524-26528-9-git-send-email-cchemparathy@ezchip.com> In-Reply-To: <1434999524-26528-9-git-send-email-cchemparathy@ezchip.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 08/12] mempool: allow config override on element alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Jun 2015 00:31:10 -0000 Hi Cyril, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Cyril Chemparathy > Sent: Monday, June 22, 2015 7:59 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 08/12] mempool: allow config override on el= ement alignment >=20 > On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware > buffer manager require a 128-byte alignment. With this change, we > allow configuration based override of the element alignment, and > default to RTE_CACHE_LINE_SIZE if left unspecified. >=20 > Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7 > Signed-off-by: Cyril Chemparathy > --- > lib/librte_mempool/rte_mempool.c | 16 +++++++++------- > lib/librte_mempool/rte_mempool.h | 6 ++++++ > 2 files changed, 15 insertions(+), 7 deletions(-) >=20 > diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_me= mpool.c > index 002d3a8..7656b0f 100644 > --- a/lib/librte_mempool/rte_mempool.c > +++ b/lib/librte_mempool/rte_mempool.c > @@ -120,10 +120,10 @@ static unsigned optimize_object_size(unsigned obj_s= ize) > nrank =3D 1; >=20 > /* process new object size */ > - new_obj_size =3D (obj_size + RTE_CACHE_LINE_MASK) / RTE_CACHE_LINE_SIZE= ; > + new_obj_size =3D (obj_size + RTE_MEMPOOL_ALIGN_MASK) / RTE_MEMPOOL_ALIG= N; > while (get_gcd(new_obj_size, nrank * nchan) !=3D 1) > new_obj_size++; > - return new_obj_size * RTE_CACHE_LINE_SIZE; > + return new_obj_size * RTE_MEMPOOL_ALIGN; > } >=20 > static void > @@ -267,7 +267,7 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t= flags, > #endif > if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) =3D=3D 0) > sz->header_size =3D RTE_ALIGN_CEIL(sz->header_size, > - RTE_CACHE_LINE_SIZE); > + RTE_MEMPOOL_ALIGN); >=20 > /* trailer contains the cookie in debug mode */ > sz->trailer_size =3D 0; > @@ -281,9 +281,9 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t= flags, > if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) =3D=3D 0) { > sz->total_size =3D sz->header_size + sz->elt_size + > sz->trailer_size; > - sz->trailer_size +=3D ((RTE_CACHE_LINE_SIZE - > - (sz->total_size & RTE_CACHE_LINE_MASK)) & > - RTE_CACHE_LINE_MASK); > + sz->trailer_size +=3D ((RTE_MEMPOOL_ALIGN - > + (sz->total_size & RTE_MEMPOOL_ALIGN_MASK)) & > + RTE_MEMPOOL_ALIGN_MASK); > } >=20 > /* > @@ -498,7 +498,7 @@ rte_mempool_xmem_create(const char *name, unsigned n,= unsigned elt_size, > * cache-aligned > */ > private_data_size =3D (private_data_size + > - RTE_CACHE_LINE_MASK) & (~RTE_CACHE_LINE_MASK); > + RTE_MEMPOOL_ALIGN_MASK) & (~RTE_MEMPOOL_ALIGN_MASK); >=20 > if (! rte_eal_has_hugepages()) { > /* > @@ -525,6 +525,7 @@ rte_mempool_xmem_create(const char *name, unsigned n,= unsigned elt_size, > * enough to hold mempool header and metadata plus mempool objects. > */ > mempool_size =3D MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size; > + mempool_size =3D RTE_ALIGN_CEIL(mempool_size, RTE_MEMPOOL_ALIGN); > if (vaddr =3D=3D NULL) > mempool_size +=3D (size_t)objsz.total_size * n; >=20 > @@ -580,6 +581,7 @@ rte_mempool_xmem_create(const char *name, unsigned n,= unsigned elt_size, > /* calculate address of the first element for continuous mempool. */ > obj =3D (char *)mp + MEMPOOL_HEADER_SIZE(mp, pg_num) + > private_data_size; > + obj =3D RTE_PTR_ALIGN_CEIL(obj, RTE_MEMPOOL_ALIGN); >=20 > /* populate address translation fields. */ > mp->pg_num =3D pg_num; > diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_me= mpool.h > index 380d60b..9321b86 100644 > --- a/lib/librte_mempool/rte_mempool.h > +++ b/lib/librte_mempool/rte_mempool.h > @@ -142,6 +142,12 @@ struct rte_mempool_objsz { > /** Mempool over one chunk of physically continuous memory */ > #define MEMPOOL_PG_NUM_DEFAULT 1 >=20 > +#ifndef RTE_MEMPOOL_ALIGN > +#define RTE_MEMPOOL_ALIGN RTE_CACHE_LINE_SIZE > +#endif > + > +#define RTE_MEMPOOL_ALIGN_MASK (RTE_MEMPOOL_ALIGN - 1) I am probably a bit late with my comments, but why not make it a runtime de= cision then? I know we can't add a new parameter to mempool_xmem_create() without ABI br= eakage, but we can make some global variable for now, that could be setup at init t= ime or something similar.=20 > + > /** > * Mempool object header structure > * > -- > 2.1.2