From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 7131A91AB for ; Fri, 16 Oct 2015 00:57:54 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 15 Oct 2015 15:57:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,687,1437462000"; d="scan'208";a="828063521" Received: from irsmsx103.ger.corp.intel.com ([163.33.3.157]) by fmsmga002.fm.intel.com with ESMTP; 15 Oct 2015 15:57:52 -0700 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.75]) by IRSMSX103.ger.corp.intel.com ([169.254.3.116]) with mapi id 14.03.0248.002; Thu, 15 Oct 2015 23:57:51 +0100 From: "Ananyev, Konstantin" To: "Lu, Wenzhuo" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update Thread-Index: AQHQ+cLiCJgwDYogqUuGVyKf1BPYmp5tRcvA Date: Thu, 15 Oct 2015 22:57:51 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AB0358@irsmsx105.ger.corp.intel.com> References: <1443426751-4906-1-git-send-email-wenzhuo.lu@intel.com> <1443426751-4906-5-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1443426751-4906-5-git-send-email-wenzhuo.lu@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Oct 2015 22:57:55 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu > Sent: Monday, September 28, 2015 8:53 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update >=20 > This patch implements the VF RSS redirection table query and update funct= ion > on 10G NICs. But the update function is only provided for x550. Because t= he > other NICs don't have the separate registers for VF, we don't want to let= a > VF NIC change the shared RSS reta registers. It may cause PF and other VF= NICs' > behavior change without being noticed. >=20 > Signed-off-by: Wenzhuo Lu > --- > drivers/net/ixgbe/ixgbe_ethdev.c | 103 +++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 103 insertions(+) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_e= thdev.c > index 5e50ee6..44baadf 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -326,6 +326,13 @@ static int ixgbe_timesync_read_rx_timestamp(struct r= te_eth_dev *dev, > static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, > struct timespec *timestamp); >=20 > +static int ixgbevf_dev_rss_reta_update(struct rte_eth_dev *dev, > + struct rte_eth_rss_reta_entry64 *reta_conf, > + uint16_t reta_size); > +static int ixgbevf_dev_rss_reta_query(struct rte_eth_dev *dev, > + struct rte_eth_rss_reta_entry64 *reta_conf, > + uint16_t reta_size); > + > /* > * Define VF Stats MACRO for Non "cleared on read" register > */ > @@ -497,6 +504,8 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = =3D { > .mac_addr_set =3D ixgbevf_set_default_mac_addr, > .get_reg_length =3D ixgbevf_get_reg_length, > .get_reg =3D ixgbevf_get_regs, > + .reta_update =3D ixgbevf_dev_rss_reta_update, > + .reta_query =3D ixgbevf_dev_rss_reta_query, > .rss_hash_update =3D ixgbevf_dev_rss_hash_update, > .rss_hash_conf_get =3D ixgbevf_dev_rss_hash_conf_get, > }; > @@ -5557,6 +5566,100 @@ ixgbe_set_eeprom(struct rte_eth_dev *dev, > return eeprom->ops.write_buffer(hw, first, length, data); > } >=20 > +static int > +ixgbevf_dev_rss_reta_update(struct rte_eth_dev *dev, > + struct rte_eth_rss_reta_entry64 *reta_conf, > + uint16_t reta_size) > +{ > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private)= ; > + uint32_t reta, r; > + uint16_t i, j; > + uint16_t idx, shift; > + uint8_t mask; > + > + if (hw->mac.type !=3D ixgbe_mac_X550_vf && > + hw->mac.type !=3D ixgbe_mac_X550EM_x_vf) { > + PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " > + "VF NIC."); > + return -ENOTSUP; > + } > + > + if (reta_size !=3D ETH_RSS_RETA_SIZE_64) { > + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " > + "(%d) doesn't match the number of hardware can " > + "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64); > + return -EINVAL; > + } > + > + for (i =3D 0; i < reta_size; i +=3D IXGBE_4_BIT_WIDTH) { > + idx =3D i / RTE_RETA_GROUP_SIZE; > + shift =3D i % RTE_RETA_GROUP_SIZE; > + mask =3D (uint8_t)((reta_conf[idx].mask >> shift) & > + IXGBE_4_BIT_WIDTH); > + if (!mask) > + continue; > + if (mask =3D=3D IXGBE_4_BIT_WIDTH) > + r =3D 0; > + else > + r =3D IXGBE_READ_REG(hw, IXGBE_VFRETA(i >> 2)); > + > + for (j =3D 0, reta =3D 0; j < IXGBE_4_BIT_WIDTH; j++) { > + if (mask & (0x1 << j)) > + reta |=3D reta_conf[idx].reta[shift + j] << > + (CHAR_BIT * j); > + else > + reta |=3D r & > + (IXGBE_8_BIT_MASK << (CHAR_BIT * j)); > + } > + IXGBE_WRITE_REG(hw, IXGBE_VFRETA(i >> 2), reta); > + } > + > + return 0; > +} > + > +static int > +ixgbevf_dev_rss_reta_query(struct rte_eth_dev *dev, > + struct rte_eth_rss_reta_entry64 *reta_conf, > + uint16_t reta_size) > +{ > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private)= ; > + uint32_t reta; > + uint16_t i, j; > + uint16_t idx, shift; > + uint8_t mask; > + > + if (hw->mac.type !=3D ixgbe_mac_X550_vf && > + hw->mac.type !=3D ixgbe_mac_X550EM_x_vf) { > + return ixgbe_dev_rss_reta_query(dev, reta_conf, reta_size); > + } > + > + if (reta_size !=3D ETH_RSS_RETA_SIZE_64) { > + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " > + "(%d) doesn't match the number of hardware can " > + "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64); > + return -EINVAL; > + } > + > + for (i =3D 0; i < reta_size; i +=3D IXGBE_4_BIT_WIDTH) { > + idx =3D i / RTE_RETA_GROUP_SIZE; > + shift =3D i % RTE_RETA_GROUP_SIZE; > + mask =3D (uint8_t)((reta_conf[idx].mask >> shift) & > + IXGBE_4_BIT_MASK); > + if (!mask) > + continue; > + > + reta =3D IXGBE_READ_REG(hw, IXGBE_VFRETA(i >> 2)); > + for (j =3D 0; j < IXGBE_4_BIT_WIDTH; j++) { > + if (mask & (0x1 << j)) > + reta_conf[idx].reta[shift + j] =3D > + ((reta >> (CHAR_BIT * j)) & > + IXGBE_8_BIT_MASK); > + } > + } > + > + return 0; > +} > + Same as for other 3 patches in that series: >90% of the code is just copy &= paste of existing one, with different HW registers name and reta_size. Pls unify. Konstantin > static struct rte_driver rte_ixgbe_driver =3D { > .type =3D PMD_PDEV, > .init =3D rte_ixgbe_pmd_init, > -- > 1.9.3