From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 94D268E72 for ; Fri, 11 Dec 2015 13:56:04 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 11 Dec 2015 04:56:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,413,1444719600"; d="scan'208";a="871608721" Received: from irsmsx105.ger.corp.intel.com ([163.33.3.28]) by fmsmga002.fm.intel.com with ESMTP; 11 Dec 2015 04:56:01 -0800 Received: from irsmsx111.ger.corp.intel.com (10.108.20.4) by irsmsx105.ger.corp.intel.com (163.33.3.28) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 11 Dec 2015 12:55:58 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.203]) by irsmsx111.ger.corp.intel.com ([169.254.2.223]) with mapi id 14.03.0248.002; Fri, 11 Dec 2015 12:55:58 +0000 From: "Ananyev, Konstantin" To: Jerin Jacob , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 4/4] cache/slow-path: reduce cache align requirement for 128-byte cache targets Thread-Index: AQHRM2kbny3RKqmdSEuc+vidWbqPKZ7Ft4gw Date: Fri, 11 Dec 2015 12:55:57 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AD2A79@irsmsx105.ger.corp.intel.com> References: <1449417564-29600-1-git-send-email-jerin.jacob@caviumnetworks.com> <1449765378-29563-1-git-send-email-jerin.jacob@caviumnetworks.com> <1449765378-29563-5-git-send-email-jerin.jacob@caviumnetworks.com> In-Reply-To: <1449765378-29563-5-git-send-email-jerin.jacob@caviumnetworks.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 4/4] cache/slow-path: reduce cache align requirement for 128-byte cache targets X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Dec 2015 12:56:05 -0000 Hi Jerin, > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Thursday, December 10, 2015 4:36 PM > To: dev@dpdk.org > Cc: thomas.monjalon@6wind.com; Ananyev, Konstantin; viktorin@rehivetech.c= om; jianbo.liu@linaro.org; Jerin Jacob > Subject: [dpdk-dev] [PATCH v2 4/4] cache/slow-path: reduce cache align re= quirement for 128-byte cache targets >=20 > slow-path data structures need not be 128-byte cache aligned. > Reduce the alignment to 64-byte to save the memory. >=20 > No behavior change for 64-byte cache aligned systems as minimum > cache line size as 64. >=20 > Signed-off-by: Jerin Jacob > --- > lib/librte_ether/rte_ethdev.h | 4 ++-- > lib/librte_mempool/rte_mempool.h | 2 +- > lib/librte_ring/rte_ring.h | 2 +- > 3 files changed, 4 insertions(+), 4 deletions(-) >=20 > diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.= h > index bada8ad..4dbf73b 100644 > --- a/lib/librte_ether/rte_ethdev.h > +++ b/lib/librte_ether/rte_ethdev.h > @@ -863,7 +863,7 @@ struct rte_eth_rxq_info { > struct rte_eth_rxconf conf; /**< queue config parameters. */ > uint8_t scattered_rx; /**< scattered packets RX supported. */ > uint16_t nb_desc; /**< configured number of RXDs. */ > -} __rte_cache_aligned; > +} __rte_cache_min_aligned; >=20 > /** > * Ethernet device TX queue information structure. > @@ -872,7 +872,7 @@ struct rte_eth_rxq_info { > struct rte_eth_txq_info { > struct rte_eth_txconf conf; /**< queue config parameters. */ > uint16_t nb_desc; /**< configured number of TXDs. */ > -} __rte_cache_aligned; > +} __rte_cache_min_aligned; >=20 > /** Maximum name length for extended statistics counters */ > #define RTE_ETH_XSTATS_NAME_SIZE 64 > diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_me= mpool.h > index 6e2390a..8e5d10c 100644 > --- a/lib/librte_mempool/rte_mempool.h > +++ b/lib/librte_mempool/rte_mempool.h > @@ -92,7 +92,7 @@ struct rte_mempool_debug_stats { > uint64_t get_success_objs; /**< Objects successfully allocated. */ > uint64_t get_fail_bulk; /**< Failed allocation number. */ > uint64_t get_fail_objs; /**< Objects that failed to be allocated. */ > -} __rte_cache_aligned; > +} __rte_cache_min_aligned; > #endif >=20 > #if RTE_MEMPOOL_CACHE_MAX_SIZE > 0 > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > index de036ce..33166aa 100644 > --- a/lib/librte_ring/rte_ring.h > +++ b/lib/librte_ring/rte_ring.h > @@ -123,7 +123,7 @@ struct rte_ring_debug_stats { > uint64_t deq_success_objs; /**< Objects successfully dequeued. */ > uint64_t deq_fail_bulk; /**< Failed dequeues number. */ > uint64_t deq_fail_objs; /**< Objects that failed to be dequeued. */ > -} __rte_cache_aligned; > +} __rte_cache_min_aligned; > #endif I think we better keep both struct rte_ring_debug_stats and rte_mempool_deb= ug_stats as __rte_cache_aligned. Both are on a per core basis and can be used at run-time (when RTE_LIBRTE_RING_DEBUG/RTE_LIBRTE_MEMPOOL_DEBUG=3Dy), and not supposed to be shared by different cores.=20 All other things in the series look good to me. BTW, by some reason I can't find that series in the patchworks. Konstantin >=20 > #define RTE_RING_NAMESIZE 32 /**< The maximum length of a ring name. */ > -- > 2.1.0