From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 952C78DAF for ; Wed, 20 Jan 2016 12:25:56 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 20 Jan 2016 03:25:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,320,1449561600"; d="scan'208";a="894547774" Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by orsmga002.jf.intel.com with ESMTP; 20 Jan 2016 03:25:54 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.237]) by IRSMSX107.ger.corp.intel.com ([169.254.10.55]) with mapi id 14.03.0248.002; Wed, 20 Jan 2016 11:25:53 +0000 From: "Ananyev, Konstantin" To: "Andralojc, WojciechX" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)... Thread-Index: AQHRU3HybIYguzqDGE2zHDM9XpiZ358EPu2A Date: Wed, 20 Jan 2016 11:25:52 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AEC360@irsmsx105.ger.corp.intel.com> References: <1450354363-102022-1-git-send-email-wojciechx.andralojc@intel.com> <1453287399-65915-1-git-send-email-wojciechx.andralojc@intel.com> In-Reply-To: <1453287399-65915-1-git-send-email-wojciechx.andralojc@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiM2UwZjAzZTUtZDZlMi00Njg5LWE3NTQtMDJiNjgwY2VkN2MzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjQuMTAuMTkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMFdxeHNuUnExTmp2SmhmQnMzVnBCb0dMcTduaW9JaU9XaUlZV1ZtenN3dz0ifQ== x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)... X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2016 11:25:57 -0000 Hi Wojciech, Couple of nits, see below. Konstantin > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wojciech Andralojc > Sent: Wednesday, January 20, 2016 10:57 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2] Patch introducing API to read/write Intel = Architecture Model Specific Registers (MSR)... >=20 > Patch rework based on feedback, only x86 specific functions left under li= b/librte_eal/common/include/arch/x86/. >=20 > Signed-off-by: Wojciech Andralojc > --- > lib/librte_eal/common/include/arch/x86/rte_msr.h | 158 +++++++++++++++++= ++++++ > 1 file changed, 158 insertions(+) > create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h >=20 > diff --git a/lib/librte_eal/common/include/arch/x86/rte_msr.h b/lib/librt= e_eal/common/include/arch/x86/rte_msr.h > new file mode 100644 > index 0000000..9d16633 > --- /dev/null > +++ b/lib/librte_eal/common/include/arch/x86/rte_msr.h > + > +#ifndef _RTE_MSR_X86_64_H_ > +#define _RTE_MSR_X86_64_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include //O_RDONLY > +#include //pread Pls remove '//' comments here. > + > +#include > +#include > + > +#define CPU_MSR_PATH "/dev/cpu/%u/msr" > +#define CPU_MSR_PATH_MAX_LEN 32 > + > +/** > + * This function should not be called directly. > + * Function to open CPU's MSR file > + */ > +static int > +__msr_open_file(const unsigned lcore, int flags) > +{ > + char fname[CPU_MSR_PATH_MAX_LEN] =3D {0}; Why not just use PATH_MAX here? > + int fd =3D -1; > + > + snprintf(fname, sizeof(fname) - 1, CPU_MSR_PATH, lcore); > + > + fd =3D open(fname, flags); > + > + if (fd < 0) > + RTE_LOG(ERR, PQOS, "Error opening file '%s'!\n", fname); > + > + return fd; > +} > + > +/** > + * Function to read CPU's MSR > + * > + * @param [in] lcore > + * CPU logical core id Hmm, are you aware that DPDK lcore id !=3D CPU lcore id? Might be better to use 'cpuid' name here? Just to avoid confusion. > + * > + * @param [in] reg > + * MSR reg to read > + * > + * @param [out] value > + * Read value of MSR reg > + * > + * @return > + * Operations status > +*/ > + > +static inline int > +rte_msr_read(const unsigned lcore, const uint32_t reg, uint64_t *value) I don't think there is a need to put rte_msr_read/rte_msr_write()=20 Definition into a header file and make them static inline. Just normal external function definition seems sufficient here. > +{ > + int fd =3D -1; > + int ret =3D -1; > + > + RTE_VERIFY(value !=3D NULL); That's a a public API. No need to coredump if one of the input parameters is invalid. > + if (value =3D=3D NULL) > + return -1; Might be better -EINVAL; > + > + fd =3D __msr_open_file(lcore, O_RDONLY); > + > + if (fd >=3D 0) { > + ssize_t read_ret =3D 0; > + > + read_ret =3D pread(fd, value, sizeof(value[0]), (off_t)reg); > + > + if (read_ret !=3D sizeof(value[0])) { > + RTE_LOG(ERR, PQOS, "RDMSR failed for reg[0x%x] on lcore %u\n", > + (unsigned)reg, lcore); > + } else > + ret =3D 0; > + > + close(fd); > + } > + > + return ret; > +}