From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 662D9374F for ; Mon, 19 Sep 2016 14:55:00 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 19 Sep 2016 05:55:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,361,1470726000"; d="scan'208";a="1058908640" Received: from irsmsx151.ger.corp.intel.com ([163.33.192.59]) by fmsmga002.fm.intel.com with ESMTP; 19 Sep 2016 05:54:58 -0700 Received: from irsmsx111.ger.corp.intel.com (10.108.20.4) by IRSMSX151.ger.corp.intel.com (163.33.192.59) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 19 Sep 2016 13:54:57 +0100 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.196]) by irsmsx111.ger.corp.intel.com ([169.254.2.67]) with mapi id 14.03.0248.002; Mon, 19 Sep 2016 13:54:57 +0100 From: "Ananyev, Konstantin" To: "Kulasek, TomaszX" , "dev@dpdk.org" CC: "jerin.jacob@caviumnetworks.com" Thread-Topic: [dpdk-dev] [PATCH v2 5/6] ixgbe: add Tx preparation Thread-Index: AQHSDQU3U1SWwi8SuEaT8zAVcgeiOaCAy3FA Date: Mon, 19 Sep 2016 12:54:56 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772583F0B5811@irsmsx105.ger.corp.intel.com> References: <1472228578-6980-1-git-send-email-tomaszx.kulasek@intel.com> <1473691487-10032-1-git-send-email-tomaszx.kulasek@intel.com> <1473691487-10032-6-git-send-email-tomaszx.kulasek@intel.com> In-Reply-To: <1473691487-10032-6-git-send-email-tomaszx.kulasek@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 5/6] ixgbe: add Tx preparation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Sep 2016 12:55:01 -0000 Hi Tomasz, > --- > drivers/net/ixgbe/ixgbe_ethdev.c | 3 ++ > drivers/net/ixgbe/ixgbe_ethdev.h | 8 +++- > drivers/net/ixgbe/ixgbe_rxtx.c | 83 ++++++++++++++++++++++++++++++++= +++++- > drivers/net/ixgbe/ixgbe_rxtx.h | 2 + > 4 files changed, 94 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_e= thdev.c > index fb618ef..1509979 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -515,6 +515,8 @@ static const struct rte_eth_desc_lim tx_desc_lim =3D = { > .nb_max =3D IXGBE_MAX_RING_DESC, > .nb_min =3D IXGBE_MIN_RING_DESC, > .nb_align =3D IXGBE_TXD_ALIGN, > + .nb_seg_max =3D IXGBE_TX_MAX_SEG, > + .nb_mtu_seg_max =3D IXGBE_TX_MAX_SEG, > }; >=20 > static const struct eth_dev_ops ixgbe_eth_dev_ops =3D { @@ -1101,6 +1103= ,7 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev) > eth_dev->dev_ops =3D &ixgbe_eth_dev_ops; > eth_dev->rx_pkt_burst =3D &ixgbe_recv_pkts; > eth_dev->tx_pkt_burst =3D &ixgbe_xmit_pkts; > + eth_dev->tx_pkt_prep =3D &ixgbe_prep_pkts; >=20 > /* > * For secondary processes, we don't initialise any further as primary = diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h > b/drivers/net/ixgbe/ixgbe_ethdev.h > index 4ff6338..09d96de 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.h > +++ b/drivers/net/ixgbe/ixgbe_ethdev.h > @@ -1,7 +1,7 @@ > /*- > * BSD LICENSE > * > - * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. > + * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. > * All rights reserved. > * > * Redistribution and use in source and binary forms, with or without > @@ -396,6 +396,12 @@ uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_= mbuf **tx_pkts, uint16_t ixgbe_xmit_pkts_simple(void > *tx_queue, struct rte_mbuf **tx_pkts, > uint16_t nb_pkts); >=20 > +uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, > + uint16_t nb_pkts); > + > +uint16_t ixgbe_prep_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkt= s, > + uint16_t nb_pkts); > + > int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev, > struct rte_eth_rss_conf *rss_conf); >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c index 8a306b0..87defa0 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -1,7 +1,7 @@ > /*- > * BSD LICENSE > * > - * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. > + * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. > * Copyright 2014 6WIND S.A. > * All rights reserved. > * > @@ -71,6 +71,7 @@ > #include > #include > #include > +#include >=20 > #include "ixgbe_logs.h" > #include "base/ixgbe_api.h" > @@ -906,6 +907,84 @@ end_of_tx: >=20 > /********************************************************************* > * > + * TX prep functions > + * > + > +**********************************************************************/ > +uint16_t > +ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t > +nb_pkts) { > + int i, ret; > + struct rte_mbuf *m; > + struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_queue; > + > + for (i =3D 0; i < nb_pkts; i++) { > + m =3D tx_pkts[i]; > + > + /** > + * Check if packet meets requirements for number of segments > + * > + * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and non-TSO > + */ > + > + if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) { > + rte_errno =3D -EINVAL; > + return i; > + } > + > + if ((m->ol_flags & PKT_TX_OFFLOAD_MASK) !=3D > + (m->ol_flags & IXGBE_TX_OFFLOAD_MASK)) { As a nit, it probably makes sense to: #define IXGBE_TX_OFFLOAD_NOTSUP_MASK (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOA= D_MASK) and then here: (m->ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) Might help to save few cycles. > + rte_errno =3D -EINVAL; > + return i; > + } > + > +#ifdef RTE_LIBRTE_ETHDEV_DEBUG > + ret =3D rte_validate_tx_offload(m); > + if (ret !=3D 0) { > + rte_errno =3D ret; > + return i; > + } > +#endif > + ret =3D rte_phdr_cksum_fix(m); We probable need to update rte_phdr_cksum_fix() to take into account tx_offload outer lengths in case PKT_TX_OUTER_IP_CKSUM is defined. As both ixgbe and i40e can do it these days.=20 Sorry for not spotting that earlier. > + if (ret !=3D 0) { > + rte_errno =3D ret; > + return i; > + } > + } > + > + return i; > +} > + > +/* ixgbe simple path as well as vector TX doesn't support tx offloads > +*/ uint16_t ixgbe_prep_pkts_simple(void *tx_queue __rte_unused, struct > +rte_mbuf **tx_pkts, > + uint16_t nb_pkts) > +{ > + int i; > + struct rte_mbuf *m; > + uint64_t ol_flags; > + > + for (i =3D 0; i < nb_pkts; i++) { > + m =3D tx_pkts[i]; > + ol_flags =3D m->ol_flags; > + > + /* simple tx path doesn't support multi-segments */ > + if (m->nb_segs !=3D 1) { > + rte_errno =3D -EINVAL; > + return i; > + } > + > + /* For simple path (simple and vector) no tx offloads are supported */ > + if (ol_flags & PKT_TX_OFFLOAD_MASK) { > + rte_errno =3D -EINVAL; > + return i; > + } > + } > + > + return i; > +} > + > +/********************************************************************* > + * > * RX functions > * > **********************************************************************/ > @@ -2290,6 +2369,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, stru= ct ixgbe_tx_queue *txq) > } else > #endif > dev->tx_pkt_burst =3D ixgbe_xmit_pkts_simple; > + dev->tx_pkt_prep =3D ixgbe_prep_pkts_simple; Shouldn't we setup ixgbe_prep_pkts_simple when vTX is selected too?=20 > } else { > PMD_INIT_LOG(DEBUG, "Using full-featured tx code path"); > PMD_INIT_LOG(DEBUG, > @@ -2301,6 +2381,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, stru= ct ixgbe_tx_queue *txq) > (unsigned long)txq->tx_rs_thresh, > (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST); > dev->tx_pkt_burst =3D ixgbe_xmit_pkts; > + dev->tx_pkt_prep =3D ixgbe_prep_pkts; > } > } >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxt= x.h index 2608b36..7bbd9b8 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.h > +++ b/drivers/net/ixgbe/ixgbe_rxtx.h > @@ -80,6 +80,8 @@ > #define RTE_IXGBE_WAIT_100_US 100 > #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2 >=20 > +#define IXGBE_TX_MAX_SEG 40 > + > #define IXGBE_PACKET_TYPE_MASK_82599 0X7F > #define IXGBE_PACKET_TYPE_MASK_X550 0X10FF > #define IXGBE_PACKET_TYPE_MASK_TUNNEL 0XFF > -- > 1.7.9.5