From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id E29B25688 for ; Tue, 6 Jun 2017 12:00:01 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2017 03:00:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,305,1493708400"; d="scan'208";a="96082257" Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2017 03:00:00 -0700 Received: from irsmsx109.ger.corp.intel.com ([169.254.13.250]) by IRSMSX106.ger.corp.intel.com ([169.254.8.236]) with mapi id 14.03.0319.002; Tue, 6 Jun 2017 10:59:59 +0100 From: "Ananyev, Konstantin" To: "Verkamp, Daniel" , "dev@dpdk.org" CC: "Richardson, Bruce" Thread-Topic: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation Thread-Index: AQHS29yUGhSpppN6a069aA11FRzec6ISDAhwgAAJcACAANJnAIADf1kAgAE3tZA= Date: Tue, 6 Jun 2017 09:59:59 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> References: <20170602200337.50743-1-daniel.verkamp@intel.com> <20170602201213.51143-1-daniel.verkamp@intel.com> <2601191342CEEE43887BDE71AB9772583FB05190@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB05216@IRSMSX109.ger.corp.intel.com> In-Reply-To: Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jun 2017 10:00:02 -0000 > > > > > > > > > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2 cache lines, so mem= bers > > of struct rte_ring are 128 byte aligned, > > >and therefore the whole struct needs 128-byte alignment according to t= he ABI > > so that the 128-byte alignment of the fields can be guaranteed. > > > > Ah ok, missed the fact that rte_ring is 128B aligned these days. > > BTW, I probably missed the initial discussion, but what was the reason = for that? > > Konstantin >=20 > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte alignment; it seems u= nnecessary if the cache line is only 64 bytes. An alternate > fix would be to just use cache line alignment for these fields (since mem= zones are already cache line aligned).=20 Yes, had the same thought. > Maybe there is some deeper reason for the >=3D 128-byte alignment logic = in rte_ring.h? Might be, would be good to hear opinion the author of that change.=20 Thanks Konstantin