From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 26B232BB9 for ; Thu, 8 Jun 2017 17:36:31 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jun 2017 08:36:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,315,1493708400"; d="scan'208";a="865921706" Received: from irsmsx154.ger.corp.intel.com ([163.33.192.96]) by FMSMGA003.fm.intel.com with ESMTP; 08 Jun 2017 08:36:29 -0700 Received: from irsmsx109.ger.corp.intel.com ([169.254.13.250]) by IRSMSX154.ger.corp.intel.com ([169.254.12.76]) with mapi id 14.03.0319.002; Thu, 8 Jun 2017 16:35:20 +0100 From: "Ananyev, Konstantin" To: "Richardson, Bruce" CC: Olivier Matz , "Verkamp, Daniel" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation Thread-Index: AQHS29yUGhSpppN6a069aA11FRzec6ISDAhwgAAJcACAANJnAIADf1kAgAE3tZCAAB0sgIAAGAMwgAANjQCAAwAeAIAACdYAgAAMdACAAAG1gIAAGaYw///604CAABKOsA== Date: Thu, 8 Jun 2017 15:35:20 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772583FB073AF@IRSMSX109.ger.corp.intel.com> References: <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com> <20170608144540.5a8e3603@platinum> <20170608132052.GA57628@bricha3-MOBL3.ger.corp.intel.com> <20170608160526.7953dd38@platinum> <20170608141133.GA58820@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB07371@IRSMSX109.ger.corp.intel.com> <20170608152449.GA63280@bricha3-MOBL3.ger.corp.intel.com> In-Reply-To: <20170608152449.GA63280@bricha3-MOBL3.ger.corp.intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jun 2017 15:36:32 -0000 > -----Original Message----- > From: Richardson, Bruce > Sent: Thursday, June 8, 2017 4:25 PM > To: Ananyev, Konstantin > Cc: Olivier Matz ; Verkamp, Daniel ; dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation >=20 > On Thu, Jun 08, 2017 at 03:50:34PM +0100, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: Richardson, Bruce > > > Sent: Thursday, June 8, 2017 3:12 PM > > > To: Olivier Matz > > > Cc: Ananyev, Konstantin ; Verkamp, Dani= el ; dev@dpdk.org > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocati= on > > > > > > On Thu, Jun 08, 2017 at 04:05:26PM +0200, Olivier Matz wrote: > > > > On Thu, 8 Jun 2017 14:20:52 +0100, Bruce Richardson wrote: > > > > > On Thu, Jun 08, 2017 at 02:45:40PM +0200, Olivier Matz wrote: > > > > > > On Tue, 6 Jun 2017 15:56:28 +0100, Bruce Richardson wrote: > > > > > > > On Tue, Jun 06, 2017 at 02:19:21PM +0100, Ananyev, Konstantin= wrote: > > > > > > > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > > > > From: Richardson, Bruce > > > > > > > > > Sent: Tuesday, June 6, 2017 1:42 PM > > > > > > > > > To: Ananyev, Konstantin > > > > > > > > > Cc: Verkamp, Daniel ; dev@dpdk.= org > > > > > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memz= one allocation > > > > > > > > > > > > > > > > > > On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev, Konsta= ntin wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2= cache lines, so members > > > > > > > > > > > > of struct rte_ring are 128 byte aligned, > > > > > > > > > > > > >and therefore the whole struct needs 128-byte alig= nment according to the ABI > > > > > > > > > > > > so that the 128-byte alignment of the fields can be= guaranteed. > > > > > > > > > > > > > > > > > > > > > > > > Ah ok, missed the fact that rte_ring is 128B aligne= d these days. > > > > > > > > > > > > BTW, I probably missed the initial discussion, but = what was the reason for that? > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > > > > > > > > > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte a= lignment; it seems unnecessary if the cache line is only 64 > bytes. > > > An > > > > > > > > > alternate > > > > > > > > > > > fix would be to just use cache line alignment for the= se fields (since memzones are already cache line aligned). > > > > > > > > > > > > > > > > > > > > Yes, had the same thought. > > > > > > > > > > > > > > > > > > > > > Maybe there is some deeper reason for the >=3D 128-b= yte alignment logic in rte_ring.h? > > > > > > > > > > > > > > > > > > > > Might be, would be good to hear opinion the author of t= hat change. > > > > > > > > > > > > > > > > > > It gives improved performance for core-2-core transfer. > > > > > > > > > > > > > > > > You mean empty cache-line(s) after prod/cons, correct? > > > > > > > > That's ok but why we can't keep them and whole rte_ring ali= gned on cache-line boundaries? > > > > > > > > Something like that: > > > > > > > > struct rte_ring { > > > > > > > > ... > > > > > > > > struct rte_ring_headtail prod __rte_cache_aligned; > > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > > struct rte_ring_headtail cons __rte_cache_aligned; > > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > > }; > > > > > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > Sure. That should probably work too. > > > > > > > > > > > > > > /Bruce > > > > > > > > > > > > I also agree with Konstantin's proposal. One question though: s= ince it > > > > > > changes the alignment constraint of the rte_ring structure, I t= hink it is > > > > > > an ABI breakage: a structure including the rte_ring structure i= nherits > > > > > > from this constraint. > > > > > > > > > > > > How could we handle that, knowing this is probably a rare case? > > > > > > > > > > > > > > > > > Is it an ABI break so long as we keep the resulting size and fiel= d > > > > > placement of the structures the same? The alignment being reduced= should > > > > > not be a problem, as 128byte alignment is also valid as 64byte > > > > > alignment, after all. > > > > > > > > I'd say yes. Consider the following example: > > > > > > > > ---8<--- > > > > #include > > > > #include > > > > > > > > #define ALIGN 64 > > > > /* #define ALIGN 128 */ > > > > > > > > /* dummy rte_ring struct */ > > > > struct rte_ring { > > > > char x[128]; > > > > } __attribute__((aligned(ALIGN))); > > > > > > > > struct foo { > > > > struct rte_ring r; > > > > unsigned bar; > > > > }; > > > > > > > > int main(void) > > > > { > > > > struct foo array[2]; > > > > > > > > printf("sizeof(ring)=3D%zu diff=3D%u\n", > > > > sizeof(struct rte_ring), > > > > (unsigned int)((char *)&array[1].r - (char *)array)); > > > > > > > > return 0; > > > > } > > > > ---8<--- > > > > > > > > The size of rte_ring is always 128. > > > > diff is 192 or 256, depending on the value of ALIGN. > > > > > > > > > > > > > > > > Olivier > > > > About would it be an ABI breakage to 17.05 - I think would... > > Though for me the actual breakage happens in 17.05 when rte_ring > > alignment was increased from 64B 128B. > > Now we just restoring it. > > > Yes, ABI change was announced in advance and explicitly broken in 17.05. > There was no announcement of ABI break in 17.08 for rte_ring. >=20 > > > > > > Yes, the diff will change, but that is after a recompile. If we have > > > rte_ring_create function always return a 128-byte aligned structure, > > > will any already-compiled apps fail to work if we also change the ali= gnment > > > of the rte_ring struct in the header? > > > > Why 128B? > > I thought we are discussing making rte_ring 64B aligned again? > > > > Konstantin >=20 > To avoid possibly breaking apps compiled against 17.05 when run against > shared libs for 17.08. Having the extra alignment won't affect 17.08 > apps, since they only require 64-byte alignment, but returning only > 64-byte aligned memory for apps which expect 128byte aligned memory may > cause issues. >=20 > Therefore, we should reduce the required alignment to 64B, which should > only affect any apps that do a recompile, and have memory allocation for > rings return 128B aligned addresses to work with both 64B aligned and > 128B aligned ring structures. Ah, I see - you are talking just about rte_ring_create(). BTW, are you sure that right now it allocates rings 128B aligned? As I can see it does just: mz =3D rte_memzone_reserve(mz_name, ring_size, socket_id, mz_flags); which means cache line alignment. Konstantin