From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id CEBDE11C5 for ; Thu, 8 Jun 2017 18:43:07 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jun 2017 09:42:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,315,1493708400"; d="scan'208";a="1179999506" Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga002.fm.intel.com with ESMTP; 08 Jun 2017 09:42:02 -0700 Received: from irsmsx109.ger.corp.intel.com ([169.254.13.250]) by irsmsx110.ger.corp.intel.com ([163.33.3.25]) with mapi id 14.03.0319.002; Thu, 8 Jun 2017 17:42:01 +0100 From: "Ananyev, Konstantin" To: "Richardson, Bruce" CC: Olivier Matz , "Verkamp, Daniel" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation Thread-Index: AQHS29yUGhSpppN6a069aA11FRzec6ISDAhwgAAJcACAANJnAIADf1kAgAE3tZCAAB0sgIAAGAMwgAANjQCAAwAeAIAACdYAgAAMdACAAAG1gIAAGaYw///604CAABKOsP//+EoAgAASxfD///HzgAACym6w Date: Thu, 8 Jun 2017 16:42:00 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772583FB07405@IRSMSX109.ger.corp.intel.com> References: <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com> <20170608144540.5a8e3603@platinum> <20170608132052.GA57628@bricha3-MOBL3.ger.corp.intel.com> <20170608160526.7953dd38@platinum> <20170608141133.GA58820@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB07371@IRSMSX109.ger.corp.intel.com> <20170608152449.GA63280@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB073AF@IRSMSX109.ger.corp.intel.com> <20170608160338.GA60420@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB073D7@IRSMSX109.ger.corp.intel.com> <59AF69C657FD0841A61C55336867B5B07217C2ED@IRSMSX104.ger.corp.intel.com> In-Reply-To: <59AF69C657FD0841A61C55336867B5B07217C2ED@IRSMSX104.ger.corp.intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jun 2017 16:43:09 -0000 > -----Original Message----- > From: Richardson, Bruce > Sent: Thursday, June 8, 2017 5:21 PM > To: Ananyev, Konstantin > Cc: Olivier Matz ; Verkamp, Daniel ; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation >=20 >=20 >=20 > > -----Original Message----- > > From: Ananyev, Konstantin > > Sent: Thursday, June 8, 2017 5:13 PM > > To: Richardson, Bruce > > Cc: Olivier Matz ; Verkamp, Daniel > > ; dev@dpdk.org > > Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > > > > -----Original Message----- > > > From: Richardson, Bruce > > > Sent: Thursday, June 8, 2017 5:04 PM > > > To: Ananyev, Konstantin > > > Cc: Olivier Matz ; Verkamp, Daniel > > > ; dev@dpdk.org > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone > > > allocation > > > > > > On Thu, Jun 08, 2017 at 04:35:20PM +0100, Ananyev, Konstantin wrote: > > > > > > > > > > > > > -----Original Message----- > > > > > From: Richardson, Bruce > > > > > Sent: Thursday, June 8, 2017 4:25 PM > > > > > To: Ananyev, Konstantin > > > > > Cc: Olivier Matz ; Verkamp, Daniel > > > > > ; dev@dpdk.org > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone > > > > > allocation > > > > > > > > > > On Thu, Jun 08, 2017 at 03:50:34PM +0100, Ananyev, Konstantin wro= te: > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > > From: Richardson, Bruce > > > > > > > Sent: Thursday, June 8, 2017 3:12 PM > > > > > > > To: Olivier Matz > > > > > > > Cc: Ananyev, Konstantin ; > > > > > > > Verkamp, Daniel ; dev@dpdk.org > > > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone > > > > > > > allocation > > > > > > > > > > > > > > On Thu, Jun 08, 2017 at 04:05:26PM +0200, Olivier Matz wrote: > > > > > > > > On Thu, 8 Jun 2017 14:20:52 +0100, Bruce Richardson > > wrote: > > > > > > > > > On Thu, Jun 08, 2017 at 02:45:40PM +0200, Olivier Matz > > wrote: > > > > > > > > > > On Tue, 6 Jun 2017 15:56:28 +0100, Bruce Richardson > > wrote: > > > > > > > > > > > On Tue, Jun 06, 2017 at 02:19:21PM +0100, Ananyev, > > Konstantin wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > > > > > > > > From: Richardson, Bruce > > > > > > > > > > > > > Sent: Tuesday, June 6, 2017 1:42 PM > > > > > > > > > > > > > To: Ananyev, Konstantin > > > > > > > > > > > > > > > > > > > > > > > > > > Cc: Verkamp, Daniel ; > > > > > > > > > > > > > dev@dpdk.org > > > > > > > > > > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use > > > > > > > > > > > > > aligned memzone allocation > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev= , > > Konstantin wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The PROD/CONS_ALIGN values on x86-64 are > > > > > > > > > > > > > > > > > set to 2 cache lines, so members > > > > > > > > > > > > > > > > of struct rte_ring are 128 byte aligned, > > > > > > > > > > > > > > > > >and therefore the whole struct needs > > > > > > > > > > > > > > > > >128-byte alignment according to the ABI > > > > > > > > > > > > > > > > so that the 128-byte alignment of the field= s > > can be guaranteed. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Ah ok, missed the fact that rte_ring is 128= B > > aligned these days. > > > > > > > > > > > > > > > > BTW, I probably missed the initial discussi= on, > > but what was the reason for that? > > > > > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't know why PROD_ALIGN/CONS_ALIGN use 12= 8 > > > > > > > > > > > > > > > byte alignment; it seems unnecessary if the > > > > > > > > > > > > > > > cache line is only 64 > > > > > bytes. > > > > > > > An > > > > > > > > > > > > > alternate > > > > > > > > > > > > > > > fix would be to just use cache line alignment > > for these fields (since memzones are already cache line aligned). > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, had the same thought. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Maybe there is some deeper reason for the >= =3D > > 128-byte alignment logic in rte_ring.h? > > > > > > > > > > > > > > > > > > > > > > > > > > > > Might be, would be good to hear opinion the aut= hor > > of that change. > > > > > > > > > > > > > > > > > > > > > > > > > > It gives improved performance for core-2-core > > transfer. > > > > > > > > > > > > > > > > > > > > > > > > You mean empty cache-line(s) after prod/cons, corre= ct? > > > > > > > > > > > > That's ok but why we can't keep them and whole > > rte_ring aligned on cache-line boundaries? > > > > > > > > > > > > Something like that: > > > > > > > > > > > > struct rte_ring { > > > > > > > > > > > > ... > > > > > > > > > > > > struct rte_ring_headtail prod __rte_cache_aligne= d; > > > > > > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > > > > > > struct rte_ring_headtail cons __rte_cache_aligne= d; > > > > > > > > > > > > EMPTY_CACHE_LINE __rte_cache_aligned; > > > > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > > > > > Konstantin > > > > > > > > > > > > > > > > > > > > > > Sure. That should probably work too. > > > > > > > > > > > > > > > > > > > > > > /Bruce > > > > > > > > > > > > > > > > > > > > I also agree with Konstantin's proposal. One question > > > > > > > > > > though: since it changes the alignment constraint of th= e > > > > > > > > > > rte_ring structure, I think it is an ABI breakage: a > > > > > > > > > > structure including the rte_ring structure inherits fro= m > > this constraint. > > > > > > > > > > > > > > > > > > > > How could we handle that, knowing this is probably a ra= re > > case? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Is it an ABI break so long as we keep the resulting size > > > > > > > > > and field placement of the structures the same? The > > > > > > > > > alignment being reduced should not be a problem, as > > > > > > > > > 128byte alignment is also valid as 64byte alignment, afte= r > > all. > > > > > > > > > > > > > > > > I'd say yes. Consider the following example: > > > > > > > > > > > > > > > > ---8<--- > > > > > > > > #include > > > > > > > > #include > > > > > > > > > > > > > > > > #define ALIGN 64 > > > > > > > > /* #define ALIGN 128 */ > > > > > > > > > > > > > > > > /* dummy rte_ring struct */ > > > > > > > > struct rte_ring { > > > > > > > > char x[128]; > > > > > > > > } __attribute__((aligned(ALIGN))); > > > > > > > > > > > > > > > > struct foo { > > > > > > > > struct rte_ring r; > > > > > > > > unsigned bar; > > > > > > > > }; > > > > > > > > > > > > > > > > int main(void) > > > > > > > > { > > > > > > > > struct foo array[2]; > > > > > > > > > > > > > > > > printf("sizeof(ring)=3D%zu diff=3D%u\n", > > > > > > > > sizeof(struct rte_ring), > > > > > > > > (unsigned int)((char *)&array[1].r - (char > > *)array)); > > > > > > > > > > > > > > > > return 0; > > > > > > > > } > > > > > > > > ---8<--- > > > > > > > > > > > > > > > > The size of rte_ring is always 128. > > > > > > > > diff is 192 or 256, depending on the value of ALIGN. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Olivier > > > > > > > > > > > > About would it be an ABI breakage to 17.05 - I think would... > > > > > > Though for me the actual breakage happens in 17.05 when rte_rin= g > > > > > > alignment was increased from 64B 128B. > > > > > > Now we just restoring it. > > > > > > > > > > > Yes, ABI change was announced in advance and explicitly broken in > > 17.05. > > > > > There was no announcement of ABI break in 17.08 for rte_ring. > > > > > > > > > > > > > > > > > > > Yes, the diff will change, but that is after a recompile. If > > > > > > > we have rte_ring_create function always return a 128-byte > > > > > > > aligned structure, will any already-compiled apps fail to wor= k > > > > > > > if we also change the alignment of the rte_ring struct in the > > header? > > > > > > > > > > > > Why 128B? > > > > > > I thought we are discussing making rte_ring 64B aligned again? > > > > > > > > > > > > Konstantin > > > > > > > > > > To avoid possibly breaking apps compiled against 17.05 when run > > > > > against shared libs for 17.08. Having the extra alignment won't > > > > > affect 17.08 apps, since they only require 64-byte alignment, but > > > > > returning only 64-byte aligned memory for apps which expect > > > > > 128byte aligned memory may cause issues. > > > > > > > > > > Therefore, we should reduce the required alignment to 64B, which > > > > > should only affect any apps that do a recompile, and have memory > > > > > allocation for rings return 128B aligned addresses to work with > > > > > both 64B aligned and 128B aligned ring structures. > > > > > > > > Ah, I see - you are talking just about rte_ring_create(). > > > > BTW, are you sure that right now it allocates rings 128B aligned? > > > > As I can see it does just: > > > > mz =3D rte_memzone_reserve(mz_name, ring_size, socket_id, mz_flags)= ; > > > > which means cache line alignment. > > > > > > > It doesn't currently allocate with that alignment, which is something > > > we need to fix - and what this patch was originally submitted to do. > > > So I think this patch should be applied, along with a further patch t= o > > > reduce the alignment going forward to avoid any other problems. > > > > But if we going to reduce alignment anyway (patch #2) why do we need pa= tch > > #1 at all? >=20 > Because any app compiled against 17.05 will use the old alignment value. = Therefore patch 1 should be applied to 17.08 for backward > compatibility, and backported to 17.05.1. Why then just no backport patch #2 to 17.05.1?