From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 5E5B01B39E for ; Thu, 12 Oct 2017 19:06:02 +0200 (CEST) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2017 10:06:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,366,1503385200"; d="scan'208";a="137859920" Received: from irsmsx108.ger.corp.intel.com ([163.33.3.3]) by orsmga004.jf.intel.com with ESMTP; 12 Oct 2017 10:05:51 -0700 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.49]) by IRSMSX108.ger.corp.intel.com ([169.254.11.167]) with mapi id 14.03.0319.002; Thu, 12 Oct 2017 18:05:50 +0100 From: "Ananyev, Konstantin" To: Olivier MATZ , Jia He CC: "dev@dpdk.org" , "jia.he@hxt-semitech.com" , "jie2.liu@hxt-semitech.com" , "bing.zhao@hxt-semitech.com" , "jerin.jacob@caviumnetworks.com" Thread-Topic: [PATCH] ring: guarantee ordering of cons/prod loading when doing enqueue/dequeue Thread-Index: AQHTQ3J26efi+G3l00mtTlAiWDrZp6Lgbx+A Date: Thu, 12 Oct 2017 17:05:50 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772585FAA859F@IRSMSX103.ger.corp.intel.com> References: <20171010095636.4507-1-hejianet@gmail.com> <20171012155350.j34ddtivxzd27pag@platinum> In-Reply-To: <20171012155350.j34ddtivxzd27pag@platinum> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTdhMmVhYmEtOTZmYy00Njg3LWI5MDQtZDEyNzY0MmM2ZDhhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6Inl2M25weGZTT2E2d2Y0MUJcL25uYjdic2I4cE5Xc01iYXkyV0t2a1A5NkJ3PSJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] ring: guarantee ordering of cons/prod loading when doing enqueue/dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Oct 2017 17:06:02 -0000 Hi guys, > -----Original Message----- > From: Olivier MATZ [mailto:olivier.matz@6wind.com] > Sent: Thursday, October 12, 2017 4:54 PM > To: Jia He > Cc: dev@dpdk.org; jia.he@hxt-semitech.com; jie2.liu@hxt-semitech.com; bin= g.zhao@hxt-semitech.com; Ananyev, Konstantin > ; jerin.jacob@caviumnetworks.com > Subject: Re: [PATCH] ring: guarantee ordering of cons/prod loading when d= oing enqueue/dequeue >=20 > Hi, >=20 > On Tue, Oct 10, 2017 at 05:56:36PM +0800, Jia He wrote: > > Before this patch: > > In __rte_ring_move_cons_head() > > ... > > do { > > /* Restore n as it may change every loop */ > > n =3D max; > > > > *old_head =3D r->cons.head; //1st load > > const uint32_t prod_tail =3D r->prod.tail; //2nd load > > > > In weak memory order architectures(powerpc,arm), the 2nd load might be > > reodered before the 1st load, that makes *entries is bigger than we wan= ted. > > This nasty reording messed enque/deque up. > > > > cpu1(producer) cpu2(consumer) cpu3(consumer) > > load r->prod.tail > > in enqueue: > > load r->cons.tail > > load r->prod.head > > > > store r->prod.tail > > > > load r->cons.head > > load r->prod.tail > > ... > > store r->cons.{head,tai= l} > > load r->cons.head > > > > THEN,r->cons.head will be bigger than prod_tail, then make *entries ver= y big > > > > After this patch, the old cons.head will be recaculated after failure o= f > > rte_atomic32_cmpset > > > > There is no such issue in X86 cpu, because X86 is strong memory order m= odel > > > > Signed-off-by: Jia He > > Signed-off-by: jia.he@hxt-semitech.com > > Signed-off-by: jie2.liu@hxt-semitech.com > > Signed-off-by: bing.zhao@hxt-semitech.com > > > > --- > > lib/librte_ring/rte_ring.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > > index 5e9b3b7..15c72e2 100644 > > --- a/lib/librte_ring/rte_ring.h > > +++ b/lib/librte_ring/rte_ring.h > > @@ -409,6 +409,10 @@ __rte_ring_move_prod_head(struct rte_ring *r, int = is_sp, > > n =3D max; > > > > *old_head =3D r->prod.head; > > + > > + /* load of prod.tail can't be reordered before cons.head */ > > + rte_smp_rmb(); > > + > > const uint32_t cons_tail =3D r->cons.tail; > > /* > > * The subtraction is done between two unsigned 32bits value > > @@ -517,6 +521,10 @@ __rte_ring_move_cons_head(struct rte_ring *r, int = is_sc, > > n =3D max; > > > > *old_head =3D r->cons.head; > > + > > + /* load of prod.tail can't be reordered before cons.head */ > > + rte_smp_rmb(); > > + > > const uint32_t prod_tail =3D r->prod.tail; > > /* The subtraction is done between two unsigned 32bits value > > * (the result is always modulo 32 bits even if we have > > -- > > 2.7.4 > > >=20 > The explanation convinces me. >=20 > However, since it's in a critical path, it would be good to have other > opinions. This patch reminds me this discussion, that was also related to > memory barrier, but at another place: > http://dpdk.org/ml/archives/dev/2016-July/043765.html > Lead to that patch: http://dpdk.org/browse/dpdk/commit/?id=3Decc7d10e448e > But finally reverted: http://dpdk.org/browse/dpdk/commit/?id=3Dc3acd92746= c3 >=20 > Konstatin, Jerin, do you have any comment? For IA, as rte_smp_rmb() is just a compiler_barrier, that patch shouldn't m= ake any difference, but I can't see how read reordering would screw things up here... Probably just me and arm or ppc guys could explain what will be the problem if let say cons.tail will be read before prod.head in __rte_ring_move_prod_= head(). I wonder Is there a simple test-case to reproduce that problem (on arm or p= pc)? Probably new test-case for rte_ring autotest is needed, or is it possible t= o reproduce it with existing one? =20 Konstantin