From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id D18141B216 for ; Wed, 8 Nov 2017 19:36:06 +0100 (CET) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Nov 2017 10:36:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,365,1505804400"; d="scan'208";a="173856637" Received: from irsmsx109.ger.corp.intel.com ([163.33.3.23]) by fmsmga006.fm.intel.com with ESMTP; 08 Nov 2017 10:36:03 -0800 Received: from irsmsx112.ger.corp.intel.com (10.108.20.5) by IRSMSX109.ger.corp.intel.com (163.33.3.23) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 8 Nov 2017 18:36:02 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.67]) by irsmsx112.ger.corp.intel.com ([169.254.1.12]) with mapi id 14.03.0319.002; Wed, 8 Nov 2017 18:36:02 +0000 From: "Ananyev, Konstantin" To: Jia He , "Richardson, Bruce" CC: "jerin.jacob@caviumnetworks.com" , "dev@dpdk.org" , "olivier.matz@6wind.com" , "jianbo.liu@arm.com" , "hemant.agrawal@nxp.com" Thread-Topic: [PATCH v4 0/4] fix race condition in enqueue/dequeue because of cpu reorder Thread-Index: AQHTWHgG6yvGCkEn00WZouJbG4saTaMKZbKAgAAxFgCAADjpsA== Date: Wed, 8 Nov 2017 18:36:01 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772585FABAF34@irsmsx105.ger.corp.intel.com> References: <1510118764-29697-1-git-send-email-hejianet@gmail.com> <1510134881-22987-1-git-send-email-hejianet@gmail.com> <20171108121550.GA9632@bricha3-MOBL3.ger.corp.intel.com> In-Reply-To: Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMDliNzhlMjYtNDcwZS00OGQ1LWJjNWItNGVlMDM1MTVjNTE3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6InhpUzZqbEEwdDVsXC9QMlY2SGJcLzNhMithS0l4SzdYQVhKZ2ZLeEtxVWxRcz0ifQ== x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 0/4] fix race condition in enqueue/dequeue because of cpu reorder X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Nov 2017 18:36:07 -0000 > -----Original Message----- > From: Jia He [mailto:hejianet@gmail.com] > Sent: Wednesday, November 8, 2017 3:12 PM > To: Richardson, Bruce > Cc: jerin.jacob@caviumnetworks.com; dev@dpdk.org; olivier.matz@6wind.com;= Ananyev, Konstantin ; > jianbo.liu@arm.com; hemant.agrawal@nxp.com > Subject: Re: [PATCH v4 0/4] fix race condition in enqueue/dequeue because= of cpu reorder >=20 > Hi Bruce >=20 >=20 > On 11/8/2017 8:15 PM, Bruce Richardson Wrote: > > On Wed, Nov 08, 2017 at 09:54:37AM +0000, Jia He wrote: > >> We watched a rte panic of mbuf_autotest in our qualcomm arm64 server > >> due to a possible race condition. > >> > >> To fix this race, there are 2 options as suggested by Jerin: 1. use > >> rte_smp_rmb 2. use load_acquire/store_release(refer to [2]). > >> CONFIG_RTE_RING_USE_C11_MEM_MODEL is provided, and by default it is > >> "y" only on arm64 so far. > >> > >> The reason why providing 2 options is due to the performance benchmark > >> difference in different arm machines. > >> > >> Already fuctionally tested on the machines as follows: - on X86 - on > >> arm64 with CONFIG_RTE_RING_USE_C11_MEM_MODEL=3Dy - on arm64 with > >> CONFIG_RTE_RING_USE_C11_MEM_MODEL=3Dn > >> > >> --- Changelog: V4: split into small patches V3: arch specific > >> implementation for enqueue/dequeue barrier V2: let users choose > >> whether using load_acquire/store_release V1: rte_smp_rmb() between 2 > >> loads > >> > >> Jia He (4): eal/arm64: remove the braces {} for dmb() and dsb() ring: > >> guarantee load/load order in enqueue and dequeue ring: introduce new > >> header file to include common functions ring: introduce new header > >> file to support C11 memory model > >> > > I'm wondering what the merge plans are for this set, given we are now > > past RC3 in 17.11? As the rings are broken on ARM machines we need to > > merge in some fix, but I'm a little concerned about the scope of the > > changes from the 3rd and 4th patches. Would it be acceptable to just > > merge in patches 1 & 2 in 17.11 and leave the rework and C11 memory > > model additions in patches 3 & 4 to 18.02 release? > As far as I'm concerned, it is ok. Sounds good to me too. Konstantin=20