From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id D647314E8 for ; Mon, 11 Dec 2017 18:30:21 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2017 09:30:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,392,1508828400"; d="scan'208";a="10974427" Received: from irsmsx109.ger.corp.intel.com ([163.33.3.23]) by FMSMGA003.fm.intel.com with ESMTP; 11 Dec 2017 09:30:20 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.67]) by IRSMSX109.ger.corp.intel.com ([169.254.13.28]) with mapi id 14.03.0319.002; Mon, 11 Dec 2017 17:30:09 +0000 From: "Ananyev, Konstantin" To: "Richardson, Bruce" CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() Thread-Index: AQHTapVd3bedCUxRrkamiGA53GG7LqM+cPaAgAAE8aA= Date: Mon, 11 Dec 2017 17:30:08 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772585FAC8193@irsmsx105.ger.corp.intel.com> References: <1512126771-27503-1-git-send-email-konstantin.ananyev@intel.com> <1512126771-27503-2-git-send-email-konstantin.ananyev@intel.com> <20171211171121.GB2232@bricha3-MOBL3.ger.corp.intel.com> In-Reply-To: <20171211171121.GB2232@bricha3-MOBL3.ger.corp.intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjY1YTViZWUtMjJlYy00ZGZjLTg0NTMtYzAzY2QxMzU0N2FiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6InpuTk5USFpjS2owUldmcER1Y2VGWXdHVG9EVE1mNVo3M0ZaTm9aeWJ3MXc9In0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Dec 2017 17:30:22 -0000 Hi Bruce, > -----Original Message----- > From: Richardson, Bruce > Sent: Monday, December 11, 2017 5:11 PM > To: Ananyev, Konstantin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH 2/2] eal/x86: Use lock-prefixed instructio= ns to reduce cost of rte_smp_mb() >=20 > On Fri, Dec 01, 2017 at 11:12:51AM +0000, Konstantin Ananyev wrote: > > On x86 it is possible to use lock-prefixed instructions to get > > the similar effect as mfence. > > As pointed by Java guys, on most modern HW that gives a better > > performance than using mfence: > > https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > > That patch adopts that technique for rte_smp_mb() implementation. > > On BDW 2.2 mb_autotest on single lcore reports 2X cycle reduction, > > i.e. from ~110 to ~55 cycles per operation. > > > > Signed-off-by: Konstantin Ananyev > > --- > > .../common/include/arch/x86/rte_atomic.h | 45 ++++++++++++++= +++++++- > > 1 file changed, 43 insertions(+), 2 deletions(-) > > > > > + * As pointed by Java guys, that makes possible to use lock-prefixed > > + * instructions to get the same effect as mfence and on most modern HW > > + * that gives a better perfomarnce than using mfence: > > + * https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > > + * So below we use that technique for rte_smp_mb() implementation. > > + */ > > + > > +#ifdef RTE_ARCH_I686 > > +#define RTE_SP RTE_STR(esp) > > +#else > > +#define RTE_SP RTE_STR(rsp) > > +#endif > > + > > +#define RTE_MB_DUMMY_MEMP "-128(%%" RTE_SP ")" > > + > > +static __rte_always_inline void > > +rte_smp_mb(void) > > +{ > > + asm volatile("lock addl $0," RTE_MB_DUMMY_MEMP "; " ::: "memory"); > > +} >=20 > Rather than #defining RTE_SP and RTE_MB_DUMMY_MEMP, why not just put the > #ifdef into the rte_smp_mb itself and have two asm volatile lines with > hard-coded register names in them? It would be shorter and I think a lot > easier to read. Fine by me. Any other thoughts from anyone till I submit v2? Konstantin