From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 70C441B37D for ; Mon, 29 Jan 2018 10:29:56 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jan 2018 01:29:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,429,1511856000"; d="scan'208";a="13869173" Received: from irsmsx105.ger.corp.intel.com ([163.33.3.28]) by fmsmga008.fm.intel.com with ESMTP; 29 Jan 2018 01:29:54 -0800 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.197]) by irsmsx105.ger.corp.intel.com ([169.254.7.221]) with mapi id 14.03.0319.002; Mon, 29 Jan 2018 09:29:53 +0000 From: "Ananyev, Konstantin" To: "Michael S. Tsirkin" , Maxime Coquelin CC: "dev@dpdk.org" , "Richardson, Bruce" Thread-Topic: Fwd: [dpdk-dev] [PATCH v3 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() Thread-Index: AQHTjhJJBKFAxWa2jEus7ykKi2KxaKN1CYuAgAC0VleAFOuLYA== Date: Mon, 29 Jan 2018 09:29:52 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725890565030@IRSMSX103.ger.corp.intel.com> References: <1516028971-3409-1-git-send-email-konstantin.ananyev@intel.com> <8b05f533-d146-7f97-48f4-82ddcfc3613b@redhat.com> <20180116035158-mutt-send-email-mst@kernel.org> In-Reply-To: <20180116035158-mutt-send-email-mst@kernel.org> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjUyMWQ4MzQtMzJlMy00ZmQ3LWE1OTktYzFhMzE5Y2U2ZmM4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IkZQTm1jR1pCenZzRzhUQ2puTUxPdlR0MUNSU29Qd1BwN1wvcGlwN1owdVBNPSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] Fwd: [PATCH v3 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Jan 2018 09:29:57 -0000 Hi Michael, >=20 > On Mon, Jan 15, 2018 at 04:15:00PM +0100, Maxime Coquelin wrote: > > Hi Michael, > > > > FYI: > > > > -------- Forwarded Message -------- > > Subject: [dpdk-dev] [PATCH v3 2/2] eal/x86: Use lock-prefixed instructi= ons > > to reduce cost of rte_smp_mb() > > Date: Mon, 15 Jan 2018 15:09:31 +0000 > > From: Konstantin Ananyev > > To: dev@dpdk.org > > CC: Konstantin Ananyev > > > > On x86 it is possible to use lock-prefixed instructions to get > > the similar effect as mfence. > > As pointed by Java guys, on most modern HW that gives a better > > performance than using mfence: > > https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > > That patch adopts that technique for rte_smp_mb() implementation. > > On BDW 2.2 mb_autotest on single lcore reports 2X cycle reduction, > > i.e. from ~110 to ~55 cycles per operation. > > > > Signed-off-by: Konstantin Ananyev > > Acked-by: Bruce Richardson > > --- > > .../common/include/arch/x86/rte_atomic.h | 44 > > +++++++++++++++++++++- > > 1 file changed, 42 insertions(+), 2 deletions(-) > > > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h > > b/lib/librte_eal/common/include/arch/x86/rte_atomic.h > > index 8469f97e1..9d466d94a 100644 > > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h > > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h > > @@ -26,12 +26,52 @@ extern "C" { > > #define rte_rmb() _mm_lfence() > > -#define rte_smp_mb() rte_mb() > > - > > #define rte_smp_wmb() rte_compiler_barrier() > > #define rte_smp_rmb() rte_compiler_barrier() > > +/* > > + * From Intel Software Development Manual; Vol 3; > > + * 8.2.2 Memory Ordering in P6 and More Recent Processor Families: > > + * ... > > + * . Reads are not reordered with other reads. > > + * . Writes are not reordered with older reads. > > + * . Writes to memory are not reordered with other writes, > > + * with the following exceptions: > > + * . streaming stores (writes) executed with the non-temporal move > > + * instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); a= nd > > + * . string operations (see Section 8.2.4.1). > > + * ... > > + * . Reads may be reordered with older writes to different locations b= ut > > not > > + * with older writes to the same location. > > + * . Reads or writes cannot be reordered with I/O instructions, > > + * locked instructions, or serializing instructions. > > + * . Reads cannot pass earlier LFENCE and MFENCE instructions. > > + * . Writes ... cannot pass earlier LFENCE, SFENCE, and MFENCE > > instructions. > > + * . LFENCE instructions cannot pass earlier reads. > > + * . SFENCE instructions cannot pass earlier writes ... > > + * . MFENCE instructions cannot pass earlier reads, writes ... > > + * > > + * As pointed by Java guys, that makes possible to use lock-prefixed > > + * instructions to get the same effect as mfence and on most modern HW > > + * that gives a better perfomance then using mfence: > > + * https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ > > + * Basic idea is to use lock prefixed add with some dummy memory locat= ion > > + * as the destination. From their experiments 128B(2 cache lines) belo= w > > + * current stack pointer looks like a good candidate. > > + * So below we use that techinque for rte_smp_mb() implementation. > > + */ > > + > > +static __rte_always_inline void > > +rte_smp_mb(void) > > +{ > > +#ifdef RTE_ARCH_I686 > > + asm volatile("lock addl $0, -128(%%esp); " ::: "memory"); > > +#else > > + asm volatile("lock addl $0, -128(%%rsp); " ::: "memory"); > > +#endif > > +} > > + > > #define rte_io_mb() rte_mb() > > #define rte_io_wmb() rte_compiler_barrier() >=20 > In my testing this appears to be suboptimal when the calling > function is large. The following seems to work better: >=20 > +static __rte_always_inline void > +rte_smp_mb(void) > +{ > +#ifdef RTE_ARCH_I686 > + asm volatile("lock addl $0, -132(%%esp); " ::: "memory"); > +#else > + asm volatile("lock addl $0, -132(%%rsp); " ::: "memory"); > +#endif > +} > + >=20 > The reason most likely is that 128 still overlaps the x86 > red zone by 4 bytes. I tried what you suggested but for my cases didn't see any improvement so f= ar. Can you explain a bit more why do you expect it to be faster? Probably some particular scenario? Konstantin >=20 > Feel free to reuse, and add > Signed-off-by: Michael S. Tsirkin >=20 >=20 > > -- > > 2.13.6