* [dpdk-dev] [PATCH 01/29] net/sfc/base: enable chained multicast on all EF10 cards
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 02/29] net/sfc/base: fix signed/unsigned mismatch errors Andrew Rybchenko
` (28 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar, stable
From: Gautam Dawar <gdawar@solarflare.com>
Set WORKAROUND_BUG26807 which does the job.
Fix the misunderstanding in the Medford code: i.e. the workaround is
always supported by firmware, but the driver still needs to enable it.
Also, as it now applies to all EF10 controllers, the implementation is
moved to EF10 common place.
Fixes: 94190e3543bf ("net/sfc/base: import SFN8xxx family support")
Fixes: 2b38e7b7b7e1 ("net/sfc/base: add Medford2 support to NIC module")
Cc: stable@dpdk.org
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 57 ++++++++++++++++++++++++++++++++++++-
drivers/net/sfc/base/hunt_nic.c | 41 ++------------------------
drivers/net/sfc/base/medford2_nic.c | 3 --
drivers/net/sfc/base/medford_nic.c | 3 --
4 files changed, 58 insertions(+), 46 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index e5e8469..1d7e6d8 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1753,6 +1753,56 @@
}
static __checkReturn efx_rc_t
+ef10_set_workaround_bug26807(
+ __in efx_nic_t *enp)
+{
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+ uint32_t flags;
+ efx_rc_t rc;
+
+ /*
+ * If the bug26807 workaround is enabled, then firmware has enabled
+ * support for chained multicast filters. Firmware will reset (FLR)
+ * functions which have filters in the hardware filter table when the
+ * workaround is enabled/disabled.
+ *
+ * We must recheck if the workaround is enabled after inserting the
+ * first hardware filter, in case it has been changed since this check.
+ */
+ rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
+ B_TRUE, &flags);
+ if (rc == 0) {
+ encp->enc_bug26807_workaround = B_TRUE;
+ if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
+ /*
+ * Other functions had installed filters before the
+ * workaround was enabled, and they have been reset
+ * by firmware.
+ */
+ EFSYS_PROBE(bug26807_workaround_flr_done);
+ /* FIXME: bump MC warm boot count ? */
+ }
+ } else if (rc == EACCES) {
+ /*
+ * Unprivileged functions cannot enable the workaround in older
+ * firmware.
+ */
+ encp->enc_bug26807_workaround = B_FALSE;
+ } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
+ encp->enc_bug26807_workaround = B_FALSE;
+ } else {
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+static __checkReturn efx_rc_t
ef10_nic_board_cfg(
__in efx_nic_t *enp)
{
@@ -1910,13 +1960,18 @@
goto fail10;
encp->enc_privilege_mask = mask;
+ if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
+ goto fail11;
+
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
- goto fail11;
+ goto fail12;
return (0);
+fail12:
+ EFSYS_PROBE(fail12);
fail11:
EFSYS_PROBE(fail11);
fail10:
diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 054d4f4..1e2b075 100644
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -72,7 +72,6 @@
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_port_t *epp = &(enp->en_port);
- uint32_t flags;
uint32_t sysclk, dpcpu_clk;
uint32_t bandwidth;
efx_rc_t rc;
@@ -130,43 +129,9 @@
encp->enc_bug41750_workaround = B_TRUE;
}
- /*
- * If the bug26807 workaround is enabled, then firmware has enabled
- * support for chained multicast filters. Firmware will reset (FLR)
- * functions which have filters in the hardware filter table when the
- * workaround is enabled/disabled.
- *
- * We must recheck if the workaround is enabled after inserting the
- * first hardware filter, in case it has been changed since this check.
- */
- rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
- B_TRUE, &flags);
- if (rc == 0) {
- encp->enc_bug26807_workaround = B_TRUE;
- if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
- /*
- * Other functions had installed filters before the
- * workaround was enabled, and they have been reset
- * by firmware.
- */
- EFSYS_PROBE(bug26807_workaround_flr_done);
- /* FIXME: bump MC warm boot count ? */
- }
- } else if (rc == EACCES) {
- /*
- * Unprivileged functions cannot enable the workaround in older
- * firmware.
- */
- encp->enc_bug26807_workaround = B_FALSE;
- } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
- encp->enc_bug26807_workaround = B_FALSE;
- } else {
- goto fail3;
- }
-
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail4;
+ goto fail3;
/*
* The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -215,7 +180,7 @@
encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
- goto fail5;
+ goto fail4;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -223,8 +188,6 @@
return (0);
-fail5:
- EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
fail3:
diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 16621d1..c0d4c13 100644
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -69,9 +69,6 @@
encp->enc_bug41750_workaround = B_TRUE;
}
- /* Chained multicast is always enabled on Medford2 */
- encp->enc_bug26807_workaround = B_TRUE;
-
/*
* If the bug61265 workaround is enabled, then interrupt holdoff timers
* cannot be controlled by timer table writes, so MCDI must be used
diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index 01a3462..c2a0054 100644
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -67,9 +67,6 @@
encp->enc_bug41750_workaround = B_TRUE;
}
- /* Chained multicast is always enabled on Medford */
- encp->enc_bug26807_workaround = B_TRUE;
-
/*
* If the bug61265 workaround is enabled, then interrupt holdoff timers
* cannot be controlled by timer table writes, so MCDI must be used
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 02/29] net/sfc/base: fix signed/unsigned mismatch errors
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 01/29] net/sfc/base: enable chained multicast on all EF10 cards Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 03/29] net/sfc/base: fix shift by more bits than field width Andrew Rybchenko
` (27 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Andrew Lee, stable
From: Andrew Lee <alee@solarflare.com>
Use UINT32_MAX instead of assigning -1 to a uint32_t variable to
resolve "conversion from 'int' to 'uint32_t', signed/unsigned mismatch"
errors produced by the Visual Studio 2017 toolchain [with the default
/W4 /WX C compiler options which set warning level 4 and treat warnings
as errors].
Fixes: 107cf1d792cb ("net/sfc/base: move limits config to ef10 NIC board config")
Cc: stable@dpdk.org
Signed-off-by: Andrew Lee <alee@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 1d7e6d8..052b4ff 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1936,7 +1936,7 @@
encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
- encp->enc_buftbl_limit = 0xFFFFFFFF;
+ encp->enc_buftbl_limit = UINT32_MAX;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 03/29] net/sfc/base: fix shift by more bits than field width
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 01/29] net/sfc/base: enable chained multicast on all EF10 cards Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 02/29] net/sfc/base: fix signed/unsigned mismatch errors Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 04/29] net/sfc/base: improve code style in sensors decoding Andrew Rybchenko
` (26 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Mark Spender, stable
From: Mark Spender <mspender@solarflare.com>
This was probably an oversight when support for multiple sensor pages
was added.
Despite being undefined behaviour in C, it probably worked on Intel
x32/x64 as on them bit shift operations wrap round.
Fixes: dfb3b1ce15f6 ("net/sfc/base: import monitors access via MCDI")
Cc: stable@dpdk.org
Signed-off-by: Mark Spender <mspender@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/mcdi_mon.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/sfc/base/mcdi_mon.c b/drivers/net/sfc/base/mcdi_mon.c
index b53de0d..d0247dc 100644
--- a/drivers/net/sfc/base/mcdi_mon.c
+++ b/drivers/net/sfc/base/mcdi_mon.c
@@ -73,7 +73,8 @@
/* This sensor is one of the page boundary bits. */
}
- if (~(sensor_mask[page]) & (1U << sensor))
+ if (~(sensor_mask[page]) &
+ (1U << (sensor % (sizeof (sensor_mask[page]) * 8))))
continue;
/* This sensor not in DMA buffer */
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 04/29] net/sfc/base: improve code style in sensors decoding
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (2 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 03/29] net/sfc/base: fix shift by more bits than field width Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 05/29] net/sfc/base: do not rely on indirect header inclusion Andrew Rybchenko
` (25 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Mark Spender
From: Mark Spender <mspender@solarflare.com>
Add more comments to simplify code reading and understanding.
Signed-off-by: Mark Spender <mspender@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/mcdi_mon.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/sfc/base/mcdi_mon.c b/drivers/net/sfc/base/mcdi_mon.c
index d0247dc..824d9ca 100644
--- a/drivers/net/sfc/base/mcdi_mon.c
+++ b/drivers/net/sfc/base/mcdi_mon.c
@@ -63,34 +63,34 @@
for (sensor = 0; sensor < sensor_max; ++sensor) {
efx_mon_stat_t id;
efx_mon_stat_portmask_t stat_portmask = 0;
- boolean_t decode_ok;
efx_mon_stat_unit_t stat_unit;
if ((sensor % (MC_CMD_SENSOR_PAGE0_NEXT + 1)) ==
MC_CMD_SENSOR_PAGE0_NEXT) {
+ /* This sensor is one of the page boundary bits. */
page++;
continue;
- /* This sensor is one of the page boundary bits. */
}
if (~(sensor_mask[page]) &
- (1U << (sensor % (sizeof (sensor_mask[page]) * 8))))
+ (1U << (sensor % (sizeof (sensor_mask[page]) * 8)))) {
+ /* This sensor is not supported. */
continue;
- /* This sensor not in DMA buffer */
+ }
+ /* Supported sensor, so it is present in the DMA buffer. */
idx++;
- /*
- * Valid stat in DMA buffer that we need to increment over, even
- * if we couldn't look up the id
- */
- decode_ok = efx_mon_mcdi_to_efx_stat(sensor, &id);
- decode_ok =
- decode_ok && efx_mon_get_stat_portmap(id, &stat_portmask);
+ if ((efx_mon_mcdi_to_efx_stat(sensor, &id) != B_TRUE) ||
+ (efx_mon_get_stat_portmap(id, &stat_portmask) != B_TRUE)){
+ /* The sensor is not known to the driver. */
+ continue;
+ }
- if (!(decode_ok && (stat_portmask & port_mask)))
+ if ((stat_portmask & port_mask) == 0) {
+ /* The sensor is not for this port. */
continue;
- /* Either bad decode, or don't know what port stat is on */
+ }
EFSYS_ASSERT(id < EFX_MON_NSTATS);
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 05/29] net/sfc/base: do not rely on indirect header inclusion
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (3 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 04/29] net/sfc/base: improve code style in sensors decoding Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 06/29] net/sfc/base: add driver version string registration Andrew Rybchenko
` (24 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev
Types defined in efx_types.h are used in efx.h and it is better do
not rely on the header inclusion from somewhere else (typically from
efsys.h).
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/efx.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 293a0e2..8a2bb39 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -9,6 +9,7 @@
#include "efx_annote.h"
#include "efsys.h"
+#include "efx_types.h"
#include "efx_check.h"
#include "efx_phy_ids.h"
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 06/29] net/sfc/base: add driver version string registration
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (4 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 05/29] net/sfc/base: do not rely on indirect header inclusion Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 07/29] net/sfc/base: add capabilities for bundle partition support Andrew Rybchenko
` (23 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Support the registration of a version string by the libefx
client. The string is passed on to the MC in efx_nic_probe
only to allow the MC to advertise the OS driver version in
NC-SI, and the content is considered opaque for libefx.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/efx.h | 13 +++++++++++++
drivers/net/sfc/base/efx_impl.h | 3 +++
drivers/net/sfc/base/efx_mcdi.c | 16 ++++++++++++++--
drivers/net/sfc/base/efx_nic.c | 35 +++++++++++++++++++++++++++++++++++
4 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 8a2bb39..700c998 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1463,6 +1463,19 @@ enum {
__inout efx_nic_t *enp,
__in efx_drv_limits_t *edlp);
+/*
+ * Register the OS driver version string for management agents
+ * (e.g. via NC-SI). The content length is provided (i.e. no
+ * NUL terminator). Use length 0 to indicate no version string
+ * should be advertised. It is valid to set the version string
+ * only before efx_nic_probe() is called.
+ */
+extern __checkReturn efx_rc_t
+efx_nic_set_drv_version(
+ __inout efx_nic_t *enp,
+ __in_ecount(length) char const *verp,
+ __in size_t length);
+
typedef enum efx_nic_region_e {
EFX_REGION_VI, /* Memory BAR UC mapping */
EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index f148c87..b5ac84d 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -647,6 +647,8 @@
#endif
+#define EFX_DRV_VER_MAX 20
+
typedef struct efx_drv_cfg_s {
uint32_t edc_min_vi_count;
uint32_t edc_max_vi_count;
@@ -677,6 +679,7 @@ struct efx_nic_s {
const efx_tx_ops_t *en_etxop;
const efx_rx_ops_t *en_erxop;
efx_fw_variant_t efv;
+ char en_drv_version[EFX_DRV_VER_MAX];
#if EFSYS_OPT_FILTER
efx_filter_t en_filter;
const efx_filter_ops_t *en_efop;
diff --git a/drivers/net/sfc/base/efx_mcdi.c b/drivers/net/sfc/base/efx_mcdi.c
index adc2eb8..584fd4d 100644
--- a/drivers/net/sfc/base/efx_mcdi.c
+++ b/drivers/net/sfc/base/efx_mcdi.c
@@ -1256,13 +1256,17 @@
__in boolean_t attach)
{
efx_mcdi_req_t req;
- EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRV_ATTACH_IN_LEN,
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRV_ATTACH_IN_V2_LEN,
MC_CMD_DRV_ATTACH_EXT_OUT_LEN);
efx_rc_t rc;
req.emr_cmd = MC_CMD_DRV_ATTACH;
req.emr_in_buf = payload;
- req.emr_in_length = MC_CMD_DRV_ATTACH_IN_LEN;
+ if (enp->en_drv_version[0] == '\0') {
+ req.emr_in_length = MC_CMD_DRV_ATTACH_IN_LEN;
+ } else {
+ req.emr_in_length = MC_CMD_DRV_ATTACH_IN_V2_LEN;
+ }
req.emr_out_buf = payload;
req.emr_out_length = MC_CMD_DRV_ATTACH_EXT_OUT_LEN;
@@ -1283,6 +1287,14 @@
MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_UPDATE, 1);
MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_FIRMWARE_ID, enp->efv);
+ if (req.emr_in_length >= MC_CMD_DRV_ATTACH_IN_V2_LEN) {
+ EFX_STATIC_ASSERT(sizeof (enp->en_drv_version) ==
+ MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN);
+ memcpy(MCDI_IN2(req, char, DRV_ATTACH_IN_V2_DRIVER_VERSION),
+ enp->en_drv_version,
+ MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN);
+ }
+
efx_mcdi_execute(enp, &req);
if (req.emr_rc != 0) {
diff --git a/drivers/net/sfc/base/efx_nic.c b/drivers/net/sfc/base/efx_nic.c
index 3ec5cbc..c1285bf 100644
--- a/drivers/net/sfc/base/efx_nic.c
+++ b/drivers/net/sfc/base/efx_nic.c
@@ -380,6 +380,41 @@
}
__checkReturn efx_rc_t
+efx_nic_set_drv_version(
+ __inout efx_nic_t *enp,
+ __in_ecount(length) char const *verp,
+ __in size_t length)
+{
+ efx_rc_t rc;
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
+
+ /*
+ * length is the string content length in bytes.
+ * Accept any content which fits into the version
+ * buffer, excluding the last byte. This is reserved
+ * for an appended NUL terminator.
+ */
+ if (length >= sizeof (enp->en_drv_version)) {
+ rc = E2BIG;
+ goto fail1;
+ }
+
+ (void) memset(enp->en_drv_version, 0,
+ sizeof (enp->en_drv_version));
+ memcpy(enp->en_drv_version, verp, length);
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
+ __checkReturn efx_rc_t
efx_nic_get_bar_region(
__in efx_nic_t *enp,
__in efx_nic_region_t region,
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 07/29] net/sfc/base: add capabilities for bundle partition support
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (5 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 06/29] net/sfc/base: add driver version string registration Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 08/29] net/sfc/base: add extensible NVRAM info function Andrew Rybchenko
` (22 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 8 ++++++++
drivers/net/sfc/base/efx.h | 4 +++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 052b4ff..27508e1 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1217,6 +1217,14 @@
encp->enc_nvram_update_verify_result_supported = B_FALSE;
/*
+ * Check if firmware update via the BUNDLE partition is supported
+ */
+ if (CAP_FLAGS2(req, BUNDLE_UPDATE))
+ encp->enc_nvram_bundle_update_supported = B_TRUE;
+ else
+ encp->enc_nvram_bundle_update_supported = B_FALSE;
+
+ /*
* Check if firmware provides packet memory and Rx datapath
* counters.
*/
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 700c998..879bc8d 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1394,7 +1394,9 @@ enum {
uint32_t enc_required_pcie_bandwidth_mbps;
uint32_t enc_max_pcie_link_gen;
/* Firmware verifies integrity of NVRAM updates */
- uint32_t enc_nvram_update_verify_result_supported;
+ boolean_t enc_nvram_update_verify_result_supported;
+ /* Firmware accepts updates via the BUNDLE partition */
+ boolean_t enc_nvram_bundle_update_supported;
/* Firmware support for extended MAC_STATS buffer */
uint32_t enc_mac_stats_nstats;
boolean_t enc_fec_counters;
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 08/29] net/sfc/base: add extensible NVRAM info function
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (6 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 07/29] net/sfc/base: add capabilities for bundle partition support Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 09/29] net/sfc/base: add NVRAM info to API Andrew Rybchenko
` (21 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Includes the partition read-only flag, to allow for
checks before opening the partition.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/efx.h | 10 ++++++
drivers/net/sfc/base/efx_impl.h | 6 ++++
drivers/net/sfc/base/efx_nvram.c | 66 +++++++++++++++++++++++++++++++---------
3 files changed, 68 insertions(+), 14 deletions(-)
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 879bc8d..a5342af 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1606,6 +1606,16 @@ enum {
EFX_NVRAM_NTYPES,
} efx_nvram_type_t;
+typedef struct efx_nvram_info_s {
+ uint32_t eni_flags;
+ uint32_t eni_partn_size;
+ uint32_t eni_address;
+ uint32_t eni_erase_size;
+ uint32_t eni_write_size;
+} efx_nvram_info_t;
+
+#define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
+
extern __checkReturn efx_rc_t
efx_nvram_init(
__in efx_nic_t *enp);
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index b5ac84d..684403f 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -568,6 +568,12 @@
__out_opt uint32_t *write_sizep);
__checkReturn efx_rc_t
+efx_mcdi_nvram_info_ex(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out efx_nvram_info_t *eni);
+
+ __checkReturn efx_rc_t
efx_mcdi_nvram_update_start(
__in efx_nic_t *enp,
__in uint32_t partn);
diff --git a/drivers/net/sfc/base/efx_nvram.c b/drivers/net/sfc/base/efx_nvram.c
index 5c611c3..df7e851 100644
--- a/drivers/net/sfc/base/efx_nvram.c
+++ b/drivers/net/sfc/base/efx_nvram.c
@@ -657,13 +657,10 @@
}
__checkReturn efx_rc_t
-efx_mcdi_nvram_info(
+efx_mcdi_nvram_info_ex(
__in efx_nic_t *enp,
__in uint32_t partn,
- __out_opt size_t *sizep,
- __out_opt uint32_t *addressp,
- __out_opt uint32_t *erase_sizep,
- __out_opt uint32_t *write_sizep)
+ __out efx_nvram_info_t *enip)
{
EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_INFO_IN_LEN,
MC_CMD_NVRAM_INFO_V2_OUT_LEN);
@@ -690,21 +687,26 @@
goto fail2;
}
- if (sizep)
- *sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE);
+ enip->eni_partn_size = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE);
- if (addressp)
- *addressp = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_PHYSADDR);
+ enip->eni_address = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_PHYSADDR);
- if (erase_sizep)
- *erase_sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE);
+ enip->eni_erase_size = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE);
- if (write_sizep) {
- *write_sizep =
+ enip->eni_write_size =
(req.emr_out_length_used <
MC_CMD_NVRAM_INFO_V2_OUT_LEN) ?
0 : MCDI_OUT_DWORD(req, NVRAM_INFO_V2_OUT_WRITESIZE);
- }
+
+ enip->eni_flags = 0;
+
+ if (MCDI_OUT_DWORD_FIELD(req, NVRAM_INFO_OUT_FLAGS,
+ NVRAM_INFO_OUT_PROTECTED))
+ enip->eni_flags |= EFX_NVRAM_FLAG_READ_ONLY;
+
+ if (MCDI_OUT_DWORD_FIELD(req, NVRAM_INFO_OUT_FLAGS,
+ NVRAM_INFO_OUT_READ_ONLY))
+ enip->eni_flags |= EFX_NVRAM_FLAG_READ_ONLY;
return (0);
@@ -716,6 +718,42 @@
return (rc);
}
+ __checkReturn efx_rc_t
+efx_mcdi_nvram_info(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out_opt size_t *sizep,
+ __out_opt uint32_t *addressp,
+ __out_opt uint32_t *erase_sizep,
+ __out_opt uint32_t *write_sizep)
+{
+ efx_nvram_info_t eni;
+ efx_rc_t rc;
+
+ if ((rc = efx_mcdi_nvram_info_ex(enp, partn, &eni)) != 0)
+ goto fail1;
+
+ if (sizep)
+ *sizep = eni.eni_partn_size;
+
+ if (addressp)
+ *addressp = eni.eni_address;
+
+ if (erase_sizep)
+ *erase_sizep = eni.eni_erase_size;
+
+ if (write_sizep)
+ *write_sizep = eni.eni_write_size;
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
/*
* MC_CMD_NVRAM_UPDATE_START_V2 must be used to support firmware-verified
* NVRAM updates. Older firmware will ignore the flags field in the request.
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 09/29] net/sfc/base: add NVRAM info to API
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (7 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 08/29] net/sfc/base: add extensible NVRAM info function Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 10/29] net/sfc/base: update MCDI headers Andrew Rybchenko
` (20 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Add function to query partition characteristics.
Refactor efx_nvram_size to share implementation.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_impl.h | 6 +++++
drivers/net/sfc/base/ef10_nvram.c | 36 +++++++++++++++++++++--------
drivers/net/sfc/base/efx.h | 6 +++++
drivers/net/sfc/base/efx_impl.h | 3 ++-
drivers/net/sfc/base/efx_nvram.c | 46 +++++++++++++++++++++++++++++++++-----
drivers/net/sfc/base/siena_impl.h | 6 +++++
drivers/net/sfc/base/siena_nvram.c | 23 +++++++++++++++++++
7 files changed, 110 insertions(+), 16 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index fae94fe..0cfbf59 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -452,6 +452,12 @@
__out size_t *sizep);
extern __checkReturn efx_rc_t
+ef10_nvram_partn_info(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out efx_nvram_info_t * enip);
+
+extern __checkReturn efx_rc_t
ef10_nvram_partn_rw_start(
__in efx_nic_t *enp,
__in uint32_t partn,
diff --git a/drivers/net/sfc/base/ef10_nvram.c b/drivers/net/sfc/base/ef10_nvram.c
index 2aed421..a618c75 100644
--- a/drivers/net/sfc/base/ef10_nvram.c
+++ b/drivers/net/sfc/base/ef10_nvram.c
@@ -1960,6 +1960,29 @@ static uint32_t checksum_tlv_partition(
}
__checkReturn efx_rc_t
+ef10_nvram_partn_info(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out efx_nvram_info_t *enip)
+{
+ efx_rc_t rc;
+
+ if ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)
+ goto fail1;
+
+ if (enip->eni_write_size == 0)
+ enip->eni_write_size = EF10_NVRAM_CHUNK;
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
+ __checkReturn efx_rc_t
ef10_nvram_partn_lock(
__in efx_nic_t *enp,
__in uint32_t partn)
@@ -2439,22 +2462,17 @@ static uint32_t checksum_tlv_partition(
__in uint32_t partn,
__out size_t *chunk_sizep)
{
- uint32_t write_size = 0;
+ efx_nvram_info_t eni = { 0 };
efx_rc_t rc;
- if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL,
- NULL, &write_size)) != 0)
+ if ((rc = ef10_nvram_partn_info(enp, partn, &eni)) != 0)
goto fail1;
if ((rc = ef10_nvram_partn_lock(enp, partn)) != 0)
goto fail2;
- if (chunk_sizep != NULL) {
- if (write_size == 0)
- *chunk_sizep = EF10_NVRAM_CHUNK;
- else
- *chunk_sizep = write_size;
- }
+ if (chunk_sizep != NULL)
+ *chunk_sizep = eni.eni_write_size;
return (0);
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index a5342af..4905918 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1635,6 +1635,12 @@ enum {
__out size_t *sizep);
extern __checkReturn efx_rc_t
+efx_nvram_info(
+ __in efx_nic_t *enp,
+ __in efx_nvram_type_t type,
+ __out efx_nvram_info_t *enip);
+
+extern __checkReturn efx_rc_t
efx_nvram_rw_start(
__in efx_nic_t *enp,
__in efx_nvram_type_t type,
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 684403f..577d5aa 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -501,7 +501,8 @@
#endif /* EFSYS_OPT_DIAG */
efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
uint32_t *);
- efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
+ efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t,
+ efx_nvram_info_t *);
efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
unsigned int, caddr_t, size_t);
diff --git a/drivers/net/sfc/base/efx_nvram.c b/drivers/net/sfc/base/efx_nvram.c
index df7e851..b817cb6 100644
--- a/drivers/net/sfc/base/efx_nvram.c
+++ b/drivers/net/sfc/base/efx_nvram.c
@@ -16,7 +16,7 @@
siena_nvram_test, /* envo_test */
#endif /* EFSYS_OPT_DIAG */
siena_nvram_type_to_partn, /* envo_type_to_partn */
- siena_nvram_partn_size, /* envo_partn_size */
+ siena_nvram_partn_info, /* envo_partn_info */
siena_nvram_partn_rw_start, /* envo_partn_rw_start */
siena_nvram_partn_read, /* envo_partn_read */
siena_nvram_partn_read, /* envo_partn_read_backup */
@@ -37,7 +37,7 @@
ef10_nvram_test, /* envo_test */
#endif /* EFSYS_OPT_DIAG */
ef10_nvram_type_to_partn, /* envo_type_to_partn */
- ef10_nvram_partn_size, /* envo_partn_size */
+ ef10_nvram_partn_info, /* envo_partn_info */
ef10_nvram_partn_rw_start, /* envo_partn_rw_start */
ef10_nvram_partn_read, /* envo_partn_read */
ef10_nvram_partn_read_backup, /* envo_partn_read_backup */
@@ -138,6 +138,7 @@
__out size_t *sizep)
{
const efx_nvram_ops_t *envop = enp->en_envop;
+ efx_nvram_info_t eni = { 0 };
uint32_t partn;
efx_rc_t rc;
@@ -147,9 +148,11 @@
if ((rc = envop->envo_type_to_partn(enp, type, &partn)) != 0)
goto fail1;
- if ((rc = envop->envo_partn_size(enp, partn, sizep)) != 0)
+ if ((rc = envop->envo_partn_info(enp, partn, &eni)) != 0)
goto fail2;
+ *sizep = eni.eni_partn_size;
+
return (0);
fail2:
@@ -161,6 +164,36 @@
return (rc);
}
+extern __checkReturn efx_rc_t
+efx_nvram_info(
+ __in efx_nic_t *enp,
+ __in efx_nvram_type_t type,
+ __out efx_nvram_info_t *enip)
+{
+ const efx_nvram_ops_t *envop = enp->en_envop;
+ uint32_t partn;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM);
+
+ if ((rc = envop->envo_type_to_partn(enp, type, &partn)) != 0)
+ goto fail1;
+
+ if ((rc = envop->envo_partn_info(enp, partn, enip)) != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
__checkReturn efx_rc_t
efx_nvram_get_version(
__in efx_nic_t *enp,
@@ -305,7 +338,7 @@
{
const efx_nvram_ops_t *envop = enp->en_envop;
unsigned int offset = 0;
- size_t size = 0;
+ efx_nvram_info_t eni = { 0 };
uint32_t partn;
efx_rc_t rc;
@@ -317,10 +350,11 @@
EFSYS_ASSERT3U(enp->en_nvram_partn_locked, ==, partn);
- if ((rc = envop->envo_partn_size(enp, partn, &size)) != 0)
+ if ((rc = envop->envo_partn_info(enp, partn, &eni)) != 0)
goto fail2;
- if ((rc = envop->envo_partn_erase(enp, partn, offset, size)) != 0)
+ if ((rc = envop->envo_partn_erase(enp, partn, offset,
+ eni.eni_partn_size)) != 0)
goto fail3;
return (0);
diff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h
index 1adb8a4..38d0289 100644
--- a/drivers/net/sfc/base/siena_impl.h
+++ b/drivers/net/sfc/base/siena_impl.h
@@ -192,6 +192,12 @@
__out size_t *sizep);
extern __checkReturn efx_rc_t
+siena_nvram_partn_info(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out efx_nvram_info_t * enip);
+
+extern __checkReturn efx_rc_t
siena_nvram_partn_rw_start(
__in efx_nic_t *enp,
__in uint32_t partn,
diff --git a/drivers/net/sfc/base/siena_nvram.c b/drivers/net/sfc/base/siena_nvram.c
index b8ea8a7..7d423d2 100644
--- a/drivers/net/sfc/base/siena_nvram.c
+++ b/drivers/net/sfc/base/siena_nvram.c
@@ -40,6 +40,29 @@
}
__checkReturn efx_rc_t
+siena_nvram_partn_info(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out efx_nvram_info_t * enip)
+{
+ efx_rc_t rc;
+
+ if ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)
+ goto fail1;
+
+ if (enip->eni_write_size == 0)
+ enip->eni_write_size = SIENA_NVRAM_CHUNK;
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
+ __checkReturn efx_rc_t
siena_nvram_partn_lock(
__in efx_nic_t *enp,
__in uint32_t partn)
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 10/29] net/sfc/base: update MCDI headers
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (8 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 09/29] net/sfc/base: add NVRAM info to API Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 11/29] net/sfc/base: add firmware ID header Andrew Rybchenko
` (19 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/efx_regs_mcdi.h | 1667 ++++++++++++++++++++++++++++-
drivers/net/sfc/base/efx_regs_mcdi_aoe.h | 13 +
drivers/net/sfc/base/efx_regs_mcdi_strs.h | 174 +--
3 files changed, 1751 insertions(+), 103 deletions(-)
diff --git a/drivers/net/sfc/base/efx_regs_mcdi.h b/drivers/net/sfc/base/efx_regs_mcdi.h
index bc44602..122a320 100644
--- a/drivers/net/sfc/base/efx_regs_mcdi.h
+++ b/drivers/net/sfc/base/efx_regs_mcdi.h
@@ -725,6 +725,18 @@
* a module change.
*/
#define MCDI_EVENT_CODE_MODULECHANGE 0x21
+/* enum: Notification that the sensors have been added and/or removed from the
+ * sensor table. This event includes the new sensor table generation count, if
+ * this does not match the driver's local copy it is expected to call
+ * DYNAMIC_SENSORS_LIST to refresh it.
+ */
+#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
+/* enum: Notification that a sensor has changed state as a result of a reading
+ * crossing a threshold. This is sent as two events, the first event contains
+ * the handle and the sensor's state (in the SRC field), and the second
+ * contains the value.
+ */
+#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
/* enum: Artificial event generated by host and posted via MC for test
* purposes.
*/
@@ -858,6 +870,24 @@
#define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
#define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
#define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32
+/* The new generation count after a sensor has been added or deleted. */
+#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
+#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
+#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
+#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32
+/* The handle of a dynamic sensor. */
+#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
+#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
+#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
+#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32
+/* The current values of a sensor. */
+#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
+#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
+#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
+#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32
+/* The current state of a sensor. */
+#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36
+#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8
/* FCDI_EVENT structuredef */
#define FCDI_EVENT_LEN 8
@@ -967,6 +997,7 @@
#define FCDI_EXTENDED_EVENT_PPS_LENMAX 248
#define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016
#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
/* Number of timestamps following */
#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
#define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
@@ -1107,6 +1138,7 @@
#define MC_CMD_READ32_OUT_LENMAX 252
#define MC_CMD_READ32_OUT_LENMAX_MCDI2 1020
#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_READ32_OUT_BUFFER_OFST 0
#define MC_CMD_READ32_OUT_BUFFER_LEN 4
#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
@@ -1128,6 +1160,7 @@
#define MC_CMD_WRITE32_IN_LENMAX 252
#define MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020
#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
+#define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
#define MC_CMD_WRITE32_IN_ADDR_OFST 0
#define MC_CMD_WRITE32_IN_ADDR_LEN 4
#define MC_CMD_WRITE32_IN_BUFFER_OFST 4
@@ -1296,6 +1329,104 @@
#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
+/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs
+ * found on Riverhead designs
+ */
+#define MC_CMD_GET_ASSERTS_OUT_V2_LEN 240
+/* Assertion status flag. */
+#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
+#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
+/* enum: No assertions have failed. */
+/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
+/* enum: A system-level assertion has failed. */
+/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
+/* enum: A thread-level assertion has failed. */
+/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
+/* enum: The system was reset by the watchdog. */
+/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
+/* enum: An illegal address trap stopped the system (huntington and later) */
+/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
+/* Failing PC value */
+#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
+#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
+/* Saved GP regs */
+#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8
+#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31
+/* enum: A magic value hinting that the value in this register at the time of
+ * the failure has likely been lost.
+ */
+/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
+/* Failing thread address */
+#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132
+#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136
+#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
+/* Saved Special Function Registers */
+#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136
+#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26
+
+/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted
+ * firmware version information
+ */
+#define MC_CMD_GET_ASSERTS_OUT_V3_LEN 360
+/* Assertion status flag. */
+#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
+#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
+/* enum: No assertions have failed. */
+/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
+/* enum: A system-level assertion has failed. */
+/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
+/* enum: A thread-level assertion has failed. */
+/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
+/* enum: The system was reset by the watchdog. */
+/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
+/* enum: An illegal address trap stopped the system (huntington and later) */
+/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
+/* Failing PC value */
+#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
+/* Saved GP regs */
+#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8
+#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31
+/* enum: A magic value hinting that the value in this register at the time of
+ * the failure has likely been lost.
+ */
+/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
+/* Failing thread address */
+#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132
+#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136
+#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
+/* Saved Special Function Registers */
+#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136
+#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20
+/* MC firmware build date (as Unix timestamp) */
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
+/* MC firmware version number */
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
+/* MC firmware security level */
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
+/* MC firmware extra version info (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64
+
/***********************************/
/* MC_CMD_LOG_CTRL
@@ -1326,7 +1457,7 @@
/***********************************/
/* MC_CMD_GET_VERSION
- * Get version information about the MC firmware.
+ * Get version information about adapter components.
*/
#define MC_CMD_GET_VERSION 0x8
#undef MC_CMD_0x8_PRIVILEGE_CTG
@@ -1390,6 +1521,95 @@
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
+/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version
+ * information for all adapter components. For Riverhead based designs, base MC
+ * firmware version fields refer to NMC firmware, while CMC firmware data is in
+ * dedicated CMC fields. Flags indicate which data is present in the response
+ * (depending on which components exist on a particular adapter)
+ */
+#define MC_CMD_GET_VERSION_V2_OUT_LEN 304
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
+/* extra info */
+#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
+
/***********************************/
/* MC_CMD_PTP
@@ -1524,6 +1744,7 @@
#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
#define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020
#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
+#define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
/* MC_CMD_PTP_IN_CMD_OFST 0 */
/* MC_CMD_PTP_IN_CMD_LEN 4 */
/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
@@ -1691,6 +1912,7 @@
#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020
#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
+#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
/* MC_CMD_PTP_IN_CMD_OFST 0 */
/* MC_CMD_PTP_IN_CMD_LEN 4 */
/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
@@ -2034,6 +2256,7 @@
#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020
#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
+#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
/* A set of host and NIC times */
#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
@@ -2118,6 +2341,7 @@
#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020
#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
+#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
@@ -2258,6 +2482,7 @@
#define MC_CMD_CSR_READ32_OUT_LENMAX 252
#define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020
#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
/* The last dword is the status, not a value read */
#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
@@ -2280,6 +2505,7 @@
#define MC_CMD_CSR_WRITE32_IN_LENMAX 252
#define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020
#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
+#define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
/* Address */
#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
#define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
@@ -2362,6 +2588,7 @@
#define MC_CMD_STACKINFO_OUT_LENMAX 252
#define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020
#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
+#define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
/* (thread ptr, stack size, free space) for each thread in system */
#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
@@ -2480,6 +2707,7 @@
#define MC_CMD_DBI_WRITE_IN_LENMAX 252
#define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020
#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
+#define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
* 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
*/
@@ -2649,6 +2877,7 @@
#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136
#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
+#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
@@ -2720,6 +2949,7 @@
#define MC_CMD_DBI_READX_IN_LENMAX 248
#define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016
#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
+#define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
/* Each Read op consists of an address (offset 0), VF/CS2) */
#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
@@ -2734,6 +2964,7 @@
#define MC_CMD_DBI_READX_OUT_LENMAX 252
#define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020
#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
/* Value */
#define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
#define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
@@ -2792,6 +3023,7 @@
#define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
#define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020
#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
/* variable number of LTSSM values, as bytes. The history is read-to-clear. */
#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
@@ -2835,6 +3067,8 @@
#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
+#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5
+#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
/* 1 to set new state, or 0 to just report the existing state */
#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
@@ -2895,6 +3129,8 @@
#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
+#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5
+#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
/* 1 to set new state, or 0 to just report the existing state */
#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
@@ -2968,11 +3204,13 @@
* input.
*/
#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
-/* enum: If set, indicates that VI spreading is inhibited on RX. See
- * description of WANT_RX_VI_SPREADING_INHIBIT above. It is an error to set
- * this flag without also setting FLAG_VI_SPREADING_ENABLED.
- */
+/* enum: Used during development only. Should no longer be used. */
#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
+/* enum: If set, indicates that TX only spreading is enabled. Even-numbered
+ * TXQs will use one engine, and odd-numbered TXQs will use the other. This
+ * also has the effect that only even-numbered RXQs will receive traffic.
+ */
+#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
/***********************************/
@@ -3140,6 +3378,7 @@
#define MC_CMD_PUTS_IN_LENMAX 252
#define MC_CMD_PUTS_IN_LENMAX_MCDI2 1020
#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
+#define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
#define MC_CMD_PUTS_IN_DEST_OFST 0
#define MC_CMD_PUTS_IN_DEST_LEN 4
#define MC_CMD_PUTS_IN_UART_LBN 0
@@ -3507,6 +3746,7 @@
#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020
#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
+#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
@@ -4699,6 +4939,7 @@
#define MC_CMD_MEMCPY_IN_LENMAX 224
#define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992
#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
+#define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
#define MC_CMD_MEMCPY_IN_RECORD_OFST 0
#define MC_CMD_MEMCPY_IN_RECORD_LEN 32
@@ -5127,6 +5368,7 @@
#define MC_CMD_NVRAM_READ_OUT_LENMAX 252
#define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020
#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
+#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
@@ -5150,6 +5392,7 @@
#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
#define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020
#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
+#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
/* Enum values, see field(s): */
@@ -5236,6 +5479,10 @@
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
* response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
@@ -5258,7 +5505,10 @@
* has completed.
*/
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
-/* Result of nvram update completion processing */
+/* Result of nvram update completion processing. Result codes that indicate an
+ * internal build failure and therefore not expected to be seen by customers in
+ * the field are marked with a prefix 'Internal-error'.
+ */
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
/* enum: Invalid return code; only non-zero values are defined. Defined as
@@ -5297,6 +5547,51 @@
#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
/* enum: The image has a lower security level than the current firmware. */
#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
+/* enum: Internal-error. The signed image is missing the 'contents' section,
+ * where the 'contents' section holds the actual image payload to be applied.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
+/* enum: Internal-error. The bundle header is invalid. */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
+/* enum: Internal-error. The bundle does not have a valid reflash image layout.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
+/* enum: Internal-error. The bundle has an inconsistent layout of components or
+ * incorrect checksum.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
+/* enum: Internal-error. The bundle manifest is inconsistent with components in
+ * the bundle.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
+/* enum: Internal-error. The number of components in a bundle do not match the
+ * number of components advertised by the bundle manifest.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
+/* enum: Internal-error. The bundle contains too many components for the MC
+ * firmware to process
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
+/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
+ * component.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
+/* enum: Internal-error. The hash of a component does not match the hash stored
+ * in the bundle manifest.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
+/* enum: Internal-error. Component hash calculation failed. */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
+/* enum: Internal-error. The component does not have a valid reflash image
+ * layout.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
+/* enum: The bundle processing code failed to copy a component to its target
+ * partition.
+ */
+#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
+/* enum: The update operation is in-progress. */
+#define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
/***********************************/
@@ -5351,6 +5646,7 @@
#define MC_CMD_SCHEDINFO_OUT_LENMAX 252
#define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020
#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
@@ -5460,6 +5756,7 @@
#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
#define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020
#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
+#define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
/* enum: Controller temperature: degC */
@@ -5668,6 +5965,7 @@
#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020
#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
+#define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
/* Enum values, see field(s): */
@@ -5869,6 +6167,7 @@
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
+#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
@@ -6065,6 +6364,7 @@
#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020
#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
+#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
/* in bytes */
#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
@@ -6219,6 +6519,7 @@
#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020
#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
+#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
/* total number of partitions */
#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
@@ -6251,6 +6552,7 @@
#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
#define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020
#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
+#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
/* Partition type ID code */
#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
@@ -6520,6 +6822,7 @@
#define MC_CMD_MUM_IN_WRITE_LENMAX 252
#define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
+#define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
/* MUM cmd header */
/* MC_CMD_MUM_IN_CMD_OFST 0 */
/* MC_CMD_MUM_IN_CMD_LEN 4 */
@@ -6543,6 +6846,7 @@
#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
#define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020
#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
+#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
/* MUM cmd header */
/* MC_CMD_MUM_IN_CMD_OFST 0 */
/* MC_CMD_MUM_IN_CMD_LEN 4 */
@@ -6849,6 +7153,7 @@
#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020
#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
+#define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
/* returned data */
#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
@@ -6861,6 +7166,7 @@
#define MC_CMD_MUM_OUT_READ_LENMAX 252
#define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020
#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
+#define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
@@ -6926,6 +7232,7 @@
#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020
#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
+#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
@@ -6975,6 +7282,7 @@
#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020
#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
+#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
/* in bytes */
#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
@@ -7001,6 +7309,7 @@
#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016
#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
/* Discrete (soldered) DDR resistor strap info */
#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
@@ -7063,6 +7372,311 @@
#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
+/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This
+ * should match the equivalent structure in the sensor_query SPHINX service.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24
+/* A value below this will trigger a warning event. */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32
+/* A value below this will trigger a critical event. */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32
+/* A value below this will shut down the card. */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32
+/* A value above this will trigger a warning event. */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32
+/* A value above this will trigger a critical event. */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32
+/* A value above this will shut down the card. */
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160
+#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32
+
+/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.
+ * This should match the equivalent structure in the sensor_query SPHINX
+ * service.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64
+/* The handle used to identify the sensor in calls to
+ * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
+ */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32
+/* A human-readable name for the sensor (zero terminated string, max 32 bytes)
+ */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256
+/* The type of the sensor device, and by implication the unit of that the
+ * values will be reported in
+ */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
+/* enum: A voltage sensor. Unit is mV */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
+/* enum: A current sensor. Unit is mA */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
+/* enum: A power sensor. Unit is mW */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
+/* enum: A temperature sensor. Unit is Celsius */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
+/* enum: A cooling fan sensor. Unit is RPM */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32
+/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320
+#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192
+
+/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.
+ * This should match the equivalent structure in the sensor_query SPHINX
+ * service.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_READING_LEN 12
+/* The handle used to identify the sensor */
+#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
+#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32
+/* The current value of the sensor */
+#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
+#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32
+#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32
+/* The sensor's condition, e.g. good, broken or removed */
+#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8
+#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
+/* enum: Sensor working normally within limits */
+#define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
+/* enum: Warning threshold breached */
+#define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
+/* enum: Critical threshold breached */
+#define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
+/* enum: Fatal threshold breached */
+#define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
+/* enum: Sensor not working */
+#define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
+/* enum: Sensor working but no reading available */
+#define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
+/* enum: Sensor initialization failed */
+#define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
+#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64
+#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_DYNAMIC_SENSORS_LIST
+ * Return a complete list of handles for sensors currently managed by the MC,
+ * and a generation count for this version of the sensor table. On systems
+ * advertising the DYNAMIC_SENSORS capability bit, this replaces the
+ * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
+ * added by the NMC.
+ *
+ * Sensor handles are persistent for the lifetime of the sensor and are used to
+ * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and
+ * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.
+ *
+ * The generation count is maintained by the MC, is persistent across reboots
+ * and will be incremented each time the sensor table is modified. When the
+ * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated
+ * containing the new generation count. The driver should compare this against
+ * the current generation count, and if it is different, call
+ * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.
+ *
+ * The sensor count is provided to allow a future path to supporting more than
+ * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.
+ * the maximum number that will fit in a single response. As this is a fairly
+ * large number (253) it is not anticipated that this will be needed in the
+ * near future, so can currently be ignored.
+ *
+ * On Riverhead this command is implemented as a a wrapper for `list` in the
+ * sensor_query SPHINX service.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
+#undef MC_CMD_0x66_PRIVILEGE_CTG
+
+#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */
+#define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
+
+/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
+/* Generation count, which will be updated each time a sensor is added to or
+ * removed from the MC sensor table.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
+/* Number of sensors managed by the MC. Note that in principle, this can be
+ * larger than the size of the HANDLES array.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
+/* Array of sensor handles */
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61
+#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253
+
+
+/***********************************/
+/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
+ * Get descriptions for a set of sensors, specified as an array of sensor
+ * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST
+ *
+ * Any handles which do not correspond to a sensor currently managed by the MC
+ * will be dropped from from the response. This may happen when a sensor table
+ * update is in progress, and effectively means the set of usable sensors is
+ * the intersection between the sets of sensors known to the driver and the MC.
+ *
+ * On Riverhead this command is implemented as a a wrapper for
+ * `get_descriptions` in the sensor_query SPHINX service.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
+#undef MC_CMD_0x67_PRIVILEGE_CTG
+
+#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
+/* Array of sensor handles */
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255
+
+/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
+/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15
+
+
+/***********************************/
+/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS
+ * Read the state and value for a set of sensors, specified as an array of
+ * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.
+ *
+ * In the case of a broken sensor, then the state of the response's
+ * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value
+ * provided should be treated as erroneous.
+ *
+ * Any handles which do not correspond to a sensor currently managed by the MC
+ * will be dropped from from the response. This may happen when a sensor table
+ * update is in progress, and effectively means the set of usable sensors is
+ * the intersection between the sets of sensors known to the driver and the MC.
+ *
+ * On Riverhead this command is implemented as a a wrapper for `get_readings`
+ * in the sensor_query SPHINX service.
+ */
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
+#undef MC_CMD_0x68_PRIVILEGE_CTG
+
+#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
+/* Array of sensor handles */
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255
+
+/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
+/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85
+
+
+/***********************************/
+/* MC_CMD_EVENT_CTRL
+ * Configure which categories of unsolicited events the driver expects to
+ * receive (Riverhead).
+ */
+#define MC_CMD_EVENT_CTRL 0x69
+#undef MC_CMD_0x69_PRIVILEGE_CTG
+
+#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EVENT_CTRL_IN msgrequest */
+#define MC_CMD_EVENT_CTRL_IN_LENMIN 0
+#define MC_CMD_EVENT_CTRL_IN_LENMAX 252
+#define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020
+#define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
+#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
+/* Array of event categories for which the driver wishes to receive events. */
+#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
+#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
+#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
+#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63
+#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255
+/* enum: Driver wishes to receive LINKCHANGE events. */
+#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
+/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.
+ */
+#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
+/* enum: Driver wishes to receive receive errors. */
+#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
+/* enum: Driver wishes to receive transmit errors. */
+#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
+/* enum: Driver wishes to receive firmware alerts. */
+#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
+/* enum: Driver wishes to receive reboot events. */
+#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
+
+/* MC_CMD_EVENT_CTRL_OUT msgrequest */
+#define MC_CMD_EVENT_CTRL_OUT_LEN 0
+
/* MC_CMD_RESOURCE_SPECIFIER enum */
/* enum: Any */
#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
@@ -7229,6 +7843,8 @@
#define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
/* enum: Bundle update non-volatile log output partition */
#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
+/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
+#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
/* enum: Start of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
/* enum: End of reserved value range (firmware may use for any purpose) */
@@ -7529,6 +8145,7 @@
#define MC_CMD_INIT_EVQ_IN_LENMAX 548
#define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 548
#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
/* Size, in entries */
#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
@@ -7614,6 +8231,7 @@
#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
#define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 548
#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
/* Size, in entries */
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
@@ -7764,6 +8382,7 @@
#define MC_CMD_INIT_RXQ_IN_LENMAX 252
#define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020
#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
/* Size, in entries */
#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
@@ -8136,6 +8755,139 @@
#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560
#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
+/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a
+ * different RX packet prefix
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_LEN 568
+/* Size, in entries */
+#define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
+#define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
+/* The EVQ to send events to. This is an index originally specified to
+ * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
+#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
+/* The value to put in the event data. Check hardware spec. for valid range.
+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
+ * == PACKED_STREAM.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
+#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
+/* Desired instance. Must be set to a specific instance, which is a function
+ * local queue index.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
+#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
+/* There will be more flags here. */
+#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16
+#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3
+#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
+/* enum: One packet per descriptor (for normal networking) */
+#define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
+/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
+#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
+/* enum: Pack multiple packets into large descriptors using the format designed
+ * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
+ * multiple fixed-size packet buffers within each bucket. For a full
+ * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
+ * firmware.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
+/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
+#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
+#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
+#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
+#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
+#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
+#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
+#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
+#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
+/* Owner ID to use if in buffer mode (zero if physical) */
+#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
+#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
+/* The port ID associated with the v-adaptor which should contain this DMAQ. */
+#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24
+#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
+/* 64-bit address of 4k of 4k-aligned host memory buffer */
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64
+/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
+#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
+#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
+/* The number of packet buffers that will be contained within each
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
+ * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
+#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
+/* The length in bytes of the area in each packet buffer that can be written to
+ * by the adapter. This is used to store the packet prefix and the packet
+ * payload. This length does not include any end padding added by the driver.
+ * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548
+#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
+/* The length in bytes of a single packet buffer within a
+ * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552
+#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
+/* The maximum time in nanoseconds that the datapath will be backpressured if
+ * there are no RX descriptors available. If the timeout is reached and there
+ * are still no descriptors then the packet will be dropped. A timeout of 0
+ * means the datapath will never be blocked. This field is ignored unless
+ * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
+#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
+/* V4 message data */
+#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560
+#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
+/* Size in bytes of buffers attached to descriptors posted to this queue. Set
+ * to zero if using this message on non-QDMA based platforms. Currently in
+ * Riverhead there is a global limit of eight different buffer sizes across all
+ * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
+ * request for a different buffer size will fail if there are already eight
+ * other buffer sizes in use. In future Riverhead this limit will go away and
+ * any size will be accepted.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560
+#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
+/* Prefix id for the RX prefix format to use on packets delivered this queue.
+ * Zero is always a valid prefix id and means the default prefix format
+ * documented for the platform. Other prefix ids can be obtained by calling
+ * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.
+ */
+#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564
+#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
+
/* MC_CMD_INIT_RXQ_OUT msgresponse */
#define MC_CMD_INIT_RXQ_OUT_LEN 0
@@ -8148,6 +8900,9 @@
/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */
#define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
+/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */
+#define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
+
/***********************************/
/* MC_CMD_INIT_TXQ
@@ -8164,6 +8919,7 @@
#define MC_CMD_INIT_TXQ_IN_LENMAX 252
#define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 1020
#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
/* Size, in entries */
#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
@@ -8633,6 +9389,7 @@
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 268
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
/* ID */
@@ -9413,6 +10170,7 @@
#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020
#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
+#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
/* identifies the type of operation requested */
#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
@@ -10192,6 +10950,7 @@
#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX_MCDI2 1020
#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
+#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)
/* Download phase. (Note: the IDLE phase is used internally and is never valid
* in a command from the host.)
*/
@@ -10798,8 +11557,14 @@
#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28
#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
- * on older firmware (check the length).
+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29
+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30
+#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
*/
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
@@ -11133,8 +11898,14 @@
#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28
#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
- * on older firmware (check the length).
+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29
+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30
+#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
*/
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
@@ -11493,8 +12264,14 @@
#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28
#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
- * on older firmware (check the length).
+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29
+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30
+#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
*/
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
@@ -11861,8 +12638,14 @@
#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28
#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
-/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
- * on older firmware (check the length).
+#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29
+#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30
+#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
*/
#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
@@ -11955,6 +12738,396 @@
#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80
#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
+/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 148
+/* First word of flags. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
+/* RxDPCPU firmware id. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 2
+/* enum: Standard RXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
+/* enum: Low latency RXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
+/* enum: Packed stream RXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
+/* enum: Rules engine RXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
+/* enum: DPDK RXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
+/* enum: BIST RXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
+/* enum: RXDP Test firmware image 1 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
+/* enum: RXDP Test firmware image 2 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
+/* enum: RXDP Test firmware image 3 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
+/* enum: RXDP Test firmware image 4 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
+/* enum: RXDP Test firmware image 5 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
+/* enum: RXDP Test firmware image 6 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
+/* enum: RXDP Test firmware image 7 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
+/* enum: RXDP Test firmware image 8 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
+/* enum: RXDP Test firmware image 9 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
+/* enum: RXDP Test firmware image 10 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
+/* TxDPCPU firmware id. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 6
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 2
+/* enum: Standard TXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
+/* enum: Low latency TXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
+/* enum: High packet rate TXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
+/* enum: Rules engine TXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
+/* enum: DPDK TXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
+/* enum: BIST TXDP firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
+/* enum: TXDP Test firmware image 1 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
+/* enum: TXDP Test firmware image 2 */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
+/* enum: TXDP CSR bus test firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial RX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: RX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured RX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant RX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+/* enum: Low latency RX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
+/* enum: Packed stream RX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
+/* enum: RX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine RX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK RX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* enum: RX PD firmware parsing but not filtering network overlay tunnel
+ * encapsulations (Medford development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
+/* enum: reserved value - do not use (may indicate alternative interpretation
+ * of REV field in future)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
+/* enum: Trivial TX PD firmware for early Huntington development (Huntington
+ * development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
+/* enum: TX PD firmware with approximately Siena-compatible behaviour
+ * (Huntington development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
+/* enum: Full featured TX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
+/* enum: (deprecated original name for the FULL_FEATURED variant) */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
+/* enum: siena_compat variant TX PD firmware using PM rather than MAC
+ * (Huntington development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
+/* enum: TX PD firmware handling layer 2 only for high packet rate performance
+ * tests (Medford development only)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
+/* enum: Rules engine TX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
+/* enum: DPDK TX PD production firmware */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
+/* Hardware capabilities of NIC */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
+/* Licensed capabilities */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 16
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
+/* Second word of flags. Not present on older firmware (check the length). */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
+/* Number of FATSOv2 contexts per datapath supported by this NIC (when
+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
+/* One byte per PF containing the number of the external port assigned to this
+ * PF, indexed by PF number. Special values indicate that a PF is either not
+ * present or not assigned.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
+/* enum: PF does not exist. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
+/* enum: PF does exist but is not assigned to any external port. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
+/* enum: This value indicates that PF is assigned, but it cannot be expressed
+ * in this field. It is intended for a possible future situation where a more
+ * complex scheme of PFs to ports mapping is being used. The future driver
+ * should look for a new field supporting the new scheme. The current/old
+ * driver should treat this value as PF_NOT_ASSIGNED.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
+/* One byte per PF containing the number of its VFs, indexed by PF number. A
+ * special value indicates that a PF is not present.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 42
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 16
+/* enum: The caller is not permitted to access information on this PF. */
+/* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
+/* enum: PF does not exist. */
+/* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
+/* Number of VIs available for each external port */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
+/* Size of RX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ RX_DESC_CACHE_SIZE)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 66
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
+/* Size of TX descriptor cache expressed as binary logarithm The actual size
+ * equals (2 ^ TX_DESC_CACHE_SIZE)
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 67
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
+/* Total number of available PIO buffers */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 68
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 2
+/* Size of a single PIO buffer */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 70
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 2
+/* On chips later than Medford the amount of address space assigned to each VI
+ * is configurable. This is a global setting that the driver must query to
+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
+ * with 8k VI windows.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 72
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
+ * CTPIO is not mapped.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
+/* Number of buffers per adapter that can be used for VFIFO Stuffing
+ * (SF-115995-SW) in the present configuration of firmware and port mode.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
+/* Entry count in the MAC stats array, including the final GENERATION_END
+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
+ * hold at least this many 64-bit stats values, if they wish to receive all
+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
+ * stats array returned will be truncated.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 76
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 2
+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 80
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
+ * they create an RX queue. Due to hardware limitations, only a small number of
+ * different buffer sizes may be available concurrently. Nonzero entries in
+ * this array are the sizes of buffers which the system guarantees will be
+ * available for use. If the list is empty, there are no limitations on
+ * concurrent buffer sizes.
+ */
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
+
/***********************************/
/* MC_CMD_V2_EXTN
@@ -13071,6 +14244,7 @@
#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1018
#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
+#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
/* The number of MAC addresses returned */
#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
@@ -13187,6 +14361,7 @@
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX_MCDI2 1020
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
+#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
/* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
@@ -13523,6 +14698,7 @@
#define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
#define MC_CMD_CAP_BLK_READ_OUT_LENMAX_MCDI2 1016
#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
@@ -13761,6 +14937,7 @@
#define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
#define MC_CMD_UART_SEND_DATA_OUT_LENMAX_MCDI2 1020
#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
+#define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1)
/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
@@ -13813,6 +14990,7 @@
#define MC_CMD_UART_RECV_DATA_IN_LENMAX 252
#define MC_CMD_UART_RECV_DATA_IN_LENMAX_MCDI2 1020
#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
+#define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1)
/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
@@ -13855,6 +15033,7 @@
#define MC_CMD_READ_FUSES_OUT_LENMAX 252
#define MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 1020
#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
+#define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
/* Length of returned OTP data in bytes */
#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
#define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
@@ -13880,6 +15059,7 @@
#define MC_CMD_KR_TUNE_IN_LENMAX 252
#define MC_CMD_KR_TUNE_IN_LENMAX_MCDI2 1020
#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
+#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
/* Requested operation */
#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
@@ -13935,6 +15115,7 @@
#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
/* RXEQ Parameter */
#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
@@ -14088,6 +15269,7 @@
#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
+#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
/* Requested operation */
#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
@@ -14134,6 +15316,7 @@
#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
/* TXEQ Parameter */
#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
@@ -14199,6 +15382,7 @@
#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX_MCDI2 1020
#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
+#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
/* Requested operation */
#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
@@ -14288,6 +15472,7 @@
#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
+#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
@@ -14404,6 +15589,7 @@
#define MC_CMD_PCIE_TUNE_IN_LENMAX 252
#define MC_CMD_PCIE_TUNE_IN_LENMAX_MCDI2 1020
#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
+#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4)
/* Requested operation */
#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
@@ -14451,6 +15637,7 @@
#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
/* RXEQ Parameter */
#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
@@ -14512,6 +15699,7 @@
#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
+#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
/* Requested operation */
#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
@@ -14558,6 +15746,7 @@
#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
/* RXEQ Parameter */
#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
@@ -14613,6 +15802,7 @@
#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
+#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
@@ -14770,6 +15960,7 @@
#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 1020
#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
+#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
/* type of license (eg 3) */
#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
@@ -14906,6 +16097,7 @@
#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
#define MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 1020
#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
+#define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
/* application ID */
#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
@@ -14928,6 +16120,7 @@
#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 1020
#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
/* result specific to this particular operation */
#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
@@ -15219,6 +16412,7 @@
#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 1020
#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
+#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
/* the type of configuration setting to change */
#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
@@ -15276,6 +16470,7 @@
#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 1020
#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
+#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
/* current value: the details depend on the type of configuration setting being
* read
*/
@@ -15833,6 +17028,7 @@
#define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
#define MC_CMD_XPM_READ_BYTES_OUT_LENMAX_MCDI2 1020
#define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
+#define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
/* Data */
#define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
#define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
@@ -15855,6 +17051,7 @@
#define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
#define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX_MCDI2 1020
#define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
+#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1)
/* Start address (byte) */
#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
@@ -15895,6 +17092,7 @@
#define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
#define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX_MCDI2 36
#define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
+#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1)
/* Sector type */
#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
@@ -15925,6 +17123,7 @@
#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX_MCDI2 44
#define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
+#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1)
/* If writing fails due to an uncorrectable error, try up to RETRIES following
* sectors (or until no more space available). If 0, only one write attempt is
* made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
@@ -15998,6 +17197,7 @@
#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX_MCDI2 1020
#define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
+#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2)
/* Total number of bad (non-blank) locations */
#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
@@ -16346,6 +17546,7 @@
#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252
#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX_MCDI2 1020
#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num))
+#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_NUM(len) (((len)-0)/1)
/* Opaque hash value; length may vary depending on the hash scheme used */
#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0
#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1
@@ -16378,6 +17579,7 @@
#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252
#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX_MCDI2 1020
#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num))
+#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-4)/4)
/* the number of new counter IDs allocated (may be less than the number
* requested if resources are unavailable)
*/
@@ -16409,6 +17611,7 @@
#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252
#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX_MCDI2 1020
#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
+#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_NUM(len) (((len)-4)/4)
/* the number of counter IDs to free */
#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0
#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_LEN 4
@@ -16443,6 +17646,7 @@
#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252
#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX_MCDI2 1020
#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num))
+#define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_NUM(len) (((len)-4)/2)
/* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */
#define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0
#define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_LEN 4
@@ -16497,6 +17701,7 @@
#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252
#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX_MCDI2 1020
#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
+#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_NUM(len) (((len)-0)/4)
/* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a
* PORTRANGE_TREE_ENTRY
*/
@@ -16530,6 +17735,7 @@
#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252
#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX_MCDI2 1020
#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
+#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_NUM(len) (((len)-0)/4)
/* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a
* PORTRANGE_TREE_ENTRY
*/
@@ -16582,6 +17788,7 @@
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 68
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
+#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
/* Flags */
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
@@ -16726,6 +17933,7 @@
#define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252
#define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX_MCDI2 1020
#define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num))
+#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_NUM(len) (((len)-4)/1)
/* The operation requested. */
#define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0
#define MC_CMD_TSA_BIND_IN_SET_KEY_OP_LEN 4
@@ -16759,6 +17967,7 @@
#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252
#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX_MCDI2 1020
#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LEN(num) (92+1*(num))
+#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_NUM(len) (((len)-92)/1)
/* The operation requested. */
#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0
#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_LEN 4
@@ -16822,6 +18031,7 @@
#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252
#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX_MCDI2 1020
#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LEN(num) (108+1*(num))
+#define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_NUM(len) (((len)-108)/1)
/* This is the signature of the above mentioned fields- TSAID, USER and REASON.
* As per current requirements, the SIG opaque data blob contains ECDSA ECC-384
* based signature. The ECC curve is secp384r1. The signature is also ASN-1
@@ -16888,6 +18098,7 @@
#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMAX 200
#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMAX_MCDI2 200
#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LEN(num) (96+1*(num))
+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_NUM(len) (((len)-96)/1)
/* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */
#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_OFST 0
#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_LEN 4
@@ -16931,6 +18142,7 @@
#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMAX 216
#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMAX_MCDI2 216
#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LEN(num) (112+1*(num))
+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_NUM(len) (((len)-112)/1)
/* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */
#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_OFST 0
#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_LEN 4
@@ -16993,6 +18205,7 @@
#define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252
#define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX_MCDI2 1020
#define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num))
+#define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_NUM(len) (((len)-14)/1)
/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_ID that is sent back to
* the caller.
*/
@@ -17030,6 +18243,7 @@
#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252
#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX_MCDI2 1020
#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num))
+#define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_NUM(len) (((len)-4)/1)
/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_TICKET that is sent back
* to the caller.
*/
@@ -17117,6 +18331,7 @@
#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX 252
#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX_MCDI2 1020
#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LEN(num) (8+1*(num))
+#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_NUM(len) (((len)-8)/1)
/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_CERTIFICATE that is sent
* back to the caller.
*/
@@ -17229,6 +18444,7 @@
#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252
#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX_MCDI2 1020
#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num))
+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_NUM(len) (((len)-4)/1)
/* indicates whether the persistent cache is valid (after completion of the
* requested operation in the case of rollback, commit, or invalidate)
*/
@@ -17266,6 +18482,7 @@
#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX_MCDI2 1020
#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
+#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1)
/* The tag to be appended */
#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
@@ -17305,6 +18522,7 @@
#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX_MCDI2 1020
#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
+#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1)
/* Number of sectors found (test builds only) */
#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
@@ -18045,6 +19263,7 @@
#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX 252
#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX_MCDI2 1020
#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LEN(num) (16+4*(num))
+#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_NUM(len) (((len)-16)/4)
/* TSA statistics sub-operation code */
#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0
#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_LEN 4
@@ -18085,6 +19304,7 @@
#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX 248
#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX_MCDI2 1016
#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LEN(num) (8+16*(num))
+#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_NUM(len) (((len)-8)/16)
/* Number of statistics counters returned in this response */
#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0
#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_LEN 4
@@ -18167,6 +19387,7 @@
#define MC_CMD_TSA_CONFIG_IN_APPEND_LENMAX 252
#define MC_CMD_TSA_CONFIG_IN_APPEND_LENMAX_MCDI2 1020
#define MC_CMD_TSA_CONFIG_IN_APPEND_LEN(num) (12+1*(num))
+#define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_NUM(len) (((len)-12)/1)
/* TSA configuration sub-operation code. The value shall be
* MC_CMD_TSA_CONFIG_OP_APPEND.
*/
@@ -18215,6 +19436,7 @@
#define MC_CMD_TSA_CONFIG_OUT_READ_LENMAX 252
#define MC_CMD_TSA_CONFIG_OUT_READ_LENMAX_MCDI2 1020
#define MC_CMD_TSA_CONFIG_OUT_READ_LEN(num) (8+1*(num))
+#define MC_CMD_TSA_CONFIG_OUT_READ_DATA_NUM(len) (((len)-8)/1)
/* The tag that was read */
#define MC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0
#define MC_CMD_TSA_CONFIG_OUT_READ_TAG_LEN 4
@@ -18287,6 +19509,7 @@
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX 248
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX_MCDI2 1016
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LEN(num) (8+8*(num))
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_NUM(len) (((len)-8)/8)
/* Header containing information to identify which sub-operation of this
* command to perform. The header contains a 16-bit op-code. Unused space in
* this field is reserved for future expansion.
@@ -18315,6 +19538,7 @@
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX 248
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX_MCDI2 1016
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LEN(num) (8+8*(num))
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_NUM(len) (((len)-8)/8)
/* Header containing information to identify which sub-operation of this
* command to perform. The header contains a 16-bit op-code. Unused space in
* this field is reserved for future expansion.
@@ -18765,6 +19989,7 @@
#define MC_CMD_GET_CERTIFICATE_OUT_LENMAX 252
#define MC_CMD_GET_CERTIFICATE_OUT_LENMAX_MCDI2 1020
#define MC_CMD_GET_CERTIFICATE_OUT_LEN(num) (12+1*(num))
+#define MC_CMD_GET_CERTIFICATE_OUT_DATA_NUM(len) (((len)-12)/1)
/* Type of the certificate. */
#define MC_CMD_GET_CERTIFICATE_OUT_TYPE_OFST 0
#define MC_CMD_GET_CERTIFICATE_OUT_TYPE_LEN 4
@@ -18884,6 +20109,7 @@
#define MC_CMD_LTSSM_TRACE_POLL_OUT_LENMAX 248
#define MC_CMD_LTSSM_TRACE_POLL_OUT_LENMAX_MCDI2 1016
#define MC_CMD_LTSSM_TRACE_POLL_OUT_LEN(num) (8+8*(num))
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_NUM(len) (((len)-8)/8)
#define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_OFST 0
#define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_LEN 4
#define MC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_LBN 0
@@ -19070,6 +20296,342 @@
#define MC_CMD_TELEMETRY_CONFIG_OUT_GET_PARAMETERS_OFST 0
#define MC_CMD_TELEMETRY_CONFIG_OUT_GET_PARAMETERS_LEN 36
+
+/***********************************/
+/* MC_CMD_GET_RX_PREFIX_ID
+ * This command is part of the mechanism for configuring the format of the RX
+ * packet prefix. It takes as input a bitmask of the fields the host would like
+ * to be in the prefix. If the hardware supports RX prefixes with that
+ * combination of fields, then this command returns a list of prefix-ids,
+ * opaque identifiers suitable for use in the RX_PREFIX_ID field of a
+ * MC_CMD_INIT_RXQ_V5_IN message. If the combination of fields is not
+ * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids
+ * due to resource constraints, returns ENOSPC.
+ */
+#define MC_CMD_GET_RX_PREFIX_ID 0x13b
+#undef MC_CMD_0x13b_PRIVILEGE_CTG
+
+#define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_RX_PREFIX_ID_IN msgrequest */
+#define MC_CMD_GET_RX_PREFIX_ID_IN_LEN 8
+/* Field bitmask. */
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_LBN 2
+#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_LBN 3
+#define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_LBN 5
+#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_LBN 6
+#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_LBN 7
+#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_LBN 8
+#define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1
+#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_LBN 9
+#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1
+
+/* MC_CMD_GET_RX_PREFIX_ID_OUT msgresponse */
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMIN 8
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX 252
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num))
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4)
+/* Number of prefix-ids returned */
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4
+/* Opaque prefix identifiers which can be passed into MC_CMD_INIT_RXQ_V5 or
+ * MC_CMD_QUERY_PREFIX_ID
+ */
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM 62
+#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM_MCDI2 254
+
+/* RX_PREFIX_FIELD_INFO structuredef: Information about a single RX prefix
+ * field
+ */
+#define RX_PREFIX_FIELD_INFO_LEN 4
+/* The offset of the field from the start of the prefix, in bits */
+#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0
+#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LEN 2
+#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0
+#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_WIDTH 16
+/* The width of the field, in bits */
+#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_OFST 2
+#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1
+#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LBN 16
+#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_WIDTH 8
+/* The type of the field. These enum values are in the same order as the fields
+ * in the MC_CMD_GET_RX_PREFIX_ID_IN bitmask
+ */
+#define RX_PREFIX_FIELD_INFO_TYPE_OFST 3
+#define RX_PREFIX_FIELD_INFO_TYPE_LEN 1
+#define RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */
+#define RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */
+#define RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */
+#define RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */
+#define RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */
+#define RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */
+#define RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */
+#define RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */
+#define RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */
+#define RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */
+#define RX_PREFIX_FIELD_INFO_TYPE_LBN 24
+#define RX_PREFIX_FIELD_INFO_TYPE_WIDTH 8
+
+/* RX_PREFIX_FIXED_RESPONSE structuredef: Information about an RX prefix in
+ * which every field has a fixed offset and width
+ */
+#define RX_PREFIX_FIXED_RESPONSE_LENMIN 4
+#define RX_PREFIX_FIXED_RESPONSE_LENMAX 252
+#define RX_PREFIX_FIXED_RESPONSE_LENMAX_MCDI2 1020
+#define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num))
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4)
+/* Length of the RX prefix in bytes */
+#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0
+#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1
+#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0
+#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_WIDTH 8
+/* Number of fields present in the prefix */
+#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1
+#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1
+#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LBN 8
+#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_WIDTH 8
+#define RX_PREFIX_FIXED_RESPONSE_RESERVED_OFST 2
+#define RX_PREFIX_FIXED_RESPONSE_RESERVED_LEN 2
+#define RX_PREFIX_FIXED_RESPONSE_RESERVED_LBN 16
+#define RX_PREFIX_FIXED_RESPONSE_RESERVED_WIDTH 16
+/* Array of RX_PREFIX_FIELD_INFO structures, of length FIELD_COUNT */
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM 62
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM_MCDI2 254
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_LBN 32
+#define RX_PREFIX_FIXED_RESPONSE_FIELDS_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_QUERY_RX_PREFIX_ID
+ * This command takes an RX prefix id (obtained from MC_CMD_GET_RX_PREFIX_ID)
+ * and returns a description of the RX prefix of packets delievered to an RXQ
+ * created with that prefix id
+ */
+#define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
+#undef MC_CMD_0x13c_PRIVILEGE_CTG
+
+#define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_QUERY_RX_PREFIX_ID_IN msgrequest */
+#define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4
+/* Prefix id to query */
+#define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0
+#define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4
+
+/* MC_CMD_QUERY_RX_PREFIX_ID_OUT msgresponse */
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX 252
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num))
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1)
+/* An enum describing the structure of this response. */
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1
+/* enum: The response is of format RX_PREFIX_FIXED_RESPONSE */
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_LEN 3
+/* The response. Its format is as defined by the RESPONSE_TYPE value */
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM 248
+#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM_MCDI2 1016
+
+
+/***********************************/
+/* MC_CMD_BUNDLE
+ * A command to perform various bundle-related operations on insecure cards.
+ */
+#define MC_CMD_BUNDLE 0x13d
+#undef MC_CMD_0x13d_PRIVILEGE_CTG
+
+#define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE
+
+/* MC_CMD_BUNDLE_IN msgrequest */
+#define MC_CMD_BUNDLE_IN_LEN 4
+/* Sub-command code */
+#define MC_CMD_BUNDLE_IN_OP_OFST 0
+#define MC_CMD_BUNDLE_IN_OP_LEN 4
+/* enum: Get the current host access mode set on component partitions. */
+#define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0
+/* enum: Set the host access mode set on component partitions. */
+#define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1
+
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN msgrequest: Retrieve the current
+ * access mode on component partitions such as MC_FIRMWARE, SUC_FIRMWARE and
+ * EXPANSION_UEFI. This command only works on engineering (insecure) cards. On
+ * secure adapters, this command returns MC_CMD_ERR_EPERM.
+ */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4
+/* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4
+
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT msgresponse: Returns the access
+ * control mode.
+ */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4
+/* Access mode of component partitions. */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4
+/* enum: Component partitions are read-only from the host. */
+#define MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0
+/* enum: Component partitions can read read-from written-to by the host. */
+#define MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1
+
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN msgrequest: The component
+ * partitions such as MC_FIRMWARE, SUC_FIRMWARE, EXPANSION_UEFI are set as
+ * read-only on firmware built with bundle support. This command marks these
+ * partitions as read/writeable. The access status set by this command does not
+ * persist across MC reboots. This command only works on engineering (insecure)
+ * cards. On secure adapters, this command returns MC_CMD_ERR_EPERM.
+ */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_LEN 8
+/* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4
+/* Access mode of component partitions. */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT/ACCESS_MODE */
+
+/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT msgresponse */
+#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_VPD
+ * Read all VPD starting from a given address
+ */
+#define MC_CMD_GET_VPD 0x165
+#undef MC_CMD_0x165_PRIVILEGE_CTG
+
+#define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_VPD_IN msgresponse */
+#define MC_CMD_GET_VPD_IN_LEN 4
+/* To request only VPD tags from a certain origin. */
+#define MC_CMD_GET_VPD_IN_STORAGE_TYPE_OFST 0
+#define MC_CMD_GET_VPD_IN_STORAGE_TYPE_LEN 2
+/* enum: Return all VPD regardless of origin. */
+#define MC_CMD_GET_VPD_IN_STORAGE_TYPE_ALL 0x0
+/* enum: Return only VPD tags generated by MCFW (not stored in NVRAM) */
+#define MC_CMD_GET_VPD_IN_STORAGE_TYPE_LIVE 0x1
+/* enum: Return only VPD tags stored in NVRAM (not generated by MCFW) */
+#define MC_CMD_GET_VPD_IN_STORAGE_TYPE_NVRAM 0x2
+/* VPD address to start from. In case VPD is longer than MCDI buffer
+ * (unlikely), user can make multiple calls with different starting addresses.
+ */
+#define MC_CMD_GET_VPD_IN_ADDR_OFST 2
+#define MC_CMD_GET_VPD_IN_ADDR_LEN 2
+
+/* MC_CMD_GET_VPD_OUT msgresponse */
+#define MC_CMD_GET_VPD_OUT_LENMIN 5
+#define MC_CMD_GET_VPD_OUT_LENMAX 252
+#define MC_CMD_GET_VPD_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_GET_VPD_OUT_LEN(num) (4+1*(num))
+#define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-4)/1)
+/* Length of VPD data returned. */
+#define MC_CMD_GET_VPD_OUT_DATALEN_OFST 0
+#define MC_CMD_GET_VPD_OUT_DATALEN_LEN 4
+/* VPD data returned. */
+#define MC_CMD_GET_VPD_OUT_DATA_OFST 4
+#define MC_CMD_GET_VPD_OUT_DATA_LEN 1
+#define MC_CMD_GET_VPD_OUT_DATA_MINNUM 1
+#define MC_CMD_GET_VPD_OUT_DATA_MAXNUM 248
+#define MC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1016
+
+
+/***********************************/
+/* MC_CMD_GET_NCSI_INFO
+ * Provide information about the NC-SI stack
+ */
+#define MC_CMD_GET_NCSI_INFO 0x167
+#undef MC_CMD_0x167_PRIVILEGE_CTG
+
+#define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_NCSI_INFO_IN msgrequest */
+#define MC_CMD_GET_NCSI_INFO_IN_LEN 8
+/* Operation to be performed */
+#define MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0
+#define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4
+/* enum: Information on the link settings. */
+#define MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0
+/* enum: Statistics associated with the channel */
+#define MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1
+/* The NC-SI channel on which the operation is to be performed */
+#define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4
+#define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4
+
+/* MC_CMD_GET_NCSI_INFO_LINK_OUT msgresponse */
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_LEN 12
+/* Settings as received from BMC. */
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4
+/* Advertised capabilities applied to channel. */
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4
+/* General status */
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_OFST 8
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_WIDTH 2
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_LBN 2
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_LBN 3
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4
+#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1
+
+/* MC_CMD_GET_NCSI_INFO_STATISTICS_OUT msgresponse */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_LEN 28
+/* The number of NC-SI commands received. */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4
+/* The number of NC-SI commands dropped. */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4
+/* The number of invalid NC-SI commands received. */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_OFST 8
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4
+/* The number of checksum errors seen. */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_OFST 12
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4
+/* The number of NC-SI requests received. */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_OFST 16
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4
+/* The number of NC-SI responses sent (includes AENs) */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_OFST 20
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4
+/* The number of NC-SI AENs sent */
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_OFST 24
+#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4
+
/* EF100_MCDI_EVENT structuredef: The structure of an MCDI_EVENT on EF100
* platforms
*/
@@ -19102,10 +20664,15 @@
*/
#define EF100_MCDI_EVENT_PTP_DATA_OFST 2
#define EF100_MCDI_EVENT_PTP_DATA_LEN 1
-#define EF100_MCDI_EVENT_SRC_LBN 0
-#define EF100_MCDI_EVENT_SRC_WIDTH 8
#define EF100_MCDI_EVENT_PTP_DATA_LBN 16
#define EF100_MCDI_EVENT_PTP_DATA_WIDTH 8
+/* Alias for PTP_DATA. Nobody uses SRC to mean the source of anything, but
+ * there's code that uses it to refer to ptp data
+ */
+#define EF100_MCDI_EVENT_SRC_OFST 2
+#define EF100_MCDI_EVENT_SRC_LEN 1
+#define EF100_MCDI_EVENT_SRC_LBN 16
+#define EF100_MCDI_EVENT_SRC_WIDTH 8
/* Set if this message continues into another event */
#define EF100_MCDI_EVENT_CONT_LBN 24
#define EF100_MCDI_EVENT_CONT_WIDTH 1
@@ -19119,4 +20686,72 @@
#define EF100_MCDI_EVENT_DATA_LBN 32
#define EF100_MCDI_EVENT_DATA_WIDTH 32
+/* CLOCK_INFO structuredef: Information about a single hardware clock */
+#define CLOCK_INFO_LEN 28
+/* Enumeration that uniquely identifies the clock */
+#define CLOCK_INFO_CLOCK_ID_OFST 0
+#define CLOCK_INFO_CLOCK_ID_LEN 2
+/* enum: The Riverhead CMC (card MC) */
+#define CLOCK_INFO_CLOCK_CMC 0x0
+/* enum: The Riverhead NMC (network MC) */
+#define CLOCK_INFO_CLOCK_NMC 0x1
+/* enum: The Riverhead SDNET slice main logic */
+#define CLOCK_INFO_CLOCK_SDNET 0x2
+/* enum: The Riverhead SDNET LUT */
+#define CLOCK_INFO_CLOCK_SDNET_LUT 0x3
+/* enum: The Riverhead SDNET control logic */
+#define CLOCK_INFO_CLOCK_SDNET_CTRL 0x4
+/* enum: The Riverhead Streaming SubSystem */
+#define CLOCK_INFO_CLOCK_SSS 0x5
+/* enum: The Riverhead network MAC and associated CSR registers */
+#define CLOCK_INFO_CLOCK_MAC 0x6
+#define CLOCK_INFO_CLOCK_ID_LBN 0
+#define CLOCK_INFO_CLOCK_ID_WIDTH 16
+/* Assorted flags */
+#define CLOCK_INFO_FLAGS_OFST 2
+#define CLOCK_INFO_FLAGS_LEN 2
+#define CLOCK_INFO_SETTABLE_LBN 0
+#define CLOCK_INFO_SETTABLE_WIDTH 1
+#define CLOCK_INFO_FLAGS_LBN 16
+#define CLOCK_INFO_FLAGS_WIDTH 16
+/* The frequency in HZ */
+#define CLOCK_INFO_FREQUENCY_OFST 4
+#define CLOCK_INFO_FREQUENCY_LEN 8
+#define CLOCK_INFO_FREQUENCY_LO_OFST 4
+#define CLOCK_INFO_FREQUENCY_HI_OFST 8
+#define CLOCK_INFO_FREQUENCY_LBN 32
+#define CLOCK_INFO_FREQUENCY_WIDTH 64
+/* Human-readable ASCII name for clock, with NUL termination */
+#define CLOCK_INFO_NAME_OFST 12
+#define CLOCK_INFO_NAME_LEN 1
+#define CLOCK_INFO_NAME_NUM 16
+#define CLOCK_INFO_NAME_LBN 96
+#define CLOCK_INFO_NAME_WIDTH 8
+
+
+/***********************************/
+/* MC_CMD_GET_CLOCKS_INFO
+ * Get information about the device clocks
+ */
+#define MC_CMD_GET_CLOCKS_INFO 0x166
+#undef MC_CMD_0x166_PRIVILEGE_CTG
+
+#define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLOCKS_INFO_IN msgrequest */
+#define MC_CMD_GET_CLOCKS_INFO_IN_LEN 0
+
+/* MC_CMD_GET_CLOCKS_INFO_OUT msgresponse */
+#define MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0
+#define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX 252
+#define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX_MCDI2 1008
+#define MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num))
+#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
+/* An array of CLOCK_INFO structures. */
+#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0
+#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_LEN 28
+#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0
+#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM 9
+#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM_MCDI2 36
+
#endif /* _SIENA_MC_DRIVER_PCOL_H */
diff --git a/drivers/net/sfc/base/efx_regs_mcdi_aoe.h b/drivers/net/sfc/base/efx_regs_mcdi_aoe.h
index 6bedfd7..8570dbc 100644
--- a/drivers/net/sfc/base/efx_regs_mcdi_aoe.h
+++ b/drivers/net/sfc/base/efx_regs_mcdi_aoe.h
@@ -277,6 +277,7 @@
#define MC_CMD_FC_IN_WRITE32_LENMAX 252
#define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020
#define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))
+#define MC_CMD_FC_IN_WRITE32_BUFFER_NUM(len) (((len)-12)/4)
/* MC_CMD_FC_IN_CMD_OFST 0 */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4
@@ -525,6 +526,7 @@
#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252
#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020
#define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))
+#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_NUM(len) (((len)-16)/4)
/* MC_CMD_FC_IN_CMD_OFST 0 */
/* MC_CMD_FC_IN_CMD_LEN 4 */
/* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
@@ -1031,6 +1033,7 @@
#define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252
#define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))
+#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_NUM(len) (((len)-12)/4)
/* MC_CMD_FC_IN_CMD_OFST 0 */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4
@@ -1256,6 +1259,7 @@
#define MC_CMD_FC_OUT_READ32_LENMAX 252
#define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))
+#define MC_CMD_FC_OUT_READ32_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0
#define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4
#define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1
@@ -1870,6 +1874,7 @@
#define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252
#define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))
+#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1
@@ -2027,6 +2032,7 @@
#define MC_CMD_FC_OUT_DMA_READ_LENMAX 252
#define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
+#define MC_CMD_FC_OUT_DMA_READ_DATA_NUM(len) (((len)-0)/1)
/* The data read */
#define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
#define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
@@ -2128,6 +2134,7 @@
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_NUM(len) (((len)-0)/8)
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4
@@ -2145,6 +2152,7 @@
#define MC_CMD_FC_OUT_SPI_READ_LENMAX 252
#define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))
+#define MC_CMD_FC_OUT_SPI_READ_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1
@@ -2433,6 +2441,7 @@
#define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252
#define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))
+#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4)
/* MC_CMD_AOE_IN_CMD_OFST 0 */
/* MC_CMD_AOE_IN_CMD_LEN 4 */
#define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4
@@ -2794,6 +2803,7 @@
#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
+#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_NUM(len) (((len)-0)/4)
/* Failure counts for each fan */
#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
@@ -2834,6 +2844,7 @@
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
+#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
/* in bytes */
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4
@@ -2848,6 +2859,7 @@
#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
+#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4)
/* Used to align the in and out data blocks so the MC can re-use the cmd */
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4
@@ -2868,6 +2880,7 @@
#define MC_CMD_AOE_OUT_DDR_LENMAX 252
#define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
+#define MC_CMD_AOE_OUT_DDR_SPD_NUM(len) (((len)-16)/1)
/* Information on the module. */
#define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
#define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4
diff --git a/drivers/net/sfc/base/efx_regs_mcdi_strs.h b/drivers/net/sfc/base/efx_regs_mcdi_strs.h
index 73d633c..9f6d88c 100644
--- a/drivers/net/sfc/base/efx_regs_mcdi_strs.h
+++ b/drivers/net/sfc/base/efx_regs_mcdi_strs.h
@@ -6,97 +6,97 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files under firmwaresrc doc/mcdi/ and
+ * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
* rebuild this file with "make -C doc mcdiheaders".
*
* The version of this file has MCDI strings really used in the libefx.
*/
-#ifndef _MC_DRIVER_PCOL_STRS_H
-#define _MC_DRIVER_PCOL_STRS_H
+#ifndef _SIENA_MC_DRIVER_PCOL_STRS_H
+#define _SIENA_MC_DRIVER_PCOL_STRS_H
-#define MC_CMD_SENSOR_CONTROLLER_TEMP_ENUM_STR "Controller temperature: degC"
-#define MC_CMD_SENSOR_PHY_COMMON_TEMP_ENUM_STR "Phy common temperature: degC"
-#define MC_CMD_SENSOR_CONTROLLER_COOLING_ENUM_STR "Controller cooling: bool"
-#define MC_CMD_SENSOR_PHY0_TEMP_ENUM_STR "Phy 0 temperature: degC"
-#define MC_CMD_SENSOR_PHY0_COOLING_ENUM_STR "Phy 0 cooling: bool"
-#define MC_CMD_SENSOR_PHY1_TEMP_ENUM_STR "Phy 1 temperature: degC"
-#define MC_CMD_SENSOR_PHY1_COOLING_ENUM_STR "Phy 1 cooling: bool"
-#define MC_CMD_SENSOR_IN_1V0_ENUM_STR "1.0v power: mV"
-#define MC_CMD_SENSOR_IN_1V2_ENUM_STR "1.2v power: mV"
-#define MC_CMD_SENSOR_IN_1V8_ENUM_STR "1.8v power: mV"
-#define MC_CMD_SENSOR_IN_2V5_ENUM_STR "2.5v power: mV"
-#define MC_CMD_SENSOR_IN_3V3_ENUM_STR "3.3v power: mV"
-#define MC_CMD_SENSOR_IN_12V0_ENUM_STR "12v power: mV"
-#define MC_CMD_SENSOR_IN_1V2A_ENUM_STR "1.2v analogue power: mV"
-#define MC_CMD_SENSOR_IN_VREF_ENUM_STR "reference voltage: mV"
-#define MC_CMD_SENSOR_OUT_VAOE_ENUM_STR "AOE FPGA power: mV"
-#define MC_CMD_SENSOR_AOE_TEMP_ENUM_STR "AOE FPGA temperature: degC"
-#define MC_CMD_SENSOR_PSU_AOE_TEMP_ENUM_STR "AOE FPGA PSU temperature: degC"
-#define MC_CMD_SENSOR_PSU_TEMP_ENUM_STR "AOE PSU temperature: degC"
-#define MC_CMD_SENSOR_FAN_0_ENUM_STR "Fan 0 speed: RPM"
-#define MC_CMD_SENSOR_FAN_1_ENUM_STR "Fan 1 speed: RPM"
-#define MC_CMD_SENSOR_FAN_2_ENUM_STR "Fan 2 speed: RPM"
-#define MC_CMD_SENSOR_FAN_3_ENUM_STR "Fan 3 speed: RPM"
-#define MC_CMD_SENSOR_FAN_4_ENUM_STR "Fan 4 speed: RPM"
-#define MC_CMD_SENSOR_IN_VAOE_ENUM_STR "AOE FPGA input power: mV"
-#define MC_CMD_SENSOR_OUT_IAOE_ENUM_STR "AOE FPGA current: mA"
-#define MC_CMD_SENSOR_IN_IAOE_ENUM_STR "AOE FPGA input current: mA"
-#define MC_CMD_SENSOR_NIC_POWER_ENUM_STR "NIC power consumption: W"
-#define MC_CMD_SENSOR_IN_0V9_ENUM_STR "0.9v power voltage: mV"
-#define MC_CMD_SENSOR_IN_I0V9_ENUM_STR "0.9v power current: mA"
-#define MC_CMD_SENSOR_IN_I1V2_ENUM_STR "1.2v power current: mA"
-#define MC_CMD_SENSOR_PAGE0_NEXT_ENUM_STR "Not a sensor: reserved for the next page flag"
-#define MC_CMD_SENSOR_IN_0V9_ADC_ENUM_STR "0.9v power voltage (at ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_2_TEMP_ENUM_STR "Controller temperature 2: degC"
-#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP_ENUM_STR "Voltage regulator internal temperature: degC"
-#define MC_CMD_SENSOR_VREG_0V9_TEMP_ENUM_STR "0.9V voltage regulator temperature: degC"
-#define MC_CMD_SENSOR_VREG_1V2_TEMP_ENUM_STR "1.2V voltage regulator temperature: degC"
-#define MC_CMD_SENSOR_CONTROLLER_VPTAT_ENUM_STR "controller internal temperature sensor voltage (internal ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_ENUM_STR "controller internal temperature (internal ADC): degC"
-#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC_ENUM_STR "controller internal temperature sensor voltage (external ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC_ENUM_STR "controller internal temperature (external ADC): degC"
-#define MC_CMD_SENSOR_AMBIENT_TEMP_ENUM_STR "ambient temperature: degC"
-#define MC_CMD_SENSOR_AIRFLOW_ENUM_STR "air flow: bool"
-#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_ENUM_STR "voltage between VSS08D and VSS08D at CSR: mV"
-#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC_ENUM_STR "voltage between VSS08D and VSS08D at CSR (external ADC): mV"
-#define MC_CMD_SENSOR_HOTPOINT_TEMP_ENUM_STR "Hotpoint temperature: degC"
-#define MC_CMD_SENSOR_PHY_POWER_PORT0_ENUM_STR "Port 0 PHY power switch over-current: bool"
-#define MC_CMD_SENSOR_PHY_POWER_PORT1_ENUM_STR "Port 1 PHY power switch over-current: bool"
-#define MC_CMD_SENSOR_MUM_VCC_ENUM_STR "Mop-up microcontroller reference voltage: mV"
-#define MC_CMD_SENSOR_IN_0V9_A_ENUM_STR "0.9v power phase A voltage: mV"
-#define MC_CMD_SENSOR_IN_I0V9_A_ENUM_STR "0.9v power phase A current: mA"
-#define MC_CMD_SENSOR_VREG_0V9_A_TEMP_ENUM_STR "0.9V voltage regulator phase A temperature: degC"
-#define MC_CMD_SENSOR_IN_0V9_B_ENUM_STR "0.9v power phase B voltage: mV"
-#define MC_CMD_SENSOR_IN_I0V9_B_ENUM_STR "0.9v power phase B current: mA"
-#define MC_CMD_SENSOR_VREG_0V9_B_TEMP_ENUM_STR "0.9V voltage regulator phase B temperature: degC"
-#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_ENUM_STR "CCOM AVREG 1v2 supply (interval ADC): mV"
-#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC_ENUM_STR "CCOM AVREG 1v2 supply (external ADC): mV"
-#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_ENUM_STR "CCOM AVREG 1v8 supply (interval ADC): mV"
-#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC_ENUM_STR "CCOM AVREG 1v8 supply (external ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_RTS_ENUM_STR "CCOM RTS temperature: degC"
-#define MC_CMD_SENSOR_PAGE1_NEXT_ENUM_STR "Not a sensor: reserved for the next page flag"
-#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_ENUM_STR "controller internal temperature sensor voltage on master core (internal ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_ENUM_STR "controller internal temperature on master core (internal ADC): degC"
-#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC_ENUM_STR "controller internal temperature sensor voltage on master core (external ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC_ENUM_STR "controller internal temperature on master core (external ADC): degC"
-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_ENUM_STR "controller internal temperature on slave core sensor voltage (internal ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_ENUM_STR "controller internal temperature on slave core (internal ADC): degC"
-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC_ENUM_STR "controller internal temperature on slave core sensor voltage (external ADC): mV"
-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC_ENUM_STR "controller internal temperature on slave core (external ADC): degC"
-#define MC_CMD_SENSOR_SODIMM_VOUT_ENUM_STR "Voltage supplied to the SODIMMs from their power supply: mV"
-#define MC_CMD_SENSOR_SODIMM_0_TEMP_ENUM_STR "Temperature of SODIMM 0 (if installed): degC"
-#define MC_CMD_SENSOR_SODIMM_1_TEMP_ENUM_STR "Temperature of SODIMM 1 (if installed): degC"
-#define MC_CMD_SENSOR_PHY0_VCC_ENUM_STR "Voltage supplied to the QSFP #0 from their power supply: mV"
-#define MC_CMD_SENSOR_PHY1_VCC_ENUM_STR "Voltage supplied to the QSFP #1 from their power supply: mV"
-#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP_ENUM_STR "Controller die temperature (TDIODE): degC"
-#define MC_CMD_SENSOR_BOARD_FRONT_TEMP_ENUM_STR "Board temperature (front): degC"
-#define MC_CMD_SENSOR_BOARD_BACK_TEMP_ENUM_STR "Board temperature (back): degC"
-#define MC_CMD_SENSOR_IN_I1V8_ENUM_STR "1.8v power current: mA"
-#define MC_CMD_SENSOR_IN_I2V5_ENUM_STR "2.5v power current: mA"
-#define MC_CMD_SENSOR_IN_I3V3_ENUM_STR "3.3v power current: mA"
-#define MC_CMD_SENSOR_IN_I12V0_ENUM_STR "12v power current: mA"
-#define MC_CMD_SENSOR_IN_1V3_ENUM_STR "1.3v power: mV"
-#define MC_CMD_SENSOR_IN_I1V3_ENUM_STR "1.3v power current: mA"
+#define MC_CMD_SENSOR_CONTROLLER_TEMP_ENUM_STR "Controller temperature: degC"
+#define MC_CMD_SENSOR_PHY_COMMON_TEMP_ENUM_STR "Phy common temperature: degC"
+#define MC_CMD_SENSOR_CONTROLLER_COOLING_ENUM_STR "Controller cooling: bool"
+#define MC_CMD_SENSOR_PHY0_TEMP_ENUM_STR "Phy 0 temperature: degC"
+#define MC_CMD_SENSOR_PHY0_COOLING_ENUM_STR "Phy 0 cooling: bool"
+#define MC_CMD_SENSOR_PHY1_TEMP_ENUM_STR "Phy 1 temperature: degC"
+#define MC_CMD_SENSOR_PHY1_COOLING_ENUM_STR "Phy 1 cooling: bool"
+#define MC_CMD_SENSOR_IN_1V0_ENUM_STR "1.0v power: mV"
+#define MC_CMD_SENSOR_IN_1V2_ENUM_STR "1.2v power: mV"
+#define MC_CMD_SENSOR_IN_1V8_ENUM_STR "1.8v power: mV"
+#define MC_CMD_SENSOR_IN_2V5_ENUM_STR "2.5v power: mV"
+#define MC_CMD_SENSOR_IN_3V3_ENUM_STR "3.3v power: mV"
+#define MC_CMD_SENSOR_IN_12V0_ENUM_STR "12v power: mV"
+#define MC_CMD_SENSOR_IN_1V2A_ENUM_STR "1.2v analogue power: mV"
+#define MC_CMD_SENSOR_IN_VREF_ENUM_STR "reference voltage: mV"
+#define MC_CMD_SENSOR_OUT_VAOE_ENUM_STR "AOE FPGA power: mV"
+#define MC_CMD_SENSOR_AOE_TEMP_ENUM_STR "AOE FPGA temperature: degC"
+#define MC_CMD_SENSOR_PSU_AOE_TEMP_ENUM_STR "AOE FPGA PSU temperature: degC"
+#define MC_CMD_SENSOR_PSU_TEMP_ENUM_STR "AOE PSU temperature: degC"
+#define MC_CMD_SENSOR_FAN_0_ENUM_STR "Fan 0 speed: RPM"
+#define MC_CMD_SENSOR_FAN_1_ENUM_STR "Fan 1 speed: RPM"
+#define MC_CMD_SENSOR_FAN_2_ENUM_STR "Fan 2 speed: RPM"
+#define MC_CMD_SENSOR_FAN_3_ENUM_STR "Fan 3 speed: RPM"
+#define MC_CMD_SENSOR_FAN_4_ENUM_STR "Fan 4 speed: RPM"
+#define MC_CMD_SENSOR_IN_VAOE_ENUM_STR "AOE FPGA input power: mV"
+#define MC_CMD_SENSOR_OUT_IAOE_ENUM_STR "AOE FPGA current: mA"
+#define MC_CMD_SENSOR_IN_IAOE_ENUM_STR "AOE FPGA input current: mA"
+#define MC_CMD_SENSOR_NIC_POWER_ENUM_STR "NIC power consumption: W"
+#define MC_CMD_SENSOR_IN_0V9_ENUM_STR "0.9v power voltage: mV"
+#define MC_CMD_SENSOR_IN_I0V9_ENUM_STR "0.9v power current: mA"
+#define MC_CMD_SENSOR_IN_I1V2_ENUM_STR "1.2v power current: mA"
+#define MC_CMD_SENSOR_PAGE0_NEXT_ENUM_STR "Not a sensor: reserved for the next page flag"
+#define MC_CMD_SENSOR_IN_0V9_ADC_ENUM_STR "0.9v power voltage (at ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_2_TEMP_ENUM_STR "Controller temperature 2: degC"
+#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP_ENUM_STR "Voltage regulator internal temperature: degC"
+#define MC_CMD_SENSOR_VREG_0V9_TEMP_ENUM_STR "0.9V voltage regulator temperature: degC"
+#define MC_CMD_SENSOR_VREG_1V2_TEMP_ENUM_STR "1.2V voltage regulator temperature: degC"
+#define MC_CMD_SENSOR_CONTROLLER_VPTAT_ENUM_STR "controller internal temperature sensor voltage (internal ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_ENUM_STR "controller internal temperature (internal ADC): degC"
+#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC_ENUM_STR "controller internal temperature sensor voltage (external ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC_ENUM_STR "controller internal temperature (external ADC): degC"
+#define MC_CMD_SENSOR_AMBIENT_TEMP_ENUM_STR "ambient temperature: degC"
+#define MC_CMD_SENSOR_AIRFLOW_ENUM_STR "air flow: bool"
+#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_ENUM_STR "voltage between VSS08D and VSS08D at CSR: mV"
+#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC_ENUM_STR "voltage between VSS08D and VSS08D at CSR (external ADC): mV"
+#define MC_CMD_SENSOR_HOTPOINT_TEMP_ENUM_STR "Hotpoint temperature: degC"
+#define MC_CMD_SENSOR_PHY_POWER_PORT0_ENUM_STR "Port 0 PHY power switch over-current: bool"
+#define MC_CMD_SENSOR_PHY_POWER_PORT1_ENUM_STR "Port 1 PHY power switch over-current: bool"
+#define MC_CMD_SENSOR_MUM_VCC_ENUM_STR "Mop-up microcontroller reference voltage: mV"
+#define MC_CMD_SENSOR_IN_0V9_A_ENUM_STR "0.9v power phase A voltage: mV"
+#define MC_CMD_SENSOR_IN_I0V9_A_ENUM_STR "0.9v power phase A current: mA"
+#define MC_CMD_SENSOR_VREG_0V9_A_TEMP_ENUM_STR "0.9V voltage regulator phase A temperature: degC"
+#define MC_CMD_SENSOR_IN_0V9_B_ENUM_STR "0.9v power phase B voltage: mV"
+#define MC_CMD_SENSOR_IN_I0V9_B_ENUM_STR "0.9v power phase B current: mA"
+#define MC_CMD_SENSOR_VREG_0V9_B_TEMP_ENUM_STR "0.9V voltage regulator phase B temperature: degC"
+#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_ENUM_STR "CCOM AVREG 1v2 supply (interval ADC): mV"
+#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC_ENUM_STR "CCOM AVREG 1v2 supply (external ADC): mV"
+#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_ENUM_STR "CCOM AVREG 1v8 supply (interval ADC): mV"
+#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC_ENUM_STR "CCOM AVREG 1v8 supply (external ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_RTS_ENUM_STR "CCOM RTS temperature: degC"
+#define MC_CMD_SENSOR_PAGE1_NEXT_ENUM_STR "Not a sensor: reserved for the next page flag"
+#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_ENUM_STR "controller internal temperature sensor voltage on master core (internal ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_ENUM_STR "controller internal temperature on master core (internal ADC): degC"
+#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC_ENUM_STR "controller internal temperature sensor voltage on master core (external ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC_ENUM_STR "controller internal temperature on master core (external ADC): degC"
+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_ENUM_STR "controller internal temperature on slave core sensor voltage (internal ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_ENUM_STR "controller internal temperature on slave core (internal ADC): degC"
+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC_ENUM_STR "controller internal temperature on slave core sensor voltage (external ADC): mV"
+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC_ENUM_STR "controller internal temperature on slave core (external ADC): degC"
+#define MC_CMD_SENSOR_SODIMM_VOUT_ENUM_STR "Voltage supplied to the SODIMMs from their power supply: mV"
+#define MC_CMD_SENSOR_SODIMM_0_TEMP_ENUM_STR "Temperature of SODIMM 0 (if installed): degC"
+#define MC_CMD_SENSOR_SODIMM_1_TEMP_ENUM_STR "Temperature of SODIMM 1 (if installed): degC"
+#define MC_CMD_SENSOR_PHY0_VCC_ENUM_STR "Voltage supplied to the QSFP #0 from their power supply: mV"
+#define MC_CMD_SENSOR_PHY1_VCC_ENUM_STR "Voltage supplied to the QSFP #1 from their power supply: mV"
+#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP_ENUM_STR "Controller die temperature (TDIODE): degC"
+#define MC_CMD_SENSOR_BOARD_FRONT_TEMP_ENUM_STR "Board temperature (front): degC"
+#define MC_CMD_SENSOR_BOARD_BACK_TEMP_ENUM_STR "Board temperature (back): degC"
+#define MC_CMD_SENSOR_IN_I1V8_ENUM_STR "1.8v power current: mA"
+#define MC_CMD_SENSOR_IN_I2V5_ENUM_STR "2.5v power current: mA"
+#define MC_CMD_SENSOR_IN_I3V3_ENUM_STR "3.3v power current: mA"
+#define MC_CMD_SENSOR_IN_I12V0_ENUM_STR "12v power current: mA"
+#define MC_CMD_SENSOR_IN_1V3_ENUM_STR "1.3v power: mV"
+#define MC_CMD_SENSOR_IN_I1V3_ENUM_STR "1.3v power current: mA"
-#endif /* _MC_DRIVER_PCOL_STRS_H */
+#endif /* _SIENA_MC_DRIVER_PCOL_STRS_H */
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 11/29] net/sfc/base: add firmware ID header
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (9 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 10/29] net/sfc/base: update MCDI headers Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 12/29] net/sfc/base: support direct FW update for bundle partitions Andrew Rybchenko
` (18 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Add definitions header for reflash header IDs. This is required to
support different handling modes for signed firmware images.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_firmware_ids.h | 184 +++++++++++++++++++++++++++++++
1 file changed, 184 insertions(+)
create mode 100644 drivers/net/sfc/base/ef10_firmware_ids.h
diff --git a/drivers/net/sfc/base/ef10_firmware_ids.h b/drivers/net/sfc/base/ef10_firmware_ids.h
new file mode 100644
index 0000000..82c31c6
--- /dev/null
+++ b/drivers/net/sfc/base/ef10_firmware_ids.h
@@ -0,0 +1,184 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2012-2018 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+/*
+ * This is NOT the original source file. Do NOT edit it.
+ * To update the board and firmware ids, please edit the copy in
+ * the sfregistry repo and then, in that repo,
+ * "make id_headers" or "make export" to
+ * regenerate and export all types of headers.
+ */
+
+#ifndef CI_MGMT_FIRMWARE_IDS_H
+#define CI_MGMT_FIRMWARE_IDS_H
+
+/* Reference: SF-103588-PS
+ *
+ * This header file is the input for v5s/scripts/genfwdef. So if you touch it,
+ * ensure that v5/scripts/genfwdef still works.
+ */
+
+enum {
+ FIRMWARE_TYPE_PHY = 0,
+ FIRMWARE_TYPE_PHY_LOADER = 1,
+ FIRMWARE_TYPE_BOOTROM = 2,
+ FIRMWARE_TYPE_MCFW = 3,
+ FIRMWARE_TYPE_MCFW_BACKUP = 4,
+ FIRMWARE_TYPE_DISABLED_CALLISTO = 5,
+ FIRMWARE_TYPE_FPGA = 6,
+ FIRMWARE_TYPE_FPGA_BACKUP = 7,
+ FIRMWARE_TYPE_FCFW = 8,
+ FIRMWARE_TYPE_FCFW_BACKUP = 9,
+ FIRMWARE_TYPE_CPLD = 10,
+ FIRMWARE_TYPE_MUMFW = 11,
+ FIRMWARE_TYPE_UEFIROM = 12,
+ FIRMWARE_TYPE_BUNDLE = 13,
+ FIRMWARE_TYPE_CMCFW = 14,
+};
+
+enum {
+ FIRMWARE_PHY_SUBTYPE_SFX7101B = 0x3,
+ FIRMWARE_PHY_SUBTYPE_SFT9001A = 0x8,
+ FIRMWARE_PHY_SUBTYPE_QT2025C = 0x9,
+ FIRMWARE_PHY_SUBTYPE_SFT9001B = 0xa,
+ FIRMWARE_PHY_SUBTYPE_SFL9021 = 0x10, /* used for loader only */
+ FIRMWARE_PHY_SUBTYPE_QT2025_KR = 0x11, /* QT2025 in KR rather than SFP+ mode */
+ FIRMWARE_PHY_SUBTYPE_AEL3020 = 0x12, /* As seen on the R2 HP blade NIC */
+};
+
+enum {
+ FIRMWARE_BOOTROM_SUBTYPE_FALCON = 0,
+ FIRMWARE_BOOTROM_SUBTYPE_BETHPAGE = 1,
+ FIRMWARE_BOOTROM_SUBTYPE_SIENA = 2,
+ FIRMWARE_BOOTROM_SUBTYPE_HUNTINGTON = 3,
+ FIRMWARE_BOOTROM_SUBTYPE_FARMINGDALE = 4,
+ FIRMWARE_BOOTROM_SUBTYPE_GREENPORT = 5,
+ FIRMWARE_BOOTROM_SUBTYPE_MEDFORD = 6,
+ FIRMWARE_BOOTROM_SUBTYPE_MEDFORD2 = 7,
+ FIRMWARE_BOOTROM_SUBTYPE_RIVERHEAD = 8,
+};
+
+enum {
+ FIRMWARE_MCFW_SUBTYPE_COSIM = 0,
+ FIRMWARE_MCFW_SUBTYPE_HALFSPEED = 6,
+ FIRMWARE_MCFW_SUBTYPE_FLORENCE = 7,
+ FIRMWARE_MCFW_SUBTYPE_ZEBEDEE = 8,
+ FIRMWARE_MCFW_SUBTYPE_ERMINTRUDE = 9,
+ FIRMWARE_MCFW_SUBTYPE_DYLAN = 10,
+ FIRMWARE_MCFW_SUBTYPE_BRIAN = 11,
+ FIRMWARE_MCFW_SUBTYPE_DOUGAL = 12,
+ FIRMWARE_MCFW_SUBTYPE_MR_RUSTY = 13,
+ FIRMWARE_MCFW_SUBTYPE_BUXTON = 14,
+ FIRMWARE_MCFW_SUBTYPE_HOPE = 15,
+ FIRMWARE_MCFW_SUBTYPE_MR_MCHENRY = 16,
+ FIRMWARE_MCFW_SUBTYPE_UNCLE_HAMISH = 17,
+ FIRMWARE_MCFW_SUBTYPE_TUTTLE = 18,
+ FIRMWARE_MCFW_SUBTYPE_FINLAY = 19,
+ FIRMWARE_MCFW_SUBTYPE_KAPTEYN = 20,
+ FIRMWARE_MCFW_SUBTYPE_JOHNSON = 21,
+ FIRMWARE_MCFW_SUBTYPE_GEHRELS = 22,
+ FIRMWARE_MCFW_SUBTYPE_WHIPPLE = 23,
+ FIRMWARE_MCFW_SUBTYPE_FORBES = 24,
+ FIRMWARE_MCFW_SUBTYPE_LONGMORE = 25,
+ FIRMWARE_MCFW_SUBTYPE_HERSCHEL = 26,
+ FIRMWARE_MCFW_SUBTYPE_SHOEMAKER = 27,
+ FIRMWARE_MCFW_SUBTYPE_IKEYA = 28,
+ FIRMWARE_MCFW_SUBTYPE_KOWALSKI = 29,
+ FIRMWARE_MCFW_SUBTYPE_NIMRUD = 30,
+ FIRMWARE_MCFW_SUBTYPE_SPARTA = 31,
+ FIRMWARE_MCFW_SUBTYPE_THEBES = 32,
+ FIRMWARE_MCFW_SUBTYPE_ICARUS = 33,
+ FIRMWARE_MCFW_SUBTYPE_JERICHO = 34,
+ FIRMWARE_MCFW_SUBTYPE_BYBLOS = 35,
+ FIRMWARE_MCFW_SUBTYPE_GROAT = 36,
+ FIRMWARE_MCFW_SUBTYPE_SHILLING = 37,
+ FIRMWARE_MCFW_SUBTYPE_FLORIN = 38,
+ FIRMWARE_MCFW_SUBTYPE_THREEPENCE = 39,
+ FIRMWARE_MCFW_SUBTYPE_CYCLOPS = 40,
+ FIRMWARE_MCFW_SUBTYPE_PENNY = 41,
+ FIRMWARE_MCFW_SUBTYPE_BOB = 42,
+ FIRMWARE_MCFW_SUBTYPE_HOG = 43,
+ FIRMWARE_MCFW_SUBTYPE_SOVEREIGN = 44,
+ FIRMWARE_MCFW_SUBTYPE_SOLIDUS = 45,
+ FIRMWARE_MCFW_SUBTYPE_SIXPENCE = 46,
+ FIRMWARE_MCFW_SUBTYPE_CROWN = 47,
+ FIRMWARE_MCFW_SUBTYPE_SOL = 48,
+ FIRMWARE_MCFW_SUBTYPE_TANNER = 49,
+ FIRMWARE_MCFW_SUBTYPE_BELUGA = 64,
+ FIRMWARE_MCFW_SUBTYPE_KALUGA = 65,
+};
+
+enum {
+ FIRMWARE_DISABLED_CALLISTO_SUBTYPE_ALL = 0
+};
+
+enum {
+ FIRMWARE_FPGA_SUBTYPE_PTP = 1, /* PTP peripheral */
+ FIRMWARE_FPGA_SUBTYPE_PTP_MR_MCHENRY = 2, /* PTP peripheral on R7 boards */
+ FIRMWARE_FPGA_SUBTYPE_FLORENCE = 3, /* Modena FPGA */
+ FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH = 4, /* Modena FPGA: Unknown silicon */
+ FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH_A7 = 5, /* Modena FPGA: A7 silicon */
+ FIRMWARE_FPGA_SUBTYPE_UNCLE_HAMISH_A5 = 6, /* Modena FPGA: A5 silicon */
+ FIRMWARE_FPGA_SUBTYPE_SHOEMAKER = 7, /* Sorrento FPGA: Unknown silicon */
+ FIRMWARE_FPGA_SUBTYPE_SHOEMAKER_A5 = 8, /* Sorrento FPGA: A5 silicon */
+ FIRMWARE_FPGA_SUBTYPE_SHOEMAKER_A7 = 9, /* Sorrento FPGA: A7 silicon */
+};
+
+enum {
+ FIRMWARE_FCFW_SUBTYPE_MODENA = 1,
+ FIRMWARE_FCFW_SUBTYPE_SORRENTO = 2,
+};
+
+enum {
+ FIRMWARE_CPLD_SUBTYPE_SFA6902 = 1, /* CPLD on Modena (2-port) */
+};
+
+enum {
+ FIRMWARE_LICENSE_SUBTYPE_AOE = 1, /* AOE */
+};
+
+enum {
+ FIRMWARE_MUMFW_SUBTYPE_MADAM_BLUE = 1, /* Sorrento MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_ICARUS = 2, /* Malaga MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_JERICHO = 3, /* Emma MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_BYBLOS = 4, /* Pagnell MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_SHILLING = 5, /* Bradford R1.x MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_FLORIN = 6, /* Bingley MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_THREEPENCE = 7, /* Baildon MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_CYCLOPS = 8, /* Talbot MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_PENNY = 9, /* Batley MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_BOB = 10, /* Bradford R2.x MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_HOG = 11, /* Roxburgh MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_SOVEREIGN = 12, /* Stirling MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_SOLIDUS = 13, /* Roxburgh R2 MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_SIXPENCE = 14, /* Melrose MUM firmware for Dell cards */
+ FIRMWARE_MUMFW_SUBTYPE_CROWN = 15, /* Coldstream MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_SOL = 16, /* Roxburgh R2 MUM firmware for Dell cards with signed-bundle-update */
+ FIRMWARE_MUMFW_SUBTYPE_KALUGA = 17, /* York MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_STERLET = 18, /* Bourn MUM firmware */
+ FIRMWARE_MUMFW_SUBTYPE_TANNER = 19, /* Melrose MUM firmware for channel cards */
+
+};
+
+
+#define FIRMWARE_UEFIROM_SUBTYPE_ALL FIRMWARE_UEFIROM_SUBTYPE_EF10
+enum {
+ FIRMWARE_UEFIROM_SUBTYPE_EF10 = 0,
+};
+
+enum {
+ FIRMWARE_BUNDLE_SUBTYPE_DELL_X2522_25G = 1, /* X2522-25G for Dell with bundle update support */
+ FIRMWARE_BUNDLE_SUBTYPE_X2552 = 2, /* X2552 OCP NIC - firmware bundle */
+ FIRMWARE_BUNDLE_SUBTYPE_DELL_X2562 = 3, /* X2562 OCP NIC for Dell - firmware bundle */
+ FIRMWARE_BUNDLE_SUBTYPE_X2562 = 4, /* X2562 OCP NIC - firmware bundle */
+};
+
+enum {
+ FIRMWARE_CMCFW_SUBTYPE_BELUGA = 1, /* Riverhead VCU1525 CMC firmware */
+ FIRMWARE_CMCFW_SUBTYPE_KALUGA = 2, /* York (X3x42) board CMC firmware */
+};
+
+#endif
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 12/29] net/sfc/base: support direct FW update for bundle partitions
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (10 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 11/29] net/sfc/base: add firmware ID header Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 13/29] net/sfc/base: transition to the extensible NVRAM info API Andrew Rybchenko
` (17 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
All signed images other than for the MCFW partition should
be written fully to the partition with no rearrangement.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_image.c | 74 ++++++++++++++++++++++++---------------
drivers/net/sfc/base/efx.h | 1 +
2 files changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_image.c b/drivers/net/sfc/base/ef10_image.c
index c035e0d..a19df7f 100644
--- a/drivers/net/sfc/base/ef10_image.c
+++ b/drivers/net/sfc/base/ef10_image.c
@@ -7,6 +7,8 @@
#include "efx.h"
#include "efx_impl.h"
+#include "ef10_firmware_ids.h"
+
#if EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
#if EFSYS_OPT_IMAGE_LAYOUT
@@ -429,54 +431,59 @@
static __checkReturn efx_rc_t
efx_check_unsigned_image(
- __in void *bufferp,
- __in uint32_t buffer_size)
+ __in void *bufferp,
+ __in uint32_t buffer_size,
+ __out efx_image_header_t **headerpp,
+ __out efx_image_trailer_t **trailerpp)
{
- efx_image_header_t *header;
- efx_image_trailer_t *trailer;
+ efx_image_header_t *headerp;
+ efx_image_trailer_t *trailerp;
uint32_t crc;
efx_rc_t rc;
- EFX_STATIC_ASSERT(sizeof (*header) == EFX_IMAGE_HEADER_SIZE);
- EFX_STATIC_ASSERT(sizeof (*trailer) == EFX_IMAGE_TRAILER_SIZE);
+ EFX_STATIC_ASSERT(sizeof (*headerp) == EFX_IMAGE_HEADER_SIZE);
+ EFX_STATIC_ASSERT(sizeof (*trailerp) == EFX_IMAGE_TRAILER_SIZE);
/* Must have at least enough space for required image header fields */
if (buffer_size < (EFX_FIELD_OFFSET(efx_image_header_t, eih_size) +
- sizeof (header->eih_size))) {
+ sizeof (headerp->eih_size))) {
rc = ENOSPC;
goto fail1;
}
- header = (efx_image_header_t *)bufferp;
+ headerp = (efx_image_header_t *)bufferp;
- if (header->eih_magic != EFX_IMAGE_HEADER_MAGIC) {
- rc = EINVAL;
+ /* Buffer must have space for image header, code and image trailer. */
+ if (buffer_size < (headerp->eih_size + headerp->eih_code_size +
+ EFX_IMAGE_TRAILER_SIZE)) {
+ rc = ENOSPC;
goto fail2;
}
+ trailerp = (efx_image_trailer_t *)((uint8_t *)headerp +
+ headerp->eih_size + headerp->eih_code_size);
+
+ *headerpp = headerp;
+ *trailerpp = trailerp;
+
+ if (headerp->eih_magic != EFX_IMAGE_HEADER_MAGIC) {
+ rc = EINVAL;
+ goto fail3;
+ }
+
/*
* Check image header version is same or higher than lowest required
* version.
*/
- if (header->eih_version < EFX_IMAGE_HEADER_VERSION) {
+ if (headerp->eih_version < EFX_IMAGE_HEADER_VERSION) {
rc = EINVAL;
- goto fail3;
- }
-
- /* Buffer must have space for image header, code and image trailer. */
- if (buffer_size < (header->eih_size + header->eih_code_size +
- EFX_IMAGE_TRAILER_SIZE)) {
- rc = ENOSPC;
goto fail4;
}
/* Check CRC from image buffer matches computed CRC. */
- trailer = (efx_image_trailer_t *)((uint8_t *)header +
- header->eih_size + header->eih_code_size);
+ crc = efx_crc32_calculate(0, (uint8_t *)headerp,
+ (headerp->eih_size + headerp->eih_code_size));
- crc = efx_crc32_calculate(0, (uint8_t *)header,
- (header->eih_size + header->eih_code_size));
-
- if (trailer->eit_crc != crc) {
+ if (trailerp->eit_crc != crc) {
rc = EINVAL;
goto fail5;
}
@@ -507,9 +514,10 @@
uint32_t image_offset;
uint32_t image_size;
void *imagep;
+ efx_image_header_t *headerp;
+ efx_image_trailer_t *trailerp;
efx_rc_t rc;
-
EFSYS_ASSERT(infop != NULL);
if (infop == NULL) {
rc = EINVAL;
@@ -531,7 +539,7 @@
if (rc == 0) {
/*
* Buffer holds signed image format. Check that the encapsulated
- * content is in unsigned image format.
+ * content contains an unsigned image format header.
*/
format = EFX_IMAGE_FORMAT_SIGNED;
} else {
@@ -546,11 +554,21 @@
}
imagep = (uint8_t *)bufferp + image_offset;
- /* Check unsigned image layout (image header, code, image trailer) */
- rc = efx_check_unsigned_image(imagep, image_size);
+ /* Check image layout (image header, code, image trailer) */
+ rc = efx_check_unsigned_image(imagep, image_size, &headerp, &trailerp);
if (rc != 0)
goto fail4;
+ /*
+ * Signed images are packages consumed directly by the firmware,
+ * with the exception of MC firmware, where the image must be
+ * rearranged for booting purposes.
+ */
+ if (format == EFX_IMAGE_FORMAT_SIGNED) {
+ if (headerp->eih_type != FIRMWARE_TYPE_MCFW)
+ format = EFX_IMAGE_FORMAT_SIGNED_PACKAGE;
+ }
+
/* Return image details */
infop->eii_format = format;
infop->eii_imagep = bufferp;
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 4905918..d46e650 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1889,6 +1889,7 @@ enum {
EFX_IMAGE_FORMAT_INVALID,
EFX_IMAGE_FORMAT_UNSIGNED,
EFX_IMAGE_FORMAT_SIGNED,
+ EFX_IMAGE_FORMAT_SIGNED_PACKAGE
} efx_image_format_t;
typedef struct efx_image_info_s {
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 13/29] net/sfc/base: transition to the extensible NVRAM info API
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (11 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 12/29] net/sfc/base: support direct FW update for bundle partitions Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 14/29] net/sfc/base: add background mode firmware updating Andrew Rybchenko
` (16 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Old NVRAM info API required function prototype too often.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nvram.c | 20 +++++++++++++-------
drivers/net/sfc/base/ef10_vpd.c | 7 +++++--
drivers/net/sfc/base/efx_impl.h | 9 ---------
drivers/net/sfc/base/efx_nvram.c | 38 +-------------------------------------
drivers/net/sfc/base/siena_nvram.c | 9 +++++----
5 files changed, 24 insertions(+), 59 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_nvram.c b/drivers/net/sfc/base/ef10_nvram.c
index a618c75..1fb7185 100644
--- a/drivers/net/sfc/base/ef10_nvram.c
+++ b/drivers/net/sfc/base/ef10_nvram.c
@@ -1946,11 +1946,13 @@ static uint32_t checksum_tlv_partition(
__out size_t *sizep)
{
efx_rc_t rc;
+ efx_nvram_info_t eni = { 0 };
- if ((rc = efx_mcdi_nvram_info(enp, partn, sizep,
- NULL, NULL, NULL)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail1;
+ *sizep = eni.eni_partn_size;
+
return (0);
fail1:
@@ -1967,7 +1969,7 @@ static uint32_t checksum_tlv_partition(
{
efx_rc_t rc;
- if ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, enip)) != 0)
goto fail1;
if (enip->eni_write_size == 0)
@@ -2080,12 +2082,14 @@ static uint32_t checksum_tlv_partition(
__in size_t size)
{
efx_rc_t rc;
+ efx_nvram_info_t eni = { 0 };
uint32_t erase_size;
- if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL,
- &erase_size, NULL)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail1;
+ erase_size = eni.eni_erase_size;
+
if (erase_size == 0) {
if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0)
goto fail2;
@@ -2126,13 +2130,15 @@ static uint32_t checksum_tlv_partition(
__in size_t size)
{
size_t chunk;
+ efx_nvram_info_t eni = { 0 };
uint32_t write_size;
efx_rc_t rc;
- if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL,
- NULL, &write_size)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail1;
+ write_size = eni.eni_write_size;
+
if (write_size != 0) {
/*
* Check that the size is a multiple of the write chunk size if
diff --git a/drivers/net/sfc/base/ef10_vpd.c b/drivers/net/sfc/base/ef10_vpd.c
index d56747b..c641936 100644
--- a/drivers/net/sfc/base/ef10_vpd.c
+++ b/drivers/net/sfc/base/ef10_vpd.c
@@ -79,6 +79,7 @@
__out size_t *sizep)
{
efx_rc_t rc;
+ efx_nvram_info_t eni = { 0 };
EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
@@ -88,10 +89,12 @@
* so we just need to return an upper bound on the dynamic vpd,
* which is the size of the DYNAMIC_CONFIG partition.
*/
- if ((rc = efx_mcdi_nvram_info(enp, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,
- sizep, NULL, NULL, NULL)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp,
+ NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, &eni)) != 0)
goto fail1;
+ *sizep = eni.eni_partn_size;
+
return (0);
fail1:
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 577d5aa..d8cadda 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -563,15 +563,6 @@
efx_mcdi_nvram_info(
__in efx_nic_t *enp,
__in uint32_t partn,
- __out_opt size_t *sizep,
- __out_opt uint32_t *addressp,
- __out_opt uint32_t *erase_sizep,
- __out_opt uint32_t *write_sizep);
-
- __checkReturn efx_rc_t
-efx_mcdi_nvram_info_ex(
- __in efx_nic_t *enp,
- __in uint32_t partn,
__out efx_nvram_info_t *eni);
__checkReturn efx_rc_t
diff --git a/drivers/net/sfc/base/efx_nvram.c b/drivers/net/sfc/base/efx_nvram.c
index b817cb6..74dac41 100644
--- a/drivers/net/sfc/base/efx_nvram.c
+++ b/drivers/net/sfc/base/efx_nvram.c
@@ -691,7 +691,7 @@
}
__checkReturn efx_rc_t
-efx_mcdi_nvram_info_ex(
+efx_mcdi_nvram_info(
__in efx_nic_t *enp,
__in uint32_t partn,
__out efx_nvram_info_t *enip)
@@ -752,42 +752,6 @@
return (rc);
}
- __checkReturn efx_rc_t
-efx_mcdi_nvram_info(
- __in efx_nic_t *enp,
- __in uint32_t partn,
- __out_opt size_t *sizep,
- __out_opt uint32_t *addressp,
- __out_opt uint32_t *erase_sizep,
- __out_opt uint32_t *write_sizep)
-{
- efx_nvram_info_t eni;
- efx_rc_t rc;
-
- if ((rc = efx_mcdi_nvram_info_ex(enp, partn, &eni)) != 0)
- goto fail1;
-
- if (sizep)
- *sizep = eni.eni_partn_size;
-
- if (addressp)
- *addressp = eni.eni_address;
-
- if (erase_sizep)
- *erase_sizep = eni.eni_erase_size;
-
- if (write_sizep)
- *write_sizep = eni.eni_write_size;
-
- return (0);
-
-fail1:
- EFSYS_PROBE1(fail1, efx_rc_t, rc);
-
- return (rc);
-}
-
-
/*
* MC_CMD_NVRAM_UPDATE_START_V2 must be used to support firmware-verified
* NVRAM updates. Older firmware will ignore the flags field in the request.
diff --git a/drivers/net/sfc/base/siena_nvram.c b/drivers/net/sfc/base/siena_nvram.c
index 7d423d2..47a8ca2 100644
--- a/drivers/net/sfc/base/siena_nvram.c
+++ b/drivers/net/sfc/base/siena_nvram.c
@@ -18,16 +18,17 @@
__out size_t *sizep)
{
efx_rc_t rc;
+ efx_nvram_info_t eni = { 0 };
if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
rc = ENOTSUP;
goto fail1;
}
- if ((rc = efx_mcdi_nvram_info(enp, partn, sizep,
- NULL, NULL, NULL)) != 0) {
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail2;
- }
+
+ *sizep = eni.eni_partn_size;
return (0);
@@ -47,7 +48,7 @@
{
efx_rc_t rc;
- if ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, enip)) != 0)
goto fail1;
if (enip->eni_write_size == 0)
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 14/29] net/sfc/base: add background mode firmware updating
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (12 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 13/29] net/sfc/base: transition to the extensible NVRAM info API Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 15/29] net/sfc/base: add definition of bundle metadata partition Andrew Rybchenko
` (15 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Richard Houldsworth
From: Richard Houldsworth <rhouldsworth@solarflare.com>
Request firmware updates be performed in background mode.
In this mode MCDI to the function processing the update
remains accessible and the client polls for completion.
This is supported for lengthy partition updates such as
MCFW and bundles. The MC ignores the flags used for this
mode for other partition updates.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 5 ++++
drivers/net/sfc/base/ef10_nvram.c | 55 ++++++++++++++++++++++++++++++++++----
drivers/net/sfc/base/efx.h | 2 ++
drivers/net/sfc/base/efx_impl.h | 4 +++
drivers/net/sfc/base/efx_nvram.c | 30 +++++++++++++++------
drivers/net/sfc/base/siena_nvram.c | 4 ++-
6 files changed, 86 insertions(+), 14 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 27508e1..4c90e10 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1216,6 +1216,11 @@
else
encp->enc_nvram_update_verify_result_supported = B_FALSE;
+ if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT))
+ encp->enc_nvram_update_poll_verify_result_supported = B_TRUE;
+ else
+ encp->enc_nvram_update_poll_verify_result_supported = B_FALSE;
+
/*
* Check if firmware update via the BUNDLE partition is supported
*/
diff --git a/drivers/net/sfc/base/ef10_nvram.c b/drivers/net/sfc/base/ef10_nvram.c
index 1fb7185..ed88e83 100644
--- a/drivers/net/sfc/base/ef10_nvram.c
+++ b/drivers/net/sfc/base/ef10_nvram.c
@@ -2177,6 +2177,10 @@ static uint32_t checksum_tlv_partition(
return (rc);
}
+#define EF10_NVRAM_INITIAL_POLL_DELAY_US 10000
+#define EF10_NVRAM_MAX_POLL_DELAY_US 1000000
+#define EF10_NVRAM_POLL_RETRIES 100
+
__checkReturn efx_rc_t
ef10_nvram_partn_unlock(
__in efx_nic_t *enp,
@@ -2184,17 +2188,58 @@ static uint32_t checksum_tlv_partition(
__out_opt uint32_t *verify_resultp)
{
boolean_t reboot = B_FALSE;
+ uint32_t poll_delay_us = EF10_NVRAM_INITIAL_POLL_DELAY_US;
+ uint32_t poll_retry = 0;
+ uint32_t verify_result = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
efx_rc_t rc;
- if (verify_resultp != NULL)
- *verify_resultp = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
+ rc = efx_mcdi_nvram_update_finish(enp, partn, reboot,
+ EFX_NVRAM_UPDATE_FLAGS_BACKGROUND, &verify_result);
- rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, verify_resultp);
- if (rc != 0)
- goto fail1;
+ /*
+ * NVRAM updates can take a long time (e.g. up to 1 minute for bundle
+ * images). Polling for NVRAM update completion ensures that other MCDI
+ * commands can be issued before the background NVRAM update completes.
+ *
+ * Without polling, other MCDI commands can only be issued before the
+ * NVRAM update completes if the MCDI transport and the firmware
+ * support the Asynchronous MCDI protocol extensions in SF-116575-PS.
+ *
+ * The initial call either completes the update synchronously, or
+ * returns RC_PENDING to indicate processing is continuing. In the
+ * latter case, we poll for at least 1 minute, at increasing intervals
+ * (10ms, 100ms, 1s).
+ */
+ while (verify_result == MC_CMD_NVRAM_VERIFY_RC_PENDING) {
+
+ if (poll_retry > EF10_NVRAM_POLL_RETRIES) {
+ rc = ETIMEDOUT;
+ goto fail1;
+ }
+ poll_retry++;
+
+ EFSYS_SLEEP(poll_delay_us);
+ if (poll_delay_us < EF10_NVRAM_MAX_POLL_DELAY_US)
+ poll_delay_us *= 10;
+
+ /* Poll for completion of background NVRAM update. */
+ verify_result = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
+
+ rc = efx_mcdi_nvram_update_finish(enp, partn, reboot,
+ EFX_NVRAM_UPDATE_FLAGS_POLL, &verify_result);
+ if (rc != 0) {
+ /* Poll failed, so assume NVRAM update failed. */
+ goto fail2;
+ }
+ }
+
+ if (verify_resultp != NULL)
+ *verify_resultp = verify_result;
return (0);
+fail2:
+ EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index d46e650..4385379 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1395,6 +1395,8 @@ enum {
uint32_t enc_max_pcie_link_gen;
/* Firmware verifies integrity of NVRAM updates */
boolean_t enc_nvram_update_verify_result_supported;
+ /* Firmware supports polled NVRAM updates on select partitions */
+ boolean_t enc_nvram_update_poll_verify_result_supported;
/* Firmware accepts updates via the BUNDLE partition */
boolean_t enc_nvram_bundle_update_supported;
/* Firmware support for extended MAC_STATS buffer */
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index d8cadda..067cec3 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -594,11 +594,15 @@
__in_bcount(size) caddr_t data,
__in size_t size);
+#define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001
+#define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002
+
__checkReturn efx_rc_t
efx_mcdi_nvram_update_finish(
__in efx_nic_t *enp,
__in uint32_t partn,
__in boolean_t reboot,
+ __in uint32_t flags,
__out_opt uint32_t *verify_resultp);
#if EFSYS_OPT_DIAG
diff --git a/drivers/net/sfc/base/efx_nvram.c b/drivers/net/sfc/base/efx_nvram.c
index 74dac41..5e7236c 100644
--- a/drivers/net/sfc/base/efx_nvram.c
+++ b/drivers/net/sfc/base/efx_nvram.c
@@ -965,6 +965,7 @@
__in efx_nic_t *enp,
__in uint32_t partn,
__in boolean_t reboot,
+ __in uint32_t flags,
__out_opt uint32_t *verify_resultp)
{
const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
@@ -972,7 +973,7 @@
EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN,
MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN);
uint32_t verify_result = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
- efx_rc_t rc;
+ efx_rc_t rc = 0;
req.emr_cmd = MC_CMD_NVRAM_UPDATE_FINISH;
req.emr_in_buf = payload;
@@ -983,8 +984,19 @@
MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_V2_IN_TYPE, partn);
MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_V2_IN_REBOOT, reboot);
- MCDI_IN_POPULATE_DWORD_1(req, NVRAM_UPDATE_FINISH_V2_IN_FLAGS,
- NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT, 1);
+ if (!encp->enc_nvram_update_poll_verify_result_supported) {
+ flags &= ~EFX_NVRAM_UPDATE_FLAGS_BACKGROUND;
+ flags &= ~EFX_NVRAM_UPDATE_FLAGS_POLL;
+ }
+
+ MCDI_IN_POPULATE_DWORD_3(req, NVRAM_UPDATE_FINISH_V2_IN_FLAGS,
+ NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT,
+ 1,
+ NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND,
+ (flags & EFX_NVRAM_UPDATE_FLAGS_BACKGROUND) ? 1 : 0,
+ NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT,
+ (flags & EFX_NVRAM_UPDATE_FLAGS_POLL) ? 1 : 0
+ );
efx_mcdi_execute(enp, &req);
@@ -1005,11 +1017,13 @@
MCDI_OUT_DWORD(req, NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE);
}
- if ((encp->enc_nvram_update_verify_result_supported) &&
- (verify_result != MC_CMD_NVRAM_VERIFY_RC_SUCCESS)) {
- /* Update verification failed */
- rc = EINVAL;
- goto fail3;
+ if (encp->enc_nvram_update_verify_result_supported) {
+ if ((verify_result != MC_CMD_NVRAM_VERIFY_RC_SUCCESS) &&
+ (verify_result != MC_CMD_NVRAM_VERIFY_RC_PENDING)) {
+ /* Update verification failed */
+ rc = EINVAL;
+ goto fail3;
+ }
}
if (verify_resultp != NULL)
diff --git a/drivers/net/sfc/base/siena_nvram.c b/drivers/net/sfc/base/siena_nvram.c
index 47a8ca2..51e601e 100644
--- a/drivers/net/sfc/base/siena_nvram.c
+++ b/drivers/net/sfc/base/siena_nvram.c
@@ -174,6 +174,7 @@
__out_opt uint32_t *verify_resultp)
{
boolean_t reboot;
+ uint32_t flags = 0;
efx_rc_t rc;
/*
@@ -184,7 +185,8 @@
partn == MC_CMD_NVRAM_TYPE_PHY_PORT1 ||
partn == MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO);
- rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, verify_resultp);
+ rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, flags,
+ verify_resultp);
if (rc != 0)
goto fail1;
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 15/29] net/sfc/base: add definition of bundle metadata partition
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (13 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 14/29] net/sfc/base: add background mode firmware updating Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 16/29] net/sfc/base: add definition of OEM TLV Andrew Rybchenko
` (14 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Paul Fox
From: Paul Fox <pfox@solarflare.com>
Signed-off-by: Paul Fox <pfox@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nvram.c | 1 +
drivers/net/sfc/base/ef10_tlv_layout.h | 25 +++++++++++++++++++++++++
drivers/net/sfc/base/efx.h | 1 +
3 files changed, 27 insertions(+)
diff --git a/drivers/net/sfc/base/ef10_nvram.c b/drivers/net/sfc/base/ef10_nvram.c
index ed88e83..8fc8fd9 100644
--- a/drivers/net/sfc/base/ef10_nvram.c
+++ b/drivers/net/sfc/base/ef10_nvram.c
@@ -2344,6 +2344,7 @@ static uint32_t checksum_tlv_partition(
PARTN_MAP_ENTRY(DYNCONFIG_DEFAULTS, ALL, DYNCONFIG_DEFAULTS),
PARTN_MAP_ENTRY(ROMCONFIG_DEFAULTS, ALL, ROMCONFIG_DEFAULTS),
PARTN_MAP_ENTRY(BUNDLE, ALL, BUNDLE),
+ PARTN_MAP_ENTRY(BUNDLE_METADATA, ALL, BUNDLE_METADATA),
};
static __checkReturn efx_rc_t
diff --git a/drivers/net/sfc/base/ef10_tlv_layout.h b/drivers/net/sfc/base/ef10_tlv_layout.h
index eaf24c5..bb1539f 100644
--- a/drivers/net/sfc/base/ef10_tlv_layout.h
+++ b/drivers/net/sfc/base/ef10_tlv_layout.h
@@ -41,6 +41,7 @@
* 2: firmware internal use
* 3: license partition
* 4: tsa configuration
+ * 5: bundle update
*
* - TTT is a type, which is just a unique value. The same type value
* might appear in both locations, indicating a relationship between
@@ -86,6 +87,30 @@
#define TLV_TAG_INVALID (0xFFFFFFFF)
+/* TLV start.
+ *
+ * Marks the start of a TLV layout within a partition that may/may-not be
+ * a TLV partition. i.e. if a portion of data (at any offset) within a
+ * partition is expected to be in TLV format, then the first tag in this
+ * layout is expected to be TLV_TAG_START.
+ *
+ * This tag is not used in TLV layouts where the entire partition is TLV.
+ * Please continue using TLV_TAG_PARTITION_HEADER to indicate the start
+ * of TLV layout in such cases.
+ */
+
+#define TLV_TAG_START (0xEF10BA5E)
+
+struct tlv_start {
+ uint32_t tag;
+ uint32_t length;
+ /* Length of the TLV structure following this tag - includes length of all tags
+ * within the TLV layout starting with this TLV_TAG_START.
+ * Includes TLV_TAG_END. Does not include TLV_TAG_START
+ */
+ uint32_t tlv_layout_len;
+};
+
/* TLV partition header.
*
* In a TLV partition, this must be the first item in the sequence, at offset
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 4385379..6b6538c 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1605,6 +1605,7 @@ enum {
EFX_NVRAM_DYNCONFIG_DEFAULTS,
EFX_NVRAM_ROMCONFIG_DEFAULTS,
EFX_NVRAM_BUNDLE,
+ EFX_NVRAM_BUNDLE_METADATA,
EFX_NVRAM_NTYPES,
} efx_nvram_type_t;
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 16/29] net/sfc/base: add definition of OEM TLV
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (14 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 15/29] net/sfc/base: add definition of bundle metadata partition Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 17/29] net/sfc/base: export the zero-based MCDI port number Andrew Rybchenko
` (13 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Kevin Lampis
From: Kevin Lampis <klampis@solarflare.com>
Allows to enable additional functionality related to this OEM
(e.g. vendor extensions to VPD, NC-SI etc.)
Signed-off-by: Kevin Lampis <klampis@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_tlv_layout.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/sfc/base/ef10_tlv_layout.h b/drivers/net/sfc/base/ef10_tlv_layout.h
index bb1539f..33b6af0 100644
--- a/drivers/net/sfc/base/ef10_tlv_layout.h
+++ b/drivers/net/sfc/base/ef10_tlv_layout.h
@@ -536,6 +536,16 @@ struct tlv_pcie_tx_amp_config {
uint8_t lane_amp[16];
};
+/* Enum to select an OEM and enable additional functionality related to this OEM
+ * (e.g. vendor extensions to VPD, NC-SI etc.) */
+#define TLV_TAG_OEM (0x00230000)
+struct tlv_oem {
+ uint32_t tag;
+ uint32_t length;
+ uint8_t oem;
+};
+#define TLV_OEM_NONE 0
+#define TLV_OEM_DELL 1
/* Global PCIe configuration, second revision. This represents the visible PFs
* by a bitmap rather than having the number of the highest visible one. As such
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 17/29] net/sfc/base: export the zero-based MCDI port number
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (15 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 16/29] net/sfc/base: add definition of OEM TLV Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 18/29] net/sfc/base: introduce of EVB module for SR-IOV support Andrew Rybchenko
` (12 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Proxy authorization module for SR-IOV requires one instance of proxy
data structures per card. In order to achieve this, proxy data
structures will be allocated only for primary port (port id 0) and other
secondary ports in the card will access those data structures through
reference to primary port. Accordingly, the port number obtained from
efx_mcdi_get_port_assignment is stored in NIC configuration as
enc_mcdi_port.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 2 ++
drivers/net/sfc/base/efx.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 4c90e10..8ee8047 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1840,6 +1840,8 @@
/* EFX MCDI interface uses one-based port numbers */
emip->emi_port = port + 1;
+ encp->enc_assigned_port = port;
+
if ((rc = ef10_external_port_mapping(enp, port,
&encp->enc_external_port)) != 0)
goto fail2;
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 6b6538c..40308ff 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1407,6 +1407,8 @@ enum {
boolean_t enc_filter_action_flag_supported;
boolean_t enc_filter_action_mark_supported;
uint32_t enc_filter_action_mark_max;
+ /* Port assigned to this PCI function */
+ uint32_t enc_assigned_port;
} efx_nic_cfg_t;
#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 18/29] net/sfc/base: introduce of EVB module for SR-IOV support
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (16 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 17/29] net/sfc/base: export the zero-based MCDI port number Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 19/29] net/sfc/base: add MCDI wrappers for vPort and vSwitch in EVB Andrew Rybchenko
` (11 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Implement the framework for Enterprise Virtual Briding (EVB) module.
SR-IOV augments the software virtual switch with NIC capbilities
supported from EVB module.
Further patches will add APIs to create and destroy EVB switching
hierarchy required for SR-IOV and APIs to set vPort properties like MAC,
VLAN etc.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/Makefile | 2 +
drivers/net/sfc/base/ef10_evb.c | 35 +++++++++++++
drivers/net/sfc/base/ef10_impl.h | 10 ++++
drivers/net/sfc/base/efx.h | 12 +++++
drivers/net/sfc/base/efx_check.h | 7 +++
drivers/net/sfc/base/efx_evb.c | 110 +++++++++++++++++++++++++++++++++++++++
drivers/net/sfc/base/efx_impl.h | 13 +++++
drivers/net/sfc/base/meson.build | 2 +
drivers/net/sfc/efsys.h | 2 +
9 files changed, 193 insertions(+)
create mode 100644 drivers/net/sfc/base/ef10_evb.c
create mode 100644 drivers/net/sfc/base/efx_evb.c
diff --git a/drivers/net/sfc/Makefile b/drivers/net/sfc/Makefile
index 3bb41a0..7149afd 100644
--- a/drivers/net/sfc/Makefile
+++ b/drivers/net/sfc/Makefile
@@ -89,6 +89,7 @@ VPATH += $(SRCDIR)/base
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_bootcfg.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_crc32.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_ev.c
+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_evb.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_filter.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_hash.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_intr.c
@@ -114,6 +115,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_phy.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_sram.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_vpd.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_ev.c
+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_evb.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_filter.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_intr.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_image.c
diff --git a/drivers/net/sfc/base/ef10_evb.c b/drivers/net/sfc/base/ef10_evb.c
new file mode 100644
index 0000000..03ac19a
--- /dev/null
+++ b/drivers/net/sfc/base/ef10_evb.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2018-2019 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+#include "efx.h"
+#include "efx_impl.h"
+
+#if EFSYS_OPT_EVB
+
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+
+ __checkReturn efx_rc_t
+ef10_evb_init(
+ __in efx_nic_t *enp)
+{
+ EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
+ enp->en_family == EFX_FAMILY_MEDFORD ||
+ enp->en_family == EFX_FAMILY_MEDFORD2);
+
+ return (0);
+}
+
+ void
+ef10_evb_fini(
+ __in efx_nic_t *enp)
+{
+ EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
+ enp->en_family == EFX_FAMILY_MEDFORD ||
+ enp->en_family == EFX_FAMILY_MEDFORD2);
+}
+
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFSYS_OPT_EVB */
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 0cfbf59..26242a1 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1262,6 +1262,16 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
+#if EFSYS_OPT_EVB
+extern __checkReturn efx_rc_t
+ef10_evb_init(
+ __in efx_nic_t *enp);
+
+extern void
+ef10_evb_fini(
+ __in efx_nic_t *enp);
+
+#endif /* EFSYS_OPT_EVB */
#if EFSYS_OPT_RX_PACKED_STREAM
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 40308ff..ca8a399 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3347,6 +3347,18 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__out efx_phy_link_state_t *eplsp);
+#if EFSYS_OPT_EVB
+
+extern __checkReturn efx_rc_t
+efx_evb_init(
+ __in efx_nic_t *enp);
+
+extern void
+efx_evb_fini(
+ __in efx_nic_t *enp);
+
+#endif /* EFSYS_OPT_EVB */
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/net/sfc/base/efx_check.h b/drivers/net/sfc/base/efx_check.h
index 4800f77..85edaef 100644
--- a/drivers/net/sfc/base/efx_check.h
+++ b/drivers/net/sfc/base/efx_check.h
@@ -351,4 +351,11 @@
# endif
#endif
+#if EFSYS_OPT_EVB
+/* Support enterprise virtual bridging */
+# if !(EFX_OPTS_EF10())
+# error "EVB requires EF10 arch"
+# endif
+#endif /* EFSYS_OPT_EVB */
+
#endif /* _SYS_EFX_CHECK_H */
diff --git a/drivers/net/sfc/base/efx_evb.c b/drivers/net/sfc/base/efx_evb.c
new file mode 100644
index 0000000..f235252
--- /dev/null
+++ b/drivers/net/sfc/base/efx_evb.c
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2018-2019 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+#include "efx.h"
+#include "efx_impl.h"
+
+
+#if EFSYS_OPT_EVB
+
+#if EFSYS_OPT_SIENA
+static const efx_evb_ops_t __efx_evb_dummy_ops = {
+ NULL, /* eeo_init */
+ NULL, /* eeo_fini */
+};
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+static const efx_evb_ops_t __efx_evb_ef10_ops = {
+ ef10_evb_init, /* eeo_init */
+ ef10_evb_fini, /* eeo_fini */
+};
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+
+ __checkReturn efx_rc_t
+efx_evb_init(
+ __in efx_nic_t *enp)
+{
+ const efx_evb_ops_t *eeop;
+ efx_rc_t rc;
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EVB));
+
+ switch (enp->en_family) {
+#if EFSYS_OPT_SIENA
+ case EFX_FAMILY_SIENA:
+ eeop = &__efx_evb_dummy_ops;
+ break;
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+ case EFX_FAMILY_HUNTINGTON:
+ eeop = &__efx_evb_ef10_ops;
+ break;
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+#if EFSYS_OPT_MEDFORD
+ case EFX_FAMILY_MEDFORD:
+ eeop = &__efx_evb_ef10_ops;
+ break;
+#endif /* EFSYS_OPT_MEDFORD */
+
+#if EFSYS_OPT_MEDFORD2
+ case EFX_FAMILY_MEDFORD2:
+ eeop = &__efx_evb_ef10_ops;
+ break;
+#endif /* EFSYS_OPT_MEDFORD2 */
+
+ default:
+ EFSYS_ASSERT(0);
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if (!encp->enc_datapath_cap_evb || !eeop->eeo_init) {
+ rc = ENOTSUP;
+ goto fail2;
+ }
+
+ if ((rc = eeop->eeo_init(enp)) != 0)
+ goto fail3;
+
+ enp->en_eeop = eeop;
+ enp->en_mod_flags |= EFX_MOD_EVB;
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+ void
+efx_evb_fini(
+ __in efx_nic_t *enp)
+{
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
+ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
+ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
+
+ if (eeop && eeop->eeo_fini)
+ eeop->eeo_fini(enp);
+
+ enp->en_eeop = NULL;
+ enp->en_mod_flags &= ~EFX_MOD_EVB;
+}
+
+#endif
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 067cec3..00f88c8 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -58,6 +58,7 @@
#define EFX_MOD_FILTER 0x00001000
#define EFX_MOD_LIC 0x00002000
#define EFX_MOD_TUNNEL 0x00004000
+#define EFX_MOD_EVB 0x00008000
#define EFX_RESET_PHY 0x00000001
#define EFX_RESET_RXQ_ERR 0x00000002
@@ -649,6 +650,15 @@
#endif
+#if EFSYS_OPT_EVB
+
+typedef struct efx_evb_ops_s {
+ efx_rc_t (*eeo_init)(efx_nic_t *);
+ void (*eeo_fini)(efx_nic_t *);
+} efx_evb_ops_t;
+
+#endif /* EFSYS_OPT_EVB */
+
#define EFX_DRV_VER_MAX 20
typedef struct efx_drv_cfg_s {
@@ -747,6 +757,9 @@ struct efx_nic_s {
} ef10;
} en_arch;
#endif /* EFX_OPTS_EF10() */
+#if EFSYS_OPT_EVB
+ const efx_evb_ops_t *en_eeop;
+#endif /* EFSYS_OPT_EVB */
};
#define EFX_FAMILY_IS_EF10(_enp) \
diff --git a/drivers/net/sfc/base/meson.build b/drivers/net/sfc/base/meson.build
index ab66f32..6fa7948 100644
--- a/drivers/net/sfc/base/meson.build
+++ b/drivers/net/sfc/base/meson.build
@@ -8,6 +8,7 @@ sources = [
'efx_bootcfg.c',
'efx_crc32.c',
'efx_ev.c',
+ 'efx_evb.c',
'efx_filter.c',
'efx_hash.c',
'efx_intr.c',
@@ -33,6 +34,7 @@ sources = [
'siena_sram.c',
'siena_vpd.c',
'ef10_ev.c',
+ 'ef10_evb.c',
'ef10_filter.c',
'ef10_image.c',
'ef10_intr.c',
diff --git a/drivers/net/sfc/efsys.h b/drivers/net/sfc/efsys.h
index f7bcc74..24f3769 100644
--- a/drivers/net/sfc/efsys.h
+++ b/drivers/net/sfc/efsys.h
@@ -166,6 +166,8 @@
#define EFSYS_OPT_FW_SUBVARIANT_AWARE 1
+#define EFSYS_OPT_EVB 0
+
/* ID */
typedef struct __efsys_identifier_s efsys_identifier_t;
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 19/29] net/sfc/base: add MCDI wrappers for vPort and vSwitch in EVB
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (17 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 18/29] net/sfc/base: introduce of EVB module for SR-IOV support Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 20/29] net/sfc/base: add EVB module vSwitch/vPort/vAdaptor ops Andrew Rybchenko
` (10 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Add the functions to implement the vPort and vSwitch MCDI calls.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_evb.c | 299 ++++++++++++++++++++++++++++++++++++++++
drivers/net/sfc/base/efx.h | 18 +++
2 files changed, 317 insertions(+)
diff --git a/drivers/net/sfc/base/ef10_evb.c b/drivers/net/sfc/base/ef10_evb.c
index 03ac19a..18cecc2 100644
--- a/drivers/net/sfc/base/ef10_evb.c
+++ b/drivers/net/sfc/base/ef10_evb.c
@@ -31,5 +31,304 @@
enp->en_family == EFX_FAMILY_MEDFORD2);
}
+ __checkReturn efx_rc_t
+efx_mcdi_vswitch_alloc(
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in efx_vswitch_type_t vswitch_type)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VSWITCH_ALLOC_IN_LEN,
+ MC_CMD_VSWITCH_ALLOC_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+ uint8_t ntags;
+
+ /* Ensure EFX and MCDI use same values for vswitch types */
+ EFX_STATIC_ASSERT(EFX_VSWITCH_TYPE_VLAN ==
+ MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN);
+ EFX_STATIC_ASSERT(EFX_VSWITCH_TYPE_VEB ==
+ MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB);
+ EFX_STATIC_ASSERT(EFX_VSWITCH_TYPE_MUX ==
+ MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX);
+
+ /* First try with maximum number of VLAN tags FW supports */
+ ntags = 2;
+retry:
+ req.emr_cmd = MC_CMD_VSWITCH_ALLOC;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VSWITCH_ALLOC_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VSWITCH_ALLOC_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID, vport_id);
+ MCDI_IN_SET_DWORD(req, VSWITCH_ALLOC_IN_TYPE, vswitch_type);
+ MCDI_IN_SET_DWORD(req, VSWITCH_ALLOC_IN_NUM_VLAN_TAGS, ntags);
+ MCDI_IN_POPULATE_DWORD_1(req, VSWITCH_ALLOC_IN_FLAGS,
+ VSWITCH_ALLOC_IN_FLAG_AUTO_PORT, 0);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ /*
+ * efx_rc_t error codes in libefx are translated from MCDI
+ * error codes in efx_mcdi_request_errcode. As this conversion
+ * is not a 1:1, here we check the specific MCDI error code.
+ */
+ if (req.emr_err_code == MC_CMD_ERR_VLAN_LIMIT) {
+ /* Too many VLAN tags, retry with fewer */
+ EFSYS_PROBE(vlan_limit);
+ ntags--;
+ if (ntags > 0) {
+ /*
+ * Zero the buffer before reusing it
+ * for another request
+ */
+ memset(payload, 0, sizeof (payload));
+ goto retry;
+ }
+ goto fail1;
+ }
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mcdi_vswitch_free(
+ __in efx_nic_t *enp)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VSWITCH_FREE_IN_LEN,
+ MC_CMD_VSWITCH_FREE_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_VSWITCH_FREE;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VSWITCH_FREE_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VSWITCH_FREE_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VSWITCH_FREE_IN_UPSTREAM_PORT_ID,
+ EVB_PORT_ID_ASSIGNED);
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mcdi_vport_alloc(
+ __in efx_nic_t *enp,
+ __in efx_vport_type_t vport_type,
+ __in uint16_t vid,
+ __in boolean_t vlan_restrict,
+ __out efx_vport_id_t *vport_idp)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_ALLOC_IN_LEN,
+ MC_CMD_VPORT_ALLOC_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ /* Ensure EFX and MCDI use same values for vport types */
+ EFX_STATIC_ASSERT(EFX_VPORT_TYPE_NORMAL ==
+ MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL);
+ EFX_STATIC_ASSERT(EFX_VPORT_TYPE_EXPANSION ==
+ MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION);
+ EFX_STATIC_ASSERT(EFX_VPORT_TYPE_TEST ==
+ MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST);
+
+ req.emr_cmd = MC_CMD_VPORT_ALLOC;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VPORT_ALLOC_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VPORT_ALLOC_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VPORT_ALLOC_IN_UPSTREAM_PORT_ID,
+ EVB_PORT_ID_ASSIGNED);
+ MCDI_IN_SET_DWORD(req, VPORT_ALLOC_IN_TYPE, vport_type);
+ MCDI_IN_SET_DWORD(req, VPORT_ALLOC_IN_NUM_VLAN_TAGS,
+ (vid != EFX_FILTER_VID_UNSPEC));
+
+ MCDI_IN_POPULATE_DWORD_2(req, VPORT_ALLOC_IN_FLAGS,
+ VPORT_ALLOC_IN_FLAG_AUTO_PORT, 0,
+ VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT, vlan_restrict);
+
+ if (vid != EFX_FILTER_VID_UNSPEC)
+ MCDI_IN_POPULATE_DWORD_1(req, VPORT_ALLOC_IN_VLAN_TAGS,
+ VPORT_ALLOC_IN_VLAN_TAG_0, vid);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ if (req.emr_out_length_used < MC_CMD_VPORT_ALLOC_OUT_LEN) {
+ rc = EMSGSIZE;
+ goto fail2;
+ }
+
+ *vport_idp = *MCDI_OUT2(req, uint32_t, VPORT_ALLOC_OUT_VPORT_ID);
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mcdi_vport_free(
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_FREE_IN_LEN,
+ MC_CMD_VPORT_FREE_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_VPORT_FREE;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VPORT_FREE_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VPORT_FREE_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VPORT_FREE_IN_VPORT_ID, vport_id);
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mcdi_vport_mac_addr_add(
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in_ecount(6) uint8_t *addrp)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN,
+ MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_VPORT_ADD_MAC_ADDRESS;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, vport_id);
+ EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t,
+ VPORT_ADD_MAC_ADDRESS_IN_MACADDR), addrp);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mcdi_vport_mac_addr_del(
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in_ecount(6) uint8_t *addrp)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN,
+ MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_VPORT_DEL_MAC_ADDRESS;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, vport_id);
+ EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t,
+ VPORT_DEL_MAC_ADDRESS_IN_MACADDR), addrp);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mcdi_port_assign(
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in uint32_t vf_index)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_EVB_PORT_ASSIGN_IN_LEN,
+ MC_CMD_EVB_PORT_ASSIGN_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_EVB_PORT_ASSIGN;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_EVB_PORT_ASSIGN_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_EVB_PORT_ASSIGN_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, EVB_PORT_ASSIGN_IN_PORT_ID, vport_id);
+ MCDI_IN_POPULATE_DWORD_2(req, EVB_PORT_ASSIGN_IN_FUNCTION,
+ EVB_PORT_ASSIGN_IN_PF, encp->enc_pf,
+ EVB_PORT_ASSIGN_IN_VF, vf_index);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return 0;
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
#endif /* EFSYS_OPT_EVB */
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index ca8a399..1287505 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3349,6 +3349,24 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
#if EFSYS_OPT_EVB
+typedef uint32_t efx_vport_id_t;
+
+typedef enum efx_vswitch_type_e {
+ EFX_VSWITCH_TYPE_VLAN = 1,
+ EFX_VSWITCH_TYPE_VEB,
+ /* VSWITCH_TYPE_VEPA: obsolete */
+ EFX_VSWITCH_TYPE_MUX = 4,
+} efx_vswitch_type_t;
+
+typedef enum efx_vport_type_e {
+ EFX_VPORT_TYPE_NORMAL = 4,
+ EFX_VPORT_TYPE_EXPANSION,
+ EFX_VPORT_TYPE_TEST,
+} efx_vport_type_t;
+
+/* Unspecified VLAN ID to support disabling of VLAN filtering */
+#define EFX_FILTER_VID_UNSPEC 0xffff
+
extern __checkReturn efx_rc_t
efx_evb_init(
__in efx_nic_t *enp);
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 20/29] net/sfc/base: add EVB module vSwitch/vPort/vAdaptor ops
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (18 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 19/29] net/sfc/base: add MCDI wrappers for vPort and vSwitch in EVB Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 21/29] net/sfc/base: implement vSwitch create/destroy Andrew Rybchenko
` (9 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Implement functions to allocate and free vSwitch, vPort and vAdaptor.
Also, implement functions to add and delete vPort MAC address and EVB
port assign.
Most of the efx_evb_ops_t functions take vSwitch ID as a parameter for
future enhancements. Currently, firmware doesn't implement vSwitch
identifier and hence this paramter is unused for EF10 architecture
implementation.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_evb.c | 147 +++++++++++++++++++++++++++++++++++----
drivers/net/sfc/base/ef10_impl.h | 73 ++++++++++++++++++-
drivers/net/sfc/base/ef10_nic.c | 4 +-
drivers/net/sfc/base/efx.h | 6 +-
drivers/net/sfc/base/efx_evb.c | 24 ++++++-
drivers/net/sfc/base/efx_impl.h | 17 +++++
6 files changed, 251 insertions(+), 20 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_evb.c b/drivers/net/sfc/base/ef10_evb.c
index 18cecc2..aaa97f6 100644
--- a/drivers/net/sfc/base/ef10_evb.c
+++ b/drivers/net/sfc/base/ef10_evb.c
@@ -163,12 +163,12 @@
(vid != EFX_FILTER_VID_UNSPEC));
MCDI_IN_POPULATE_DWORD_2(req, VPORT_ALLOC_IN_FLAGS,
- VPORT_ALLOC_IN_FLAG_AUTO_PORT, 0,
- VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT, vlan_restrict);
+ VPORT_ALLOC_IN_FLAG_AUTO_PORT, 0,
+ VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT, vlan_restrict);
if (vid != EFX_FILTER_VID_UNSPEC)
MCDI_IN_POPULATE_DWORD_1(req, VPORT_ALLOC_IN_VLAN_TAGS,
- VPORT_ALLOC_IN_VLAN_TAG_0, vid);
+ VPORT_ALLOC_IN_VLAN_TAG_0, vid);
efx_mcdi_execute(enp, &req);
@@ -223,11 +223,11 @@
return (rc);
}
- __checkReturn efx_rc_t
+ __checkReturn efx_rc_t
efx_mcdi_vport_mac_addr_add(
- __in efx_nic_t *enp,
- __in efx_vport_id_t vport_id,
- __in_ecount(6) uint8_t *addrp)
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp)
{
EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN,
MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN);
@@ -258,11 +258,11 @@
return (rc);
}
- __checkReturn efx_rc_t
+ __checkReturn efx_rc_t
efx_mcdi_vport_mac_addr_del(
- __in efx_nic_t *enp,
- __in efx_vport_id_t vport_id,
- __in_ecount(6) uint8_t *addrp)
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp)
{
EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN,
MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN);
@@ -323,12 +323,135 @@
goto fail1;
}
- return 0;
+ return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
+ __checkReturn efx_rc_t
+ef10_evb_vswitch_alloc(
+ __in efx_nic_t *enp,
+ __out efx_vswitch_id_t *vswitch_idp)
+{
+ efx_rc_t rc;
+ if (vswitch_idp == NULL) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ if ((rc = efx_mcdi_vswitch_alloc(enp, EVB_PORT_ID_ASSIGNED,
+ EFX_VSWITCH_TYPE_VEB)) != 0) {
+ goto fail2;
+ }
+
+ *vswitch_idp = EFX_DEFAULT_VSWITCH_ID;
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vswitch_free(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_vswitch_free(enp));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vport_alloc(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_type_t vport_type,
+ __in uint16_t vid,
+ __in boolean_t vlan_restrict,
+ __out efx_vport_id_t *vport_idp)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_vport_alloc(enp,
+ vport_type, vid,
+ vlan_restrict, vport_idp));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vport_free(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_vport_free(enp, vport_id));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vport_mac_addr_add(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+ EFSYS_ASSERT(addrp != NULL);
+
+ return (efx_mcdi_vport_mac_addr_add(enp, vport_id, addrp));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vport_mac_addr_del(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+ EFSYS_ASSERT(addrp != NULL);
+
+ return (efx_mcdi_vport_mac_addr_del(enp, vport_id, addrp));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vadaptor_alloc(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_vadaptor_alloc(enp, vport_id));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vadaptor_free(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_vadaptor_free(enp, vport_id));
+}
+
+ __checkReturn efx_rc_t
+ef10_evb_vport_assign(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in uint32_t vf_index)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_port_assign(enp, vport_id, vf_index));
+}
+
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
#endif /* EFSYS_OPT_EVB */
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 26242a1..e261487 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -195,6 +195,16 @@
/* NIC */
extern __checkReturn efx_rc_t
+efx_mcdi_vadaptor_alloc(
+ __in efx_nic_t *enp,
+ __in uint32_t port_id);
+
+extern __checkReturn efx_rc_t
+efx_mcdi_vadaptor_free(
+ __in efx_nic_t *enp,
+ __in uint32_t port_id);
+
+extern __checkReturn efx_rc_t
ef10_nic_probe(
__in efx_nic_t *enp);
@@ -1267,10 +1277,71 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
ef10_evb_init(
__in efx_nic_t *enp);
-extern void
+extern void
ef10_evb_fini(
__in efx_nic_t *enp);
+extern __checkReturn efx_rc_t
+ef10_evb_vswitch_alloc(
+ __in efx_nic_t *enp,
+ __out efx_vswitch_id_t *vswitch_idp);
+
+
+extern __checkReturn efx_rc_t
+ef10_evb_vswitch_free(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id);
+
+extern __checkReturn efx_rc_t
+ef10_evb_vport_alloc(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_type_t vport_type,
+ __in uint16_t vid,
+ __in boolean_t vlan_restrict,
+ __out efx_vport_id_t *vport_idp);
+
+
+extern __checkReturn efx_rc_t
+ef10_evb_vport_free(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id);
+
+extern __checkReturn efx_rc_t
+ef10_evb_vport_mac_addr_add(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in_ecount(6) uint8_t *addrp);
+
+extern __checkReturn efx_rc_t
+ef10_evb_vport_mac_addr_del(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in_ecount(6) uint8_t *addrp);
+
+extern __checkReturn efx_rc_t
+ef10_evb_vadaptor_alloc(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id);
+
+
+extern __checkReturn efx_rc_t
+ef10_evb_vadaptor_free(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id);
+
+extern __checkReturn efx_rc_t
+ef10_evb_vport_assign(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in uint32_t vf_index);
+
#endif /* EFSYS_OPT_EVB */
#if EFSYS_OPT_RX_PACKED_STREAM
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 8ee8047..7eada57 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -223,7 +223,7 @@
return (rc);
}
-static __checkReturn efx_rc_t
+ __checkReturn efx_rc_t
efx_mcdi_vadaptor_alloc(
__in efx_nic_t *enp,
__in uint32_t port_id)
@@ -261,7 +261,7 @@
return (rc);
}
-static __checkReturn efx_rc_t
+ __checkReturn efx_rc_t
efx_mcdi_vadaptor_free(
__in efx_nic_t *enp,
__in uint32_t port_id)
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 1287505..664efc8 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3349,6 +3349,7 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
#if EFSYS_OPT_EVB
+typedef uint32_t efx_vswitch_id_t;
typedef uint32_t efx_vport_id_t;
typedef enum efx_vswitch_type_e {
@@ -3366,12 +3367,13 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
/* Unspecified VLAN ID to support disabling of VLAN filtering */
#define EFX_FILTER_VID_UNSPEC 0xffff
+#define EFX_DEFAULT_VSWITCH_ID 1
-extern __checkReturn efx_rc_t
+extern __checkReturn efx_rc_t
efx_evb_init(
__in efx_nic_t *enp);
-extern void
+extern void
efx_evb_fini(
__in efx_nic_t *enp);
diff --git a/drivers/net/sfc/base/efx_evb.c b/drivers/net/sfc/base/efx_evb.c
index f235252..ff240f9 100644
--- a/drivers/net/sfc/base/efx_evb.c
+++ b/drivers/net/sfc/base/efx_evb.c
@@ -14,13 +14,31 @@
static const efx_evb_ops_t __efx_evb_dummy_ops = {
NULL, /* eeo_init */
NULL, /* eeo_fini */
+ NULL, /* eeo_vswitch_alloc */
+ NULL, /* eeo_vswitch_free */
+ NULL, /* eeo_vport_alloc */
+ NULL, /* eeo_vport_free */
+ NULL, /* eeo_vport_mac_addr_add */
+ NULL, /* eeo_vport_mac_addr_del */
+ NULL, /* eeo_vadaptor_alloc */
+ NULL, /* eeo_vadaptor_free */
+ NULL, /* eeo_vport_assign */
};
#endif /* EFSYS_OPT_SIENA */
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
static const efx_evb_ops_t __efx_evb_ef10_ops = {
- ef10_evb_init, /* eeo_init */
- ef10_evb_fini, /* eeo_fini */
+ ef10_evb_init, /* eeo_init */
+ ef10_evb_fini, /* eeo_fini */
+ ef10_evb_vswitch_alloc, /* eeo_vswitch_alloc */
+ ef10_evb_vswitch_free, /* eeo_vswitch_free */
+ ef10_evb_vport_alloc, /* eeo_vport_alloc */
+ ef10_evb_vport_free, /* eeo_vport_free */
+ ef10_evb_vport_mac_addr_add, /* eeo_vport_mac_addr_add */
+ ef10_evb_vport_mac_addr_del, /* eeo_vport_mac_addr_del */
+ ef10_evb_vadaptor_alloc, /* eeo_vadaptor_alloc */
+ ef10_evb_vadaptor_free, /* eeo_vadaptor_free */
+ ef10_evb_vport_assign, /* eeo_vport_assign */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
@@ -89,7 +107,7 @@
return (rc);
}
- void
+ void
efx_evb_fini(
__in efx_nic_t *enp)
{
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 00f88c8..ef6a97a 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -655,6 +655,23 @@
typedef struct efx_evb_ops_s {
efx_rc_t (*eeo_init)(efx_nic_t *);
void (*eeo_fini)(efx_nic_t *);
+ efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
+ efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
+ efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_type_t, uint16_t,
+ boolean_t, efx_vport_id_t *);
+ efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t);
+ efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t, uint8_t *);
+ efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t, uint8_t *);
+ efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t);
+ efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t);
+ efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t, uint32_t);
} efx_evb_ops_t;
#endif /* EFSYS_OPT_EVB */
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 21/29] net/sfc/base: implement vSwitch create/destroy
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (19 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 20/29] net/sfc/base: add EVB module vSwitch/vPort/vAdaptor ops Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 22/29] net/sfc/base: factor out upstream port vAdaptor allocation Andrew Rybchenko
` (8 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
The vSwitch create API takes an array of num_vports client driver
allocated vPort config entries where entry at index 0 contains the PF
configuration and rest num_vports-1 entries refer to vPort configuration
for VFs 0 to (num_vports-2). The required hierarchy
(vswitch/vport/vadaptor) is created within this API. The destroy API
tears down this hierarchy and releases memory for the vSwitch object.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/efx.h | 40 ++++++
drivers/net/sfc/base/efx_evb.c | 269 +++++++++++++++++++++++++++++++++++++++-
drivers/net/sfc/base/efx_impl.h | 16 +++
3 files changed, 324 insertions(+), 1 deletion(-)
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 664efc8..492c8c6 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1411,6 +1411,9 @@ enum {
uint32_t enc_assigned_port;
} efx_nic_cfg_t;
+#define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
+ ((configp)->evc_function == 0xffff)
+
#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
@@ -3369,6 +3372,31 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
#define EFX_FILTER_VID_UNSPEC 0xffff
#define EFX_DEFAULT_VSWITCH_ID 1
+/* Default VF VLAN ID on creation */
+#define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
+#define EFX_VPORT_ID_INVALID 0
+
+typedef struct efx_vport_config_s {
+ /* Either VF index or 0xffff for PF */
+ uint16_t evc_function;
+ /* VLAN ID of the associated function */
+ uint16_t evc_vid;
+ /* vport id shared with client driver */
+ efx_vport_id_t evc_vport_id;
+ /* MAC address of the associated function */
+ uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
+ /*
+ * vports created with this flag set may only transfer traffic on the
+ * VLANs permitted by the vport. Also, an attempt to install filter with
+ * VLAN will be refused unless requesting function has VLAN privilege.
+ */
+ boolean_t evc_vlan_restrict;
+ /* Whether this function is assigned or not */
+ boolean_t evc_vport_assigned;
+} efx_vport_config_t;
+
+typedef struct efx_vswitch_s efx_vswitch_t;
+
extern __checkReturn efx_rc_t
efx_evb_init(
__in efx_nic_t *enp);
@@ -3377,6 +3405,18 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
efx_evb_fini(
__in efx_nic_t *enp);
+extern __checkReturn efx_rc_t
+efx_evb_vswitch_create(
+ __in efx_nic_t *enp,
+ __in uint32_t num_vports,
+ __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
+ __deref_out efx_vswitch_t **evpp);
+
+extern __checkReturn efx_rc_t
+efx_evb_vswitch_destroy(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp);
+
#endif /* EFSYS_OPT_EVB */
#ifdef __cplusplus
diff --git a/drivers/net/sfc/base/efx_evb.c b/drivers/net/sfc/base/efx_evb.c
index ff240f9..27b466f 100644
--- a/drivers/net/sfc/base/efx_evb.c
+++ b/drivers/net/sfc/base/efx_evb.c
@@ -107,7 +107,7 @@
return (rc);
}
- void
+ void
efx_evb_fini(
__in efx_nic_t *enp)
{
@@ -125,4 +125,271 @@
enp->en_mod_flags &= ~EFX_MOD_EVB;
}
+/*
+ * efx_is_zero_eth_addr returns TRUE if the passed MAC address has all bytes
+ * equal to zero. A vport is assigned a MAC address after creation and this
+ * function checks if that has happened. It is called in the clean-up function
+ * before calling eeo_vport_mac_addr_del to ensure that the vport actually had
+ * an allocated MAC address.
+ */
+
+__checkReturn boolean_t
+efx_is_zero_eth_addr(
+ __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp)
+{
+ return (!(addrp[0] | addrp[1] | addrp[2] |
+ addrp[3] | addrp[4] | addrp[5]));
+}
+
+static void
+efx_evb_free_vport(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __inout efx_vport_config_t *configp)
+{
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+
+ /* If any callback fails, continue clean-up with others functions */
+ if (EFX_VPORT_PCI_FUNCTION_IS_PF(configp)) {
+ /* free vadaptor */
+ if ((configp->evc_vport_id != EFX_VPORT_ID_INVALID) &&
+ (eeop->eeo_vadaptor_free(enp, vswitch_id,
+ configp->evc_vport_id) != 0)) {
+ EFSYS_PROBE2(eeo_vadaptor_free,
+ uint16_t, configp->evc_function,
+ uint32_t, configp->evc_vport_id);
+ }
+ } else {
+ if (configp->evc_vport_assigned == B_TRUE) {
+ if (eeop->eeo_vport_assign(enp, vswitch_id,
+ EVB_PORT_ID_NULL,
+ configp->evc_function) != 0) {
+ EFSYS_PROBE1(eeo_vport_assign,
+ uint16_t, configp->evc_function);
+ }
+ configp->evc_vport_assigned = B_FALSE;
+ }
+ }
+
+ /*
+ * Call eeo_vport_mac_addr_del after checking that this vport is
+ * actually allocated a MAC address in call to efx_evb_configure_vport
+ */
+ if (!efx_is_zero_eth_addr(configp->evc_mac_addr)) {
+ if (eeop->eeo_vport_mac_addr_del(enp, vswitch_id,
+ configp->evc_vport_id,
+ configp->evc_mac_addr) != 0) {
+ EFSYS_PROBE1(eeo_vport_mac_addr_del,
+ uint16_t, configp->evc_function);
+ }
+ memset(configp->evc_mac_addr, 0x00, EFX_MAC_ADDR_LEN);
+ }
+
+ if (configp->evc_vport_id != EFX_VPORT_ID_INVALID) {
+ if (eeop->eeo_vport_free(enp, vswitch_id,
+ configp->evc_vport_id) != 0) {
+ EFSYS_PROBE1(eeo_vport_free,
+ uint16_t, configp->evc_function);
+ }
+ configp->evc_vport_id = EFX_VPORT_ID_INVALID;
+ }
+}
+
+static void
+efx_evb_free_vports(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in uint32_t num_vports,
+ __inout_ecount(num_vports) efx_vport_config_t *vport_configp)
+{
+ efx_vport_config_t *configp;
+ uint32_t i;
+
+ if (vport_configp == NULL) {
+ EFSYS_PROBE(null_vport_config);
+ return;
+ }
+
+ for (i = 0; i < num_vports; i++) {
+ configp = vport_configp + i;
+ efx_evb_free_vport(enp, vswitch_id, configp);
+ }
+}
+
+static __checkReturn efx_rc_t
+efx_evb_configure_vport(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in const efx_evb_ops_t *eeop,
+ __inout efx_vport_config_t *configp)
+{
+ efx_rc_t rc;
+ efx_vport_id_t vport_id;
+
+ if ((rc = eeop->eeo_vport_alloc(enp, vswitch_id,
+ EFX_VPORT_TYPE_NORMAL, configp->evc_vid,
+ configp->evc_vlan_restrict, &vport_id)) != 0)
+ goto fail1;
+
+ configp->evc_vport_id = vport_id;
+
+ if ((rc = eeop->eeo_vport_mac_addr_add(enp, vswitch_id,
+ configp->evc_vport_id,
+ configp->evc_mac_addr)) != 0)
+ goto fail2;
+
+ if (EFX_VPORT_PCI_FUNCTION_IS_PF(configp)) {
+ if ((rc = eeop->eeo_vadaptor_alloc(enp, vswitch_id,
+ configp->evc_vport_id)) != 0)
+ goto fail3;
+ } else {
+ if ((rc = eeop->eeo_vport_assign(enp, vswitch_id,
+ configp->evc_vport_id,
+ configp->evc_function)) != 0)
+ goto fail4;
+ configp->evc_vport_assigned = B_TRUE;
+ }
+
+ return (0);
+
+fail4:
+ EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_evb_vswitch_create(
+ __in efx_nic_t *enp,
+ __in uint32_t num_vports,
+ __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
+ __deref_out efx_vswitch_t **evpp)
+{
+ efx_vswitch_t *evp;
+ efx_rc_t rc;
+ efx_vswitch_id_t vswitch_id;
+ efx_vport_config_t *configp;
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+ uint32_t i;
+
+ /* vport_configp is a caller allocated array filled in with vports
+ * configuration. Index 0 carries the PF vport configuration and next
+ * num_vports - 1 indices carry VFs configuration.
+ */
+ EFSYS_ASSERT((num_vports != 0) && (vport_configp != NULL) &&
+ (evpp != NULL));
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_EVB);
+ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
+
+ if ((eeop->eeo_vswitch_alloc == NULL) ||
+ (eeop->eeo_vport_alloc == NULL) ||
+ (eeop->eeo_vport_free == NULL) ||
+ (eeop->eeo_vport_mac_addr_add == NULL) ||
+ (eeop->eeo_vport_mac_addr_del == NULL) ||
+ (eeop->eeo_vadaptor_alloc == NULL) ||
+ (eeop->eeo_vadaptor_free == NULL) ||
+ (eeop->eeo_vport_assign == NULL) ||
+ (eeop->eeo_vswitch_free == NULL)) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ /* Allocate a vSwitch object */
+ EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_vswitch_t), evp);
+
+ if (evp == NULL) {
+ rc = ENOMEM;
+ goto fail2;
+ }
+
+ if ((rc = eeop->eeo_vswitch_alloc(enp, &vswitch_id)) != 0)
+ goto fail3;
+
+ evp->ev_enp = enp;
+ evp->ev_num_vports = num_vports;
+ evp->ev_evcp = vport_configp;
+ evp->ev_vswitch_id = vswitch_id;
+
+ for (i = 0; i < num_vports; i++) {
+ configp = vport_configp + i;
+
+ if ((rc = efx_evb_configure_vport(enp, vswitch_id, eeop,
+ configp)) != 0)
+ goto fail4;
+ }
+
+ enp->en_vswitchp = evp;
+ *evpp = evp;
+ return (0);
+
+fail4:
+ EFSYS_PROBE(fail4);
+ efx_evb_free_vports(enp, vswitch_id, i + 1, vport_configp);
+ /* Free the vSwitch */
+ eeop->eeo_vswitch_free(enp, vswitch_id);
+
+fail3:
+ EFSYS_PROBE(fail3);
+ /* Free the vSwitch object */
+ EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_vswitch_t), evp);
+
+fail2:
+ EFSYS_PROBE(fail2);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
+ __checkReturn efx_rc_t
+efx_evb_vswitch_destroy(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp)
+{
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+ efx_vswitch_id_t vswitch_id;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(evp != NULL);
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_EVB);
+
+ if ((eeop->eeo_vport_mac_addr_del == NULL) ||
+ (eeop->eeo_vadaptor_free == NULL) ||
+ (eeop->eeo_vport_assign == NULL) ||
+ (eeop->eeo_vport_free == NULL) ||
+ (eeop->eeo_vswitch_free == NULL)) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ vswitch_id = evp->ev_vswitch_id;
+ efx_evb_free_vports(enp, vswitch_id,
+ evp->ev_num_vports, evp->ev_evcp);
+
+ /* Free the vSwitch object */
+ EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_vswitch_t), evp);
+ enp->en_vswitchp = NULL;
+
+ /* Free the vSwitch */
+ if ((rc = eeop->eeo_vswitch_free(enp, vswitch_id)) != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
#endif
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index ef6a97a..46d5389 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -652,6 +652,17 @@
#if EFSYS_OPT_EVB
+struct efx_vswitch_s {
+ efx_nic_t *ev_enp;
+ efx_vswitch_id_t ev_vswitch_id;
+ uint32_t ev_num_vports;
+ /*
+ * Vport configuration array: index 0 to store PF configuration
+ * and next ev_num_vports-1 entries hold VFs configuration.
+ */
+ efx_vport_config_t *ev_evcp;
+};
+
typedef struct efx_evb_ops_s {
efx_rc_t (*eeo_init)(efx_nic_t *);
void (*eeo_fini)(efx_nic_t *);
@@ -674,6 +685,10 @@
efx_vport_id_t, uint32_t);
} efx_evb_ops_t;
+extern __checkReturn boolean_t
+efx_is_zero_eth_addr(
+ __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp);
+
#endif /* EFSYS_OPT_EVB */
#define EFX_DRV_VER_MAX 20
@@ -776,6 +791,7 @@ struct efx_nic_s {
#endif /* EFX_OPTS_EF10() */
#if EFSYS_OPT_EVB
const efx_evb_ops_t *en_eeop;
+ struct efx_vswitch_s *en_vswitchp;
#endif /* EFSYS_OPT_EVB */
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 22/29] net/sfc/base: factor out upstream port vAdaptor allocation
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (20 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 21/29] net/sfc/base: implement vSwitch create/destroy Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 23/29] net/sfc/base: support data path with EVB module Andrew Rybchenko
` (7 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Separate out vAdaptor allocation from ef10_nic_init() as it is not
required for SR-IOV use case. In case of SR-IOV, vAdaptor is allocated
early along with vSwitch creation and vPort configuration.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 110 ++++++++++++++++++++++++++--------------
1 file changed, 72 insertions(+), 38 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 7eada57..0cf9ddd 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -2220,6 +2220,58 @@
return (rc);
}
+static __checkReturn efx_rc_t
+ef10_upstream_port_vadaptor_alloc(
+ __in efx_nic_t *enp)
+{
+ uint32_t retry;
+ uint32_t delay_us;
+ efx_rc_t rc;
+
+ /*
+ * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
+ * driver has yet to bring up the EVB port. See bug 56147. In this case,
+ * retry the request several times after waiting a while. The wait time
+ * between retries starts small (10ms) and exponentially increases.
+ * Total wait time is a little over two seconds. Retry logic in the
+ * client driver may mean this whole loop is repeated if it continues to
+ * fail.
+ */
+ retry = 0;
+ delay_us = 10000;
+ while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
+ if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
+ (rc != ENOENT)) {
+ /*
+ * Do not retry alloc for PF, or for other errors on
+ * a VF.
+ */
+ goto fail1;
+ }
+
+ /* VF startup before PF is ready. Retry allocation. */
+ if (retry > 5) {
+ /* Too many attempts */
+ rc = EINVAL;
+ goto fail2;
+ }
+ EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
+ EFSYS_SLEEP(delay_us);
+ retry++;
+ if (delay_us < 500000)
+ delay_us <<= 2;
+ }
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
__checkReturn efx_rc_t
ef10_nic_init(
__in efx_nic_t *enp)
@@ -2228,12 +2280,13 @@
uint32_t min_vi_count, max_vi_count;
uint32_t vi_count, vi_base, vi_shift;
uint32_t i;
- uint32_t retry;
- uint32_t delay_us;
uint32_t vi_window_size;
efx_rc_t rc;
+ boolean_t alloc_vadaptor = B_TRUE;
- EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
+ EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
+ enp->en_family == EFX_FAMILY_MEDFORD ||
+ enp->en_family == EFX_FAMILY_MEDFORD2);
/* Enable reporting of some events (e.g. link change) */
if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
@@ -2330,48 +2383,29 @@
}
/*
- * Allocate a vAdaptor attached to our upstream vPort/pPort.
- *
- * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
- * driver has yet to bring up the EVB port. See bug 56147. In this case,
- * retry the request several times after waiting a while. The wait time
- * between retries starts small (10ms) and exponentially increases.
- * Total wait time is a little over two seconds. Retry logic in the
- * client driver may mean this whole loop is repeated if it continues to
- * fail.
+ * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
+ * during NIC initialization when vSwitch is created and vports are
+ * allocated. Hence, skip vAdaptor allocation for EVB and update vport
+ * id in NIC structure with the one allocated for PF.
*/
- retry = 0;
- delay_us = 10000;
- while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
- (rc != ENOENT)) {
- /*
- * Do not retry alloc for PF, or for other errors on
- * a VF.
- */
- goto fail5;
- }
-
- /* VF startup before PF is ready. Retry allocation. */
- if (retry > 5) {
- /* Too many attempts */
- rc = EINVAL;
- goto fail6;
- }
- EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
- EFSYS_SLEEP(delay_us);
- retry++;
- if (delay_us < 500000)
- delay_us <<= 2;
- }
enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
+#if EFSYS_OPT_EVB
+ if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
+ /* For EVB use vport allocated on vswitch */
+ enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
+ alloc_vadaptor = B_FALSE;
+ }
+#endif
+ if (alloc_vadaptor != B_FALSE) {
+ /* Allocate a vAdaptor attached to our upstream vPort/pPort */
+ if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
+ goto fail5;
+ }
enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
return (0);
-fail6:
- EFSYS_PROBE(fail6);
fail5:
EFSYS_PROBE(fail5);
fail4:
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 23/29] net/sfc/base: support data path with EVB module
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (21 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 22/29] net/sfc/base: factor out upstream port vAdaptor allocation Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 24/29] net/sfc/base: support proxy auth operations for SR-IOV Andrew Rybchenko
` (6 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
ef10_nic_init() allocates a vAdaptor for the physical port in current
flow. In case of SR-IOV, this vAdaptor must be created for the PF as the
vSwitch is allocated on the physical port. So, the call to
efx_mcdi_vadaptor_alloc() should be avoided in ef10_nic_init() in SR-IOV
flow. To achieve this, for SR-IOV use case, the vSwitch is created
before NIC initialization and its handle is used to prevent vAdaptor
allocation in ef10_nic_init(). This approach has been taken to minimize
the changes in NIC initilization flow.
This is also the case with Linux driver where vSwitch creation happens
before NIC initialization.
Also, when DMA queues need to be allocated for Tx/Rx functionality
(MC_CMD_INIT_RXQ / MC_CMD_INIT_TXQ), the correct vPort is selected
based on efx_vswitch_t property of efx_nic_t structure - vport
corresponding to PF in case of SR-IOV use case and EVB_PORT_ID_ASSIGNED
for physical port.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_filter.c | 3 +--
drivers/net/sfc/base/ef10_nic.c | 18 ++++++++++++++----
drivers/net/sfc/base/ef10_rx.c | 4 ++--
drivers/net/sfc/base/ef10_tx.c | 2 +-
4 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_filter.c b/drivers/net/sfc/base/ef10_filter.c
index 9c09a0d..e4f8de5 100644
--- a/drivers/net/sfc/base/ef10_filter.c
+++ b/drivers/net/sfc/base/ef10_filter.c
@@ -202,8 +202,7 @@
goto fail1;
}
- MCDI_IN_SET_DWORD(req, FILTER_OP_EXT_IN_PORT_ID,
- EVB_PORT_ID_ASSIGNED);
+ MCDI_IN_SET_DWORD(req, FILTER_OP_EXT_IN_PORT_ID, enp->en_vport_id);
MCDI_IN_SET_DWORD(req, FILTER_OP_EXT_IN_MATCH_FIELDS,
match_flags);
if (spec->efs_dmaq_id == EFX_FILTER_SPEC_RX_DMAQ_ID_DROP) {
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 0cf9ddd..a647daa 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -233,8 +233,6 @@
MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
efx_rc_t rc;
- EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
-
req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
req.emr_in_buf = payload;
req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
@@ -2517,9 +2515,21 @@
{
uint32_t i;
efx_rc_t rc;
+ boolean_t do_vadaptor_free = B_TRUE;
- (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
- enp->en_vport_id = 0;
+#if EFSYS_OPT_EVB
+ if (enp->en_vswitchp != NULL) {
+ /*
+ * For SR-IOV the vAdaptor is freed with the vswitch,
+ * so do not free it here.
+ */
+ do_vadaptor_free = B_FALSE;
+ }
+#endif
+ if (do_vadaptor_free != B_FALSE) {
+ (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
+ enp->en_vport_id = EVB_PORT_ID_NULL;
+ }
/* Unlink piobufs from extra VIs in WC mapping */
if (enp->en_arch.ef10.ena_piobuf_count > 0) {
diff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c
index 27514c1..10eace4 100644
--- a/drivers/net/sfc/base/ef10_rx.c
+++ b/drivers/net/sfc/base/ef10_rx.c
@@ -106,7 +106,7 @@
INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes,
INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev);
MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
- MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
+ MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, enp->en_vport_id);
if (es_bufs_per_desc > 0) {
MCDI_IN_SET_DWORD(req,
@@ -233,7 +233,7 @@
req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
- EVB_PORT_ID_ASSIGNED);
+ enp->en_vport_id);
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
/*
diff --git a/drivers/net/sfc/base/ef10_tx.c b/drivers/net/sfc/base/ef10_tx.c
index 6a90816..90f4803 100644
--- a/drivers/net/sfc/base/ef10_tx.c
+++ b/drivers/net/sfc/base/ef10_tx.c
@@ -82,7 +82,7 @@
INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
- MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
+ MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, enp->en_vport_id);
dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
addr = EFSYS_MEM_ADDR(esmp);
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 24/29] net/sfc/base: support proxy auth operations for SR-IOV
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (22 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 23/29] net/sfc/base: support data path with EVB module Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 25/29] net/sfc/base: implement proxy auth MCDI event handling Andrew Rybchenko
` (5 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
VMware expects that certain kind of configurations made on the VFs are
authorized by the ESXi before these are applied e.g. assigning a MAC
address to the VF, setting MTU etc. Firmware supports a feature called
MCDI proxy which will be used to implement this authorization check.
The proxy auth module is governed by EFSYS_OPT_MCDI_PROXY_AUTH switch.
This patch adds the framework for proxy auth module along with the APIs
required for SR-IOV initialization.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/Makefile | 2 +
drivers/net/sfc/base/ef10_impl.h | 34 +++++
drivers/net/sfc/base/ef10_proxy.c | 255 ++++++++++++++++++++++++++++++++++++++
drivers/net/sfc/base/efx.h | 32 +++++
drivers/net/sfc/base/efx_impl.h | 22 ++++
drivers/net/sfc/base/efx_proxy.c | 200 ++++++++++++++++++++++++++++++
drivers/net/sfc/base/meson.build | 2 +
drivers/net/sfc/efsys.h | 2 +
8 files changed, 549 insertions(+)
create mode 100644 drivers/net/sfc/base/ef10_proxy.c
create mode 100644 drivers/net/sfc/base/efx_proxy.c
diff --git a/drivers/net/sfc/Makefile b/drivers/net/sfc/Makefile
index 7149afd..7dd660d 100644
--- a/drivers/net/sfc/Makefile
+++ b/drivers/net/sfc/Makefile
@@ -101,6 +101,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_nic.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_nvram.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_phy.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_port.c
+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_proxy.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_rx.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_sram.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_tunnel.c
@@ -124,6 +125,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_mcdi.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_nic.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_nvram.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_phy.c
+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_proxy.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_rx.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_tx.c
SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_vpd.c
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index e261487..4b719c9 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1344,6 +1344,40 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
#endif /* EFSYS_OPT_EVB */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+extern __checkReturn efx_rc_t
+ef10_proxy_auth_init(
+ __in efx_nic_t *enp);
+
+extern void
+ef10_proxy_auth_fini(
+ __in efx_nic_t *enp);
+
+extern __checkReturn efx_rc_t
+ef10_proxy_auth_mc_config(
+ __in efx_nic_t *enp,
+ __in efsys_mem_t *request_bufferp,
+ __in efsys_mem_t *response_bufferp,
+ __in efsys_mem_t *status_bufferp,
+ __in uint32_t block_cnt,
+ __in_ecount(op_count) uint32_t *op_listp,
+ __in size_t op_count);
+
+extern __checkReturn efx_rc_t
+ef10_proxy_auth_disable(
+ __in efx_nic_t *enp);
+
+extern __checkReturn efx_rc_t
+ef10_proxy_auth_privilege_modify(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_group,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __in uint32_t add_privileges_mask,
+ __in uint32_t remove_privileges_mask);
+
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+
#if EFSYS_OPT_RX_PACKED_STREAM
/* Data space per credit in packed stream mode */
diff --git a/drivers/net/sfc/base/ef10_proxy.c b/drivers/net/sfc/base/ef10_proxy.c
new file mode 100644
index 0000000..6b1afcc
--- /dev/null
+++ b/drivers/net/sfc/base/ef10_proxy.c
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2018-2019 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+#include "efx.h"
+#include "efx_impl.h"
+
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_init(
+ __in efx_nic_t *enp)
+{
+ EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
+ enp->en_family == EFX_FAMILY_MEDFORD ||
+ enp->en_family == EFX_FAMILY_MEDFORD2);
+
+ return (0);
+}
+
+ void
+ef10_proxy_auth_fini(
+ __in efx_nic_t *enp)
+{
+ EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
+ enp->en_family == EFX_FAMILY_MEDFORD ||
+ enp->en_family == EFX_FAMILY_MEDFORD2);
+}
+
+static __checkReturn efx_rc_t
+efx_mcdi_proxy_configure(
+ __in efx_nic_t *enp,
+ __in boolean_t disable_proxy,
+ __in uint64_t req_buffer_addr,
+ __in uint64_t resp_buffer_addr,
+ __in uint64_t stat_buffer_addr,
+ __in size_t req_size,
+ __in size_t resp_size,
+ __in uint32_t block_cnt,
+ __in uint8_t *op_maskp,
+ __in size_t op_mask_size)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN,
+ MC_CMD_PROXY_CONFIGURE_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_PROXY_CONFIGURE;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_PROXY_CONFIGURE_OUT_LEN;
+
+ if (!disable_proxy) {
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_FLAGS, 1);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO,
+ req_buffer_addr & 0xffffffff);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI,
+ req_buffer_addr >> 32);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO,
+ resp_buffer_addr & 0xffffffff);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI,
+ resp_buffer_addr >> 32);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO,
+ stat_buffer_addr & 0xffffffff);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI,
+ stat_buffer_addr >> 32);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE,
+ req_size);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE,
+ resp_size);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE,
+ MC_PROXY_STATUS_BUFFER_LEN);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_IN_NUM_BLOCKS,
+ block_cnt);
+ memcpy(MCDI_IN2(req, efx_byte_t,
+ PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK),
+ op_maskp, op_mask_size);
+ MCDI_IN_SET_DWORD(req, PROXY_CONFIGURE_EXT_IN_RESERVED,
+ EFX_PROXY_CONFIGURE_MAGIC);
+ }
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+static __checkReturn efx_rc_t
+efx_mcdi_privilege_modify(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_group,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __in uint32_t add_privileges_mask,
+ __in uint32_t remove_privileges_mask)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PRIVILEGE_MODIFY_IN_LEN,
+ MC_CMD_PRIVILEGE_MODIFY_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_PRIVILEGE_MODIFY;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_PRIVILEGE_MODIFY_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_PRIVILEGE_MODIFY_OUT_LEN;
+
+ EFSYS_ASSERT(fn_group <= MC_CMD_PRIVILEGE_MODIFY_IN_ONE);
+
+ MCDI_IN_SET_DWORD(req, PRIVILEGE_MODIFY_IN_FN_GROUP, fn_group);
+
+ if ((fn_group == MC_CMD_PRIVILEGE_MODIFY_IN_ONE) ||
+ (fn_group == MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF)) {
+ MCDI_IN_POPULATE_DWORD_2(req,
+ PRIVILEGE_MODIFY_IN_FUNCTION,
+ PRIVILEGE_MODIFY_IN_FUNCTION_PF, pf_index,
+ PRIVILEGE_MODIFY_IN_FUNCTION_VF, vf_index);
+ }
+
+ MCDI_IN_SET_DWORD(req, PRIVILEGE_MODIFY_IN_ADD_MASK,
+ add_privileges_mask);
+ MCDI_IN_SET_DWORD(req, PRIVILEGE_MODIFY_IN_REMOVE_MASK,
+ remove_privileges_mask);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+static __checkReturn efx_rc_t
+efx_proxy_auth_fill_op_mask(
+ __in_ecount(op_count) uint32_t *op_listp,
+ __in size_t op_count,
+ __out_ecount(op_mask_size) uint32_t *op_maskp,
+ __in size_t op_mask_size)
+{
+ efx_rc_t rc;
+ uint32_t op;
+
+ if ((op_listp == NULL) || (op_maskp == NULL)) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ while (op_count--) {
+ op = *op_listp++;
+ if (op > op_mask_size * 32) {
+ rc = EINVAL;
+ goto fail2;
+ }
+ op_maskp[op / 32] |= 1u << (op & 31);
+ }
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_mc_config(
+ __in efx_nic_t *enp,
+ __in_ecount(block_cnt) efsys_mem_t *request_bufferp,
+ __in_ecount(block_cnt) efsys_mem_t *response_bufferp,
+ __in_ecount(block_cnt) efsys_mem_t *status_bufferp,
+ __in uint32_t block_cnt,
+ __in_ecount(op_count) uint32_t *op_listp,
+ __in size_t op_count)
+{
+#define PROXY_OPS_MASK_SIZE \
+ (EFX_DIV_ROUND_UP( \
+ MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN, \
+ sizeof (uint32_t)))
+
+ efx_rc_t rc;
+ uint32_t op_mask[PROXY_OPS_MASK_SIZE] = {0};
+
+ /* Prepare the operation mask from operation list array */
+ if ((rc = efx_proxy_auth_fill_op_mask(op_listp, op_count,
+ op_mask, PROXY_OPS_MASK_SIZE) != 0))
+ goto fail1;
+
+ if ((rc = efx_mcdi_proxy_configure(enp, B_FALSE,
+ EFSYS_MEM_ADDR(request_bufferp),
+ EFSYS_MEM_ADDR(response_bufferp),
+ EFSYS_MEM_ADDR(status_bufferp),
+ EFSYS_MEM_SIZE(request_bufferp) / block_cnt,
+ EFSYS_MEM_SIZE(response_bufferp) / block_cnt,
+ block_cnt, (uint8_t *)&op_mask,
+ sizeof (op_mask))) != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_disable(
+ __in efx_nic_t *enp)
+{
+ efx_rc_t rc;
+
+ if ((rc = efx_mcdi_proxy_configure(enp, B_TRUE,
+ 0, 0, 0, 0, 0, 0, NULL, 0) != 0))
+ goto fail1;
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_privilege_modify(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_group,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __in uint32_t add_privileges_mask,
+ __in uint32_t remove_privileges_mask)
+{
+ return (efx_mcdi_privilege_modify(enp, fn_group, pf_index, vf_index,
+ add_privileges_mask, remove_privileges_mask));
+}
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 492c8c6..8a3eb17 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3419,6 +3419,38 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
#endif /* EFSYS_OPT_EVB */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+
+typedef struct efx_proxy_auth_config_s {
+ efsys_mem_t *request_bufferp;
+ efsys_mem_t *response_bufferp;
+ efsys_mem_t *status_bufferp;
+ uint32_t block_cnt;
+ uint32_t *op_listp;
+ size_t op_count;
+ uint32_t handled_privileges;
+} efx_proxy_auth_config_t;
+
+extern __checkReturn efx_rc_t
+efx_proxy_auth_init(
+ __in efx_nic_t *enp);
+
+extern void
+efx_proxy_auth_fini(
+ __in efx_nic_t *enp);
+
+extern __checkReturn efx_rc_t
+efx_proxy_auth_configure(
+ __in efx_nic_t *enp,
+ __in efx_proxy_auth_config_t *configp);
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_destroy(
+ __in efx_nic_t *enp,
+ __in uint32_t handled_privileges);
+
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 46d5389..6a8fee8 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -59,6 +59,7 @@
#define EFX_MOD_LIC 0x00002000
#define EFX_MOD_TUNNEL 0x00004000
#define EFX_MOD_EVB 0x00008000
+#define EFX_MOD_PROXY 0x00010000
#define EFX_RESET_PHY 0x00000001
#define EFX_RESET_RXQ_ERR 0x00000002
@@ -691,6 +692,24 @@ struct efx_vswitch_s {
#endif /* EFSYS_OPT_EVB */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+
+#define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF
+
+
+typedef struct efx_proxy_ops_s {
+ efx_rc_t (*epo_init)(efx_nic_t *);
+ void (*epo_fini)(efx_nic_t *);
+ efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
+ efsys_mem_t *, efsys_mem_t *,
+ uint32_t, uint32_t *, size_t);
+ efx_rc_t (*epo_disable)(efx_nic_t *);
+ efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+} efx_proxy_ops_t;
+
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+
#define EFX_DRV_VER_MAX 20
typedef struct efx_drv_cfg_s {
@@ -793,6 +812,9 @@ struct efx_nic_s {
const efx_evb_ops_t *en_eeop;
struct efx_vswitch_s *en_vswitchp;
#endif /* EFSYS_OPT_EVB */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ const efx_proxy_ops_t *en_epop;
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
};
#define EFX_FAMILY_IS_EF10(_enp) \
diff --git a/drivers/net/sfc/base/efx_proxy.c b/drivers/net/sfc/base/efx_proxy.c
new file mode 100644
index 0000000..6aadf07
--- /dev/null
+++ b/drivers/net/sfc/base/efx_proxy.c
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2018-2019 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+#include "efx.h"
+#include "efx_impl.h"
+
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+
+#if EFSYS_OPT_SIENA
+static const efx_proxy_ops_t __efx_proxy_dummy_ops = {
+ NULL, /* epo_init */
+ NULL, /* epo_fini */
+ NULL, /* epo_mc_config */
+ NULL, /* epo_disable */
+ NULL, /* epo_privilege_modify */
+};
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+static const efx_proxy_ops_t __efx_proxy_ef10_ops = {
+ ef10_proxy_auth_init, /* epo_init */
+ ef10_proxy_auth_fini, /* epo_fini */
+ ef10_proxy_auth_mc_config, /* epo_mc_config */
+ ef10_proxy_auth_disable, /* epo_disable */
+ ef10_proxy_auth_privilege_modify, /* epo_privilege_modify */
+};
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_init(
+ __in efx_nic_t *enp)
+{
+ const efx_proxy_ops_t *epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROXY));
+
+ switch (enp->en_family) {
+#if EFSYS_OPT_SIENA
+ case EFX_FAMILY_SIENA:
+ epop = &__efx_proxy_dummy_ops;
+ break;
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+ case EFX_FAMILY_HUNTINGTON:
+ epop = &__efx_proxy_ef10_ops;
+ break;
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+#if EFSYS_OPT_MEDFORD
+ case EFX_FAMILY_MEDFORD:
+ epop = &__efx_proxy_ef10_ops;
+ break;
+#endif /* EFSYS_OPT_MEDFORD */
+
+#if EFSYS_OPT_MEDFORD2
+ case EFX_FAMILY_MEDFORD2:
+ epop = &__efx_proxy_ef10_ops;
+ break;
+#endif /* EFSYS_OPT_MEDFORD2 */
+
+ default:
+ EFSYS_ASSERT(0);
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if (epop->epo_init == NULL) {
+ rc = ENOTSUP;
+ goto fail2;
+ }
+
+ if ((rc = epop->epo_init(enp)) != 0)
+ goto fail3;
+
+ enp->en_epop = epop;
+ enp->en_mod_flags |= EFX_MOD_PROXY;
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+ void
+efx_proxy_auth_fini(
+ __in efx_nic_t *enp)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if ((epop != NULL) && (epop->epo_fini != NULL))
+ epop->epo_fini(enp);
+
+ enp->en_epop = NULL;
+ enp->en_mod_flags &= ~EFX_MOD_PROXY;
+}
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_configure(
+ __in efx_nic_t *enp,
+ __in efx_proxy_auth_config_t *configp)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if ((configp == NULL) ||
+ (configp->request_bufferp == NULL) ||
+ (configp->response_bufferp == NULL) ||
+ (configp->status_bufferp == NULL) ||
+ (configp->op_listp == NULL) ||
+ (configp->block_cnt == 0)) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ if ((epop->epo_mc_config == NULL) ||
+ (epop->epo_privilege_modify == NULL)) {
+ rc = ENOTSUP;
+ goto fail2;
+ }
+
+ rc = epop->epo_mc_config(enp, configp->request_bufferp,
+ configp->response_bufferp, configp->status_bufferp,
+ configp->block_cnt, configp->op_listp,
+ configp->op_count);
+ if (rc != 0)
+ goto fail3;
+
+ rc = epop->epo_privilege_modify(enp, MC_CMD_PRIVILEGE_MODIFY_IN_ALL,
+ 0, 0, 0, configp->handled_privileges);
+ if (rc != 0)
+ goto fail4;
+
+ return (0);
+
+fail4:
+ EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_destroy(
+ __in efx_nic_t *enp,
+ __in uint32_t handled_privileges)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if ((epop->epo_disable == NULL) ||
+ (epop->epo_privilege_modify == NULL)) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ rc = epop->epo_privilege_modify(enp, MC_CMD_PRIVILEGE_MODIFY_IN_ALL,
+ 0, 0, handled_privileges, 0);
+ if (rc != 0)
+ goto fail2;
+
+ rc = epop->epo_disable(enp);
+ if (rc != 0)
+ goto fail3;
+
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
diff --git a/drivers/net/sfc/base/meson.build b/drivers/net/sfc/base/meson.build
index 6fa7948..6c80305 100644
--- a/drivers/net/sfc/base/meson.build
+++ b/drivers/net/sfc/base/meson.build
@@ -20,6 +20,7 @@ sources = [
'efx_nvram.c',
'efx_phy.c',
'efx_port.c',
+ 'efx_proxy.c',
'efx_rx.c',
'efx_sram.c',
'efx_tunnel.c',
@@ -43,6 +44,7 @@ sources = [
'ef10_nic.c',
'ef10_nvram.c',
'ef10_phy.c',
+ 'ef10_proxy.c',
'ef10_rx.c',
'ef10_tx.c',
'ef10_vpd.c',
diff --git a/drivers/net/sfc/efsys.h b/drivers/net/sfc/efsys.h
index 24f3769..762c6ee 100644
--- a/drivers/net/sfc/efsys.h
+++ b/drivers/net/sfc/efsys.h
@@ -168,6 +168,8 @@
#define EFSYS_OPT_EVB 0
+#define EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 0
+
/* ID */
typedef struct __efsys_identifier_s efsys_identifier_t;
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 25/29] net/sfc/base: implement proxy auth MCDI event handling
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (23 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 24/29] net/sfc/base: support proxy auth operations for SR-IOV Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 26/29] net/sfc/base: provide proxy APIs to client drivers Andrew Rybchenko
` (4 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Add the capability to receive MCDI proxy event from firmware and
invoke the client driver registered function to handle it.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_ev.c | 7 +++++++
drivers/net/sfc/base/efx.h | 3 +++
drivers/net/sfc/base/efx_check.h | 9 ++++++++-
drivers/net/sfc/base/efx_mcdi.c | 12 ++++++++++++
drivers/net/sfc/base/efx_mcdi.h | 7 +++++++
5 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/net/sfc/base/ef10_ev.c b/drivers/net/sfc/base/ef10_ev.c
index 99cae3f..8cabb4e 100644
--- a/drivers/net/sfc/base/ef10_ev.c
+++ b/drivers/net/sfc/base/ef10_ev.c
@@ -1227,6 +1227,13 @@
break;
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ case MCDI_EVENT_CODE_PROXY_REQUEST:
+ efx_mcdi_ev_proxy_request(enp,
+ MCDI_EV_FIELD(eqp, PROXY_REQUEST_BUFF_INDEX));
+ break;
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+
case MCDI_EVENT_CODE_LINKCHANGE: {
efx_link_mode_t link_mode;
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 8a3eb17..97c4e62 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -243,6 +243,9 @@ enum {
#if EFSYS_OPT_MCDI_PROXY_AUTH
void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ void (*emt_ev_proxy_request)(void *, uint32_t);
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
} efx_mcdi_transport_t;
extern __checkReturn efx_rc_t
diff --git a/drivers/net/sfc/base/efx_check.h b/drivers/net/sfc/base/efx_check.h
index 85edaef..06983dc 100644
--- a/drivers/net/sfc/base/efx_check.h
+++ b/drivers/net/sfc/base/efx_check.h
@@ -119,8 +119,15 @@
# endif
#endif /* EFSYS_OPT_MCDI_LOGGING */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+/* Support MCDI proxy authorization (server) */
+# if !EFSYS_OPT_MCDI_PROXY_AUTH
+# error "MCDI_PROXY_AUTH_SERVER requires MCDI_PROXY_AUTH"
+# endif
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+
#if EFSYS_OPT_MCDI_PROXY_AUTH
-/* Support MCDI proxy authorization */
+/* Support MCDI proxy authorization (client) */
# if !EFSYS_OPT_MCDI
# error "MCDI_PROXY_AUTH requires MCDI"
# endif
diff --git a/drivers/net/sfc/base/efx_mcdi.c b/drivers/net/sfc/base/efx_mcdi.c
index 584fd4d..325c2e4 100644
--- a/drivers/net/sfc/base/efx_mcdi.c
+++ b/drivers/net/sfc/base/efx_mcdi.c
@@ -845,6 +845,18 @@
}
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ void
+efx_mcdi_ev_proxy_request(
+ __in efx_nic_t *enp,
+ __in unsigned int index)
+{
+ const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
+
+ if (emtp->emt_ev_proxy_request != NULL)
+ emtp->emt_ev_proxy_request(emtp->emt_context, index);
+}
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
void
efx_mcdi_ev_death(
__in efx_nic_t *enp,
diff --git a/drivers/net/sfc/base/efx_mcdi.h b/drivers/net/sfc/base/efx_mcdi.h
index a9e0255..56c0ab1 100644
--- a/drivers/net/sfc/base/efx_mcdi.h
+++ b/drivers/net/sfc/base/efx_mcdi.h
@@ -87,6 +87,13 @@ struct efx_mcdi_req_s {
__in unsigned int status);
#endif
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+extern void
+efx_mcdi_ev_proxy_request(
+ __in efx_nic_t *enp,
+ __in unsigned int index);
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+
extern void
efx_mcdi_ev_death(
__in efx_nic_t *enp,
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 26/29] net/sfc/base: provide proxy APIs to client drivers
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (24 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 25/29] net/sfc/base: implement proxy auth MCDI event handling Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 27/29] net/sfc/base: provide APIs to configure and reset vPort Andrew Rybchenko
` (3 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Implement the APIs for PROXY_CMD, PROXY_COMPLETE and PRIVILEGE_MASK
messages to allow client drivers authorize VF operations like set MAC,
set MTU etc. with firmware.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_impl.h | 19 ++++
drivers/net/sfc/base/ef10_proxy.c | 208 ++++++++++++++++++++++++++++++++++++++
drivers/net/sfc/base/efx.h | 29 ++++++
drivers/net/sfc/base/efx_impl.h | 5 +
drivers/net/sfc/base/efx_mcdi.c | 34 ++++++-
drivers/net/sfc/base/efx_mcdi.h | 2 +-
drivers/net/sfc/base/efx_proxy.c | 100 ++++++++++++++++++
7 files changed, 394 insertions(+), 3 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 4b719c9..e9ce31a 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1376,6 +1376,25 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in uint32_t add_privileges_mask,
__in uint32_t remove_privileges_mask);
+ __checkReturn efx_rc_t
+ef10_proxy_auth_set_privilege_mask(
+ __in efx_nic_t *enp,
+ __in uint32_t vf_index,
+ __in uint32_t mask,
+ __in uint32_t value);
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_complete_request(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_index,
+ __in uint32_t proxy_result,
+ __in uint32_t handle);
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_exec_cmd(
+ __in efx_nic_t *enp,
+ __inout efx_proxy_cmd_params_t *paramsp);
+
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
#if EFSYS_OPT_RX_PACKED_STREAM
diff --git a/drivers/net/sfc/base/ef10_proxy.c b/drivers/net/sfc/base/ef10_proxy.c
index 6b1afcc..a3b73f4 100644
--- a/drivers/net/sfc/base/ef10_proxy.c
+++ b/drivers/net/sfc/base/ef10_proxy.c
@@ -252,4 +252,212 @@
return (efx_mcdi_privilege_modify(enp, fn_group, pf_index, vf_index,
add_privileges_mask, remove_privileges_mask));
}
+
+static __checkReturn efx_rc_t
+efx_mcdi_privilege_mask_set(
+ __in efx_nic_t *enp,
+ __in uint32_t vf_index,
+ __in uint32_t mask,
+ __in uint32_t value)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PRIVILEGE_MASK_IN_LEN,
+ MC_CMD_PRIVILEGE_MASK_OUT_LEN);
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+ uint32_t old_mask = 0;
+ uint32_t new_mask = 0;
+
+ EFSYS_ASSERT((value & ~mask) == 0);
+
+ req.emr_cmd = MC_CMD_PRIVILEGE_MASK;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_PRIVILEGE_MASK_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_PRIVILEGE_MASK_OUT_LEN;
+
+ /* Get privilege mask */
+ MCDI_IN_POPULATE_DWORD_2(req, PRIVILEGE_MASK_IN_FUNCTION,
+ PRIVILEGE_MASK_IN_FUNCTION_PF, encp->enc_pf,
+ PRIVILEGE_MASK_IN_FUNCTION_VF, vf_index);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ if (req.emr_out_length_used != MC_CMD_PRIVILEGE_MASK_OUT_LEN) {
+ rc = EMSGSIZE;
+ goto fail2;
+ }
+
+ old_mask = *MCDI_OUT2(req, uint32_t, PRIVILEGE_MASK_OUT_OLD_MASK);
+ new_mask = old_mask & ~mask;
+ new_mask |= (value & mask);
+
+ if (new_mask == old_mask)
+ return (0);
+
+ new_mask |= MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE;
+ memset(payload, 0, sizeof (payload));
+
+ req.emr_cmd = MC_CMD_PRIVILEGE_MASK;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_PRIVILEGE_MASK_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_PRIVILEGE_MASK_OUT_LEN;
+
+ /* Set privilege mask */
+ MCDI_IN_SET_DWORD(req, PRIVILEGE_MASK_IN_NEW_MASK, new_mask);
+
+ efx_mcdi_execute(enp, &req);
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail3;
+ }
+
+ if (req.emr_out_length_used != MC_CMD_PRIVILEGE_MASK_OUT_LEN) {
+ rc = EMSGSIZE;
+ goto fail4;
+ }
+
+ return (0);
+
+fail4:
+ EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_set_privilege_mask(
+ __in efx_nic_t *enp,
+ __in uint32_t vf_index,
+ __in uint32_t mask,
+ __in uint32_t value)
+{
+ return (efx_mcdi_privilege_mask_set(enp, vf_index,
+ mask, value));
+}
+
+static __checkReturn efx_rc_t
+efx_mcdi_proxy_complete(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_index,
+ __in uint32_t proxy_result,
+ __in uint32_t handle)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PROXY_COMPLETE_IN_LEN,
+ MC_CMD_PROXY_COMPLETE_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ req.emr_cmd = MC_CMD_PROXY_COMPLETE;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_PROXY_COMPLETE_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_PROXY_COMPLETE_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, PROXY_COMPLETE_IN_BLOCK_INDEX, fn_index);
+ MCDI_IN_SET_DWORD(req, PROXY_COMPLETE_IN_STATUS, proxy_result);
+ MCDI_IN_SET_DWORD(req, PROXY_COMPLETE_IN_HANDLE, handle);
+
+ efx_mcdi_execute(enp, &req);
+
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_complete_request(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_index,
+ __in uint32_t proxy_result,
+ __in uint32_t handle)
+{
+ return (efx_mcdi_proxy_complete(enp, fn_index,
+ proxy_result, handle));
+}
+
+static __checkReturn efx_rc_t
+efx_mcdi_proxy_cmd(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __in_bcount(request_size) uint8_t *request_bufferp,
+ __in size_t request_size,
+ __out_bcount(response_size) uint8_t *response_bufferp,
+ __in size_t response_size,
+ __out_opt size_t *response_size_actualp)
+{
+ efx_dword_t *inbufp;
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+
+ if (request_size % sizeof (*inbufp) != 0) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ EFSYS_KMEM_ALLOC(enp, (MC_CMD_PROXY_CMD_IN_LEN + request_size), inbufp);
+
+ req.emr_cmd = MC_CMD_PROXY_CMD;
+ req.emr_in_buf = (uint8_t *) inbufp;
+ req.emr_in_length = MC_CMD_PROXY_CMD_IN_LEN + request_size;
+ req.emr_out_buf = response_bufferp;
+ req.emr_out_length = response_size;
+
+ MCDI_IN_POPULATE_DWORD_2(req, PROXY_CMD_IN_TARGET,
+ PROXY_CMD_IN_TARGET_PF, pf_index,
+ PROXY_CMD_IN_TARGET_VF, vf_index);
+
+ /* Proxied command should be located just after PROXY_CMD */
+ memcpy(&inbufp[MC_CMD_PROXY_CMD_IN_LEN / sizeof (*inbufp)],
+ request_bufferp, request_size);
+
+ efx_mcdi_execute(enp, &req);
+
+ EFSYS_KMEM_FREE(enp, (MC_CMD_PROXY_CMD_IN_LEN + request_size), inbufp);
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail2;
+ }
+
+ if (response_size_actualp != NULL)
+ *response_size_actualp = req.emr_out_length_used;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_proxy_auth_exec_cmd(
+ __in efx_nic_t *enp,
+ __inout efx_proxy_cmd_params_t *paramsp)
+{
+ return (efx_mcdi_proxy_cmd(enp, paramsp->pf_index, paramsp->vf_index,
+ paramsp->request_bufferp, paramsp->request_size,
+ paramsp->response_bufferp, paramsp->response_size,
+ paramsp->response_size_actualp));
+}
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 97c4e62..e43302a 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3434,6 +3434,16 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
uint32_t handled_privileges;
} efx_proxy_auth_config_t;
+typedef struct efx_proxy_cmd_params_s {
+ uint32_t pf_index;
+ uint32_t vf_index;
+ uint8_t *request_bufferp;
+ size_t request_size;
+ uint8_t *response_bufferp;
+ size_t response_size;
+ size_t *response_size_actualp;
+} efx_proxy_cmd_params_t;
+
extern __checkReturn efx_rc_t
efx_proxy_auth_init(
__in efx_nic_t *enp);
@@ -3452,6 +3462,25 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in efx_nic_t *enp,
__in uint32_t handled_privileges);
+ __checkReturn efx_rc_t
+efx_proxy_auth_complete_request(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_index,
+ __in uint32_t proxy_result,
+ __in uint32_t handle);
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_exec_cmd(
+ __in efx_nic_t *enp,
+ __inout efx_proxy_cmd_params_t *paramsp);
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_set_privilege_mask(
+ __in efx_nic_t *enp,
+ __in uint32_t vf_index,
+ __in uint32_t mask,
+ __in uint32_t value);
+
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
#ifdef __cplusplus
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 6a8fee8..6c72166 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -706,6 +706,11 @@ struct efx_vswitch_s {
efx_rc_t (*epo_disable)(efx_nic_t *);
efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
+ efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
+ uint32_t, uint32_t);
+ efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t,
+ uint32_t, uint32_t);
+ efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
} efx_proxy_ops_t;
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
diff --git a/drivers/net/sfc/base/efx_mcdi.c b/drivers/net/sfc/base/efx_mcdi.c
index 325c2e4..e840401 100644
--- a/drivers/net/sfc/base/efx_mcdi.c
+++ b/drivers/net/sfc/base/efx_mcdi.c
@@ -360,7 +360,11 @@
rc = EIO;
goto fail1;
}
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ if (((cmd != emrp->emr_cmd) && (emrp->emr_cmd != MC_CMD_PROXY_CMD)) ||
+#else
if ((cmd != emrp->emr_cmd) ||
+#endif
(seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) {
/* Response is for a different request */
rc = EIO;
@@ -442,6 +446,11 @@
efx_dword_t hdr[2];
unsigned int hdr_len;
size_t bytes;
+ unsigned int resp_off;
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ unsigned int resp_cmd;
+ boolean_t proxied_cmd_resp = B_FALSE;
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
if (emrp->emr_out_buf == NULL)
return;
@@ -456,14 +465,35 @@
*/
efx_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1]));
hdr_len += sizeof (hdr[1]);
+ resp_off = hdr_len;
emrp->emr_out_length_used = EFX_DWORD_FIELD(hdr[1],
- MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
+ MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
+#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
+ /*
+ * A proxy MCDI command is executed by PF on behalf of
+ * one of its VFs. The command to be proxied follows
+ * immediately afterward in the host buffer.
+ * PROXY_CMD inner call complete response should be copied to
+ * output buffer so that it can be returned to the requesting
+ * function in MC_CMD_PROXY_COMPLETE payload.
+ */
+ resp_cmd =
+ EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_EXTENDED_CMD);
+ proxied_cmd_resp = ((emrp->emr_cmd == MC_CMD_PROXY_CMD) &&
+ (resp_cmd != MC_CMD_PROXY_CMD));
+ if (proxied_cmd_resp) {
+ resp_off = 0;
+ emrp->emr_out_length_used += hdr_len;
+ }
+#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
+ } else {
+ resp_off = hdr_len;
}
/* Copy payload out into caller supplied buffer */
bytes = MIN(emrp->emr_out_length_used, emrp->emr_out_length);
- efx_mcdi_read_response(enp, emrp->emr_out_buf, hdr_len, bytes);
+ efx_mcdi_read_response(enp, emrp->emr_out_buf, resp_off, bytes);
#if EFSYS_OPT_MCDI_LOGGING
if (emtp->emt_logger != NULL) {
diff --git a/drivers/net/sfc/base/efx_mcdi.h b/drivers/net/sfc/base/efx_mcdi.h
index 56c0ab1..74cde50 100644
--- a/drivers/net/sfc/base/efx_mcdi.h
+++ b/drivers/net/sfc/base/efx_mcdi.h
@@ -31,7 +31,7 @@ struct efx_mcdi_req_s {
unsigned int emr_cmd;
uint8_t *emr_in_buf;
size_t emr_in_length;
- /* Outputs: retcode, buffer, length, and length used */
+ /* Outputs: retcode, buffer, length and length used */
efx_rc_t emr_rc;
uint8_t *emr_out_buf;
size_t emr_out_length;
diff --git a/drivers/net/sfc/base/efx_proxy.c b/drivers/net/sfc/base/efx_proxy.c
index 6aadf07..b04e7dd 100644
--- a/drivers/net/sfc/base/efx_proxy.c
+++ b/drivers/net/sfc/base/efx_proxy.c
@@ -16,6 +16,9 @@
NULL, /* epo_mc_config */
NULL, /* epo_disable */
NULL, /* epo_privilege_modify */
+ NULL, /* epo_set_privilege_mask */
+ NULL, /* epo_complete_request */
+ NULL, /* epo_exec_cmd */
};
#endif /* EFSYS_OPT_SIENA */
@@ -26,6 +29,9 @@
ef10_proxy_auth_mc_config, /* epo_mc_config */
ef10_proxy_auth_disable, /* epo_disable */
ef10_proxy_auth_privilege_modify, /* epo_privilege_modify */
+ ef10_proxy_auth_set_privilege_mask, /* epo_set_privilege_mask */
+ ef10_proxy_auth_complete_request, /* epo_complete_request */
+ ef10_proxy_auth_exec_cmd, /* epo_exec_cmd */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
@@ -197,4 +203,98 @@
return (rc);
}
+ __checkReturn efx_rc_t
+efx_proxy_auth_complete_request(
+ __in efx_nic_t *enp,
+ __in uint32_t fn_index,
+ __in uint32_t proxy_result,
+ __in uint32_t handle)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if (epop->epo_complete_request == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ rc = epop->epo_complete_request(enp, fn_index, proxy_result, handle);
+ if (rc != 0)
+ goto fail2;
+
+ return (0);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_exec_cmd(
+ __in efx_nic_t *enp,
+ __inout efx_proxy_cmd_params_t *paramsp)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if (paramsp == NULL) {
+ rc = EINVAL;
+ goto fail1;
+ }
+
+ if (epop->epo_exec_cmd == NULL) {
+ rc = ENOTSUP;
+ goto fail2;
+ }
+
+ rc = epop->epo_exec_cmd(enp, paramsp);
+ if (rc != 0)
+ goto fail3;
+
+ return (0);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_set_privilege_mask(
+ __in efx_nic_t *enp,
+ __in uint32_t vf_index,
+ __in uint32_t mask,
+ __in uint32_t value)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if (epop->epo_set_privilege_mask == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ rc = epop->epo_set_privilege_mask(enp, vf_index, mask, value);
+ if (rc != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 27/29] net/sfc/base: provide APIs to configure and reset vPort
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (25 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 26/29] net/sfc/base: provide proxy APIs to client drivers Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 28/29] net/sfc/base: provide API to fetch vPort statistics Andrew Rybchenko
` (2 subsequent siblings)
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Implement functions to set vPort VLAN and MAC address and reset the vPort.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_evb.c | 83 +++++++++++++++++++++++++++++
drivers/net/sfc/base/ef10_impl.h | 9 ++++
drivers/net/sfc/base/ef10_nic.c | 6 +++
drivers/net/sfc/base/efx.h | 24 +++++++++
drivers/net/sfc/base/efx_evb.c | 109 +++++++++++++++++++++++++++++++++++++++
drivers/net/sfc/base/efx_impl.h | 4 ++
6 files changed, 235 insertions(+)
diff --git a/drivers/net/sfc/base/ef10_evb.c b/drivers/net/sfc/base/ef10_evb.c
index aaa97f6..6b6d7cc 100644
--- a/drivers/net/sfc/base/ef10_evb.c
+++ b/drivers/net/sfc/base/ef10_evb.c
@@ -330,6 +330,74 @@
return (rc);
}
+ __checkReturn efx_rc_t
+efx_mcdi_vport_reconfigure(
+ __in efx_nic_t *enp,
+ __in efx_vport_id_t vport_id,
+ __in_opt uint16_t *vidp,
+ __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
+ __out_opt boolean_t *fn_resetp)
+{
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_RECONFIGURE_IN_LEN,
+ MC_CMD_VPORT_RECONFIGURE_OUT_LEN);
+ efx_mcdi_req_t req;
+ efx_rc_t rc;
+ uint32_t reset_flag = 0;
+
+ req.emr_cmd = MC_CMD_VPORT_RECONFIGURE;
+ req.emr_in_buf = payload;
+ req.emr_in_length = MC_CMD_VPORT_RECONFIGURE_IN_LEN;
+ req.emr_out_buf = payload;
+ req.emr_out_length = MC_CMD_VPORT_RECONFIGURE_OUT_LEN;
+
+ MCDI_IN_SET_DWORD(req, VPORT_RECONFIGURE_IN_VPORT_ID, vport_id);
+
+ if (vidp != NULL) {
+ MCDI_IN_POPULATE_DWORD_1(req, VPORT_RECONFIGURE_IN_FLAGS,
+ VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS, 1);
+ if (*vidp != EFX_FILTER_VID_UNSPEC) {
+ MCDI_IN_SET_DWORD(req,
+ VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS, 1);
+ MCDI_IN_POPULATE_DWORD_1(req,
+ VPORT_RECONFIGURE_IN_VLAN_TAGS,
+ VPORT_RECONFIGURE_IN_VLAN_TAG_0, *vidp);
+ }
+ }
+
+ if ((addrp != NULL) && (efx_is_zero_eth_addr(addrp) == B_FALSE)) {
+ MCDI_IN_POPULATE_DWORD_1(req, VPORT_RECONFIGURE_IN_FLAGS,
+ VPORT_RECONFIGURE_IN_REPLACE_MACADDRS, 1);
+ MCDI_IN_SET_DWORD(req, VPORT_RECONFIGURE_IN_NUM_MACADDRS, 1);
+ EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t,
+ VPORT_RECONFIGURE_IN_MACADDRS), addrp);
+ }
+
+ efx_mcdi_execute(enp, &req);
+ if (req.emr_rc != 0) {
+ rc = req.emr_rc;
+ goto fail1;
+ }
+
+ if (req.emr_out_length_used < MC_CMD_VPORT_RECONFIGURE_OUT_LEN) {
+ rc = EMSGSIZE;
+ goto fail2;
+ }
+
+ reset_flag = MCDI_OUT_DWORD_FIELD(req, VPORT_RECONFIGURE_OUT_FLAGS,
+ VPORT_RECONFIGURE_OUT_RESET_DONE);
+
+ if (fn_resetp != NULL)
+ *fn_resetp = (reset_flag != 0);
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
__checkReturn efx_rc_t
ef10_evb_vswitch_alloc(
__in efx_nic_t *enp,
@@ -453,5 +521,20 @@
return (efx_mcdi_port_assign(enp, vport_id, vf_index));
}
+ __checkReturn efx_rc_t
+ef10_evb_vport_reconfigure(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in_opt uint16_t *vidp,
+ __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
+ __out_opt boolean_t *fn_resetp)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_vport_reconfigure(enp, vport_id, vidp,
+ addrp, fn_resetp));
+}
+
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
#endif /* EFSYS_OPT_EVB */
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index e9ce31a..20f2a5c 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1342,6 +1342,15 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in efx_vport_id_t vport_id,
__in uint32_t vf_index);
+extern __checkReturn efx_rc_t
+ef10_evb_vport_reconfigure(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in_opt uint16_t *vidp,
+ __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
+ __out_opt boolean_t *fn_resetp);
+
#endif /* EFSYS_OPT_EVB */
#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index a647daa..b25ce19 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1108,6 +1108,12 @@
else
encp->enc_datapath_cap_evb = B_FALSE;
+ /* Check if the firmware supports vport reconfiguration */
+ if (CAP_FLAGS1(req, VPORT_RECONFIGURE))
+ encp->enc_vport_reconfigure_supported = B_TRUE;
+ else
+ encp->enc_vport_reconfigure_supported = B_FALSE;
+
/* Check if the firmware supports VLAN insertion */
if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index e43302a..0e6e842 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1370,6 +1370,8 @@ enum {
uint32_t enc_hw_pf_count;
/* Datapath firmware vadapter/vport/vswitch support */
boolean_t enc_datapath_cap_evb;
+ /* Datapath firmware vport reconfigure support */
+ boolean_t enc_vport_reconfigure_supported;
boolean_t enc_rx_disable_scatter_supported;
boolean_t enc_allow_set_mac_with_installed_filters;
boolean_t enc_enhanced_set_mac_supported;
@@ -3420,6 +3422,28 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in efx_nic_t *enp,
__in efx_vswitch_t *evp);
+extern __checkReturn efx_rc_t
+efx_evb_vport_mac_set(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
+
+extern __checkReturn efx_rc_t
+efx_evb_vport_vlan_set(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __in uint16_t vid);
+
+extern __checkReturn efx_rc_t
+efx_evb_vport_reset(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
+ __in uint16_t vid,
+ __out boolean_t *is_fn_resetp);
#endif /* EFSYS_OPT_EVB */
#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
diff --git a/drivers/net/sfc/base/efx_evb.c b/drivers/net/sfc/base/efx_evb.c
index 27b466f..d48e1d7 100644
--- a/drivers/net/sfc/base/efx_evb.c
+++ b/drivers/net/sfc/base/efx_evb.c
@@ -23,6 +23,7 @@
NULL, /* eeo_vadaptor_alloc */
NULL, /* eeo_vadaptor_free */
NULL, /* eeo_vport_assign */
+ NULL, /* eeo_vport_reconfigure */
};
#endif /* EFSYS_OPT_SIENA */
@@ -39,6 +40,7 @@
ef10_evb_vadaptor_alloc, /* eeo_vadaptor_alloc */
ef10_evb_vadaptor_free, /* eeo_vadaptor_free */
ef10_evb_vport_assign, /* eeo_vport_assign */
+ ef10_evb_vport_reconfigure, /* eeo_vport_reconfigure */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
@@ -348,7 +350,114 @@
return (rc);
}
+ __checkReturn efx_rc_t
+efx_evb_vport_mac_set(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp)
+{
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_EVB);
+
+ if (eeop->eeo_vport_reconfigure == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if (addrp == NULL) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ rc = eeop->eeo_vport_reconfigure(enp, evp->ev_vswitch_id, vport_id,
+ NULL, addrp, NULL);
+ if (rc != 0)
+ goto fail3;
+
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_evb_vport_vlan_set(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __in uint16_t vid)
+{
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_EVB);
+
+ if (eeop->eeo_vport_reconfigure == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+ rc = eeop->eeo_vport_reconfigure(enp, evp->ev_vswitch_id, vport_id,
+ &vid, NULL, NULL);
+ if (rc != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_evb_vport_reset(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
+ __in uint16_t vid,
+ __out boolean_t *is_fn_resetp)
+{
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_EVB);
+
+ if (eeop->eeo_vport_reconfigure == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if (is_fn_resetp == NULL) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ rc = eeop->eeo_vport_reconfigure(enp, evp->ev_vswitch_id, vport_id,
+ &vid, addrp, is_fn_resetp);
+ if (rc != 0)
+ goto fail3;
+
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
__checkReturn efx_rc_t
efx_evb_vswitch_destroy(
__in efx_nic_t *enp,
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 6c72166..fd31a6d 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -684,6 +684,10 @@ struct efx_vswitch_s {
efx_vport_id_t);
efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
efx_vport_id_t, uint32_t);
+ efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t,
+ uint16_t *, uint8_t *,
+ boolean_t *);
} efx_evb_ops_t;
extern __checkReturn boolean_t
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 28/29] net/sfc/base: provide API to fetch vPort statistics
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (26 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 27/29] net/sfc/base: provide APIs to configure and reset vPort Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-10 7:38 ` [dpdk-dev] [PATCH 29/29] net/sfc/base: add APIs for PTP privilege configuration Andrew Rybchenko
2019-06-18 7:52 ` [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Ferruh Yigit
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Hypervisor should be able to track VF statistics.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_evb.c | 13 +++++++++++++
drivers/net/sfc/base/ef10_impl.h | 7 +++++++
drivers/net/sfc/base/efx.h | 8 ++++++++
drivers/net/sfc/base/efx_evb.c | 40 ++++++++++++++++++++++++++++++++++++++++
drivers/net/sfc/base/efx_impl.h | 18 ++++++++++++++++++
drivers/net/sfc/base/efx_mcdi.c | 30 +++++++++++++-----------------
6 files changed, 99 insertions(+), 17 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_evb.c b/drivers/net/sfc/base/ef10_evb.c
index 6b6d7cc..1788a2c 100644
--- a/drivers/net/sfc/base/ef10_evb.c
+++ b/drivers/net/sfc/base/ef10_evb.c
@@ -536,5 +536,18 @@
addrp, fn_resetp));
}
+ __checkReturn efx_rc_t
+ef10_evb_vport_stats(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __in efsys_mem_t *esmp)
+{
+ _NOTE(ARGUNUSED(vswitch_id))
+
+ return (efx_mcdi_mac_stats(enp, vport_id, esmp,
+ EFX_STATS_UPLOAD, 0));
+}
+
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
#endif /* EFSYS_OPT_EVB */
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 20f2a5c..09f97f8 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1351,6 +1351,13 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
__out_opt boolean_t *fn_resetp);
+extern __checkReturn efx_rc_t
+ef10_evb_vport_stats(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_id_t vswitch_id,
+ __in efx_vport_id_t vport_id,
+ __out efsys_mem_t *esmp);
+
#endif /* EFSYS_OPT_EVB */
#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 0e6e842..a43ddd9 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3444,6 +3444,14 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
__in uint16_t vid,
__out boolean_t *is_fn_resetp);
+
+extern __checkReturn efx_rc_t
+efx_evb_vport_stats(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __out efsys_mem_t *stats_bufferp);
+
#endif /* EFSYS_OPT_EVB */
#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
diff --git a/drivers/net/sfc/base/efx_evb.c b/drivers/net/sfc/base/efx_evb.c
index d48e1d7..dd64bc7 100644
--- a/drivers/net/sfc/base/efx_evb.c
+++ b/drivers/net/sfc/base/efx_evb.c
@@ -24,6 +24,7 @@
NULL, /* eeo_vadaptor_free */
NULL, /* eeo_vport_assign */
NULL, /* eeo_vport_reconfigure */
+ NULL, /* eeo_vport_stats */
};
#endif /* EFSYS_OPT_SIENA */
@@ -41,6 +42,7 @@
ef10_evb_vadaptor_free, /* eeo_vadaptor_free */
ef10_evb_vport_assign, /* eeo_vport_assign */
ef10_evb_vport_reconfigure, /* eeo_vport_reconfigure */
+ ef10_evb_vport_stats, /* eeo_vport_stats */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
@@ -501,4 +503,42 @@
return (rc);
}
+ __checkReturn efx_rc_t
+efx_evb_vport_stats(
+ __in efx_nic_t *enp,
+ __in efx_vswitch_t *evp,
+ __in efx_vport_id_t vport_id,
+ __out efsys_mem_t *stats_bufferp)
+{
+ efx_rc_t rc;
+ const efx_evb_ops_t *eeop = enp->en_eeop;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_EVB);
+
+ if (eeop->eeo_vport_stats == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if (stats_bufferp == NULL) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ rc = eeop->eeo_vport_stats(enp, evp->ev_vswitch_id,
+ vport_id, stats_bufferp);
+ if (rc != 0)
+ goto fail3;
+
+ return (0);
+
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
#endif
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index fd31a6d..3e8b26a 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -688,6 +688,8 @@ struct efx_vswitch_s {
efx_vport_id_t,
uint16_t *, uint8_t *,
boolean_t *);
+ efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
+ efx_vport_id_t, efsys_mem_t *);
} efx_evb_ops_t;
extern __checkReturn boolean_t
@@ -1358,6 +1360,14 @@ struct efx_mac_stats_range {
efx_mac_stat_t last;
};
+typedef enum efx_stats_action_e {
+ EFX_STATS_CLEAR,
+ EFX_STATS_UPLOAD,
+ EFX_STATS_ENABLE_NOEVENTS,
+ EFX_STATS_ENABLE_EVENTS,
+ EFX_STATS_DISABLE,
+} efx_stats_action_t;
+
extern efx_rc_t
efx_mac_stats_mask_add_ranges(
__inout_bcount(mask_size) uint32_t *maskp,
@@ -1365,6 +1375,14 @@ struct efx_mac_stats_range {
__in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
__in unsigned int rng_count);
+extern __checkReturn efx_rc_t
+efx_mcdi_mac_stats(
+ __in efx_nic_t *enp,
+ __in uint32_t vport_id,
+ __in_opt efsys_mem_t *esmp,
+ __in efx_stats_action_t action,
+ __in uint16_t period_ms);
+
#endif /* EFSYS_OPT_MAC_STATS */
#ifdef __cplusplus
diff --git a/drivers/net/sfc/base/efx_mcdi.c b/drivers/net/sfc/base/efx_mcdi.c
index e840401..477b128 100644
--- a/drivers/net/sfc/base/efx_mcdi.c
+++ b/drivers/net/sfc/base/efx_mcdi.c
@@ -1834,17 +1834,10 @@
#if EFSYS_OPT_MAC_STATS
-typedef enum efx_stats_action_e {
- EFX_STATS_CLEAR,
- EFX_STATS_UPLOAD,
- EFX_STATS_ENABLE_NOEVENTS,
- EFX_STATS_ENABLE_EVENTS,
- EFX_STATS_DISABLE,
-} efx_stats_action_t;
-
-static __checkReturn efx_rc_t
+ __checkReturn efx_rc_t
efx_mcdi_mac_stats(
__in efx_nic_t *enp,
+ __in uint32_t vport_id,
__in_opt efsys_mem_t *esmp,
__in efx_stats_action_t action,
__in uint16_t period_ms)
@@ -1910,7 +1903,7 @@
* vadapter has already been deleted.
*/
MCDI_IN_SET_DWORD(req, MAC_STATS_IN_PORT_ID,
- (disable ? EVB_PORT_ID_NULL : enp->en_vport_id));
+ (disable ? EVB_PORT_ID_NULL : vport_id));
efx_mcdi_execute(enp, &req);
@@ -1943,7 +1936,8 @@
{
efx_rc_t rc;
- if ((rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_CLEAR, 0)) != 0)
+ if ((rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL,
+ EFX_STATS_CLEAR, 0)) != 0)
goto fail1;
return (0);
@@ -1966,7 +1960,8 @@
* avoid having to pull the statistics buffer into the cache to
* maintain cumulative statistics.
*/
- if ((rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_UPLOAD, 0)) != 0)
+ if ((rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, esmp,
+ EFX_STATS_UPLOAD, 0)) != 0)
goto fail1;
return (0);
@@ -1994,13 +1989,14 @@
* Medford uses a fixed 1sec period before v6.2.1.1033 firmware.
*/
if (period_ms == 0)
- rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_DISABLE, 0);
+ rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, NULL,
+ EFX_STATS_DISABLE, 0);
else if (events)
- rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_EVENTS,
- period_ms);
+ rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, esmp,
+ EFX_STATS_ENABLE_EVENTS, period_ms);
else
- rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_NOEVENTS,
- period_ms);
+ rc = efx_mcdi_mac_stats(enp, enp->en_vport_id, esmp,
+ EFX_STATS_ENABLE_NOEVENTS, period_ms);
if (rc != 0)
goto fail1;
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* [dpdk-dev] [PATCH 29/29] net/sfc/base: add APIs for PTP privilege configuration
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (27 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 28/29] net/sfc/base: provide API to fetch vPort statistics Andrew Rybchenko
@ 2019-06-10 7:38 ` Andrew Rybchenko
2019-06-18 7:52 ` [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Ferruh Yigit
29 siblings, 0 replies; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-10 7:38 UTC (permalink / raw)
To: dev; +Cc: Gautam Dawar
From: Gautam Dawar <gdawar@solarflare.com>
Implement the efx_proxy_auth_privilege_mask_get() to get a function's
privilege mask and efx_proxy_auth_privilege_modify() to add/remove
privileges for a function specified by PF and VF index.
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_impl.h | 7 +++++
drivers/net/sfc/base/ef10_proxy.c | 11 +++++++
drivers/net/sfc/base/efx.h | 15 +++++++++
drivers/net/sfc/base/efx_impl.h | 2 ++
drivers/net/sfc/base/efx_proxy.c | 64 +++++++++++++++++++++++++++++++++++++++
5 files changed, 99 insertions(+)
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 09f97f8..3961801 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1411,6 +1411,13 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in efx_nic_t *enp,
__inout efx_proxy_cmd_params_t *paramsp);
+ __checkReturn efx_rc_t
+ef10_proxy_auth_get_privilege_mask(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __out uint32_t *maskp);
+
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
#if EFSYS_OPT_RX_PACKED_STREAM
diff --git a/drivers/net/sfc/base/ef10_proxy.c b/drivers/net/sfc/base/ef10_proxy.c
index a3b73f4..059b2f5 100644
--- a/drivers/net/sfc/base/ef10_proxy.c
+++ b/drivers/net/sfc/base/ef10_proxy.c
@@ -451,6 +451,17 @@
}
__checkReturn efx_rc_t
+ef10_proxy_auth_get_privilege_mask(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __out uint32_t *maskp)
+{
+ return (efx_mcdi_privilege_mask(enp, pf_index, vf_index, maskp));
+}
+
+
+ __checkReturn efx_rc_t
ef10_proxy_auth_exec_cmd(
__in efx_nic_t *enp,
__inout efx_proxy_cmd_params_t *paramsp)
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index a43ddd9..53c7b42 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -3513,6 +3513,21 @@ extern __checkReturn __success(return != B_FALSE) boolean_t
__in uint32_t mask,
__in uint32_t value);
+ __checkReturn efx_rc_t
+efx_proxy_auth_privilege_mask_get(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __out uint32_t *maskp);
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_privilege_modify(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __in uint32_t add_privileges_mask,
+ __in uint32_t remove_privileges_mask);
+
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
#ifdef __cplusplus
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 3e8b26a..85d984f 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -717,6 +717,8 @@ struct efx_vswitch_s {
efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t,
uint32_t, uint32_t);
efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
+ efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
+ uint32_t, uint32_t *);
} efx_proxy_ops_t;
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
diff --git a/drivers/net/sfc/base/efx_proxy.c b/drivers/net/sfc/base/efx_proxy.c
index b04e7dd..791105a 100644
--- a/drivers/net/sfc/base/efx_proxy.c
+++ b/drivers/net/sfc/base/efx_proxy.c
@@ -19,6 +19,7 @@
NULL, /* epo_set_privilege_mask */
NULL, /* epo_complete_request */
NULL, /* epo_exec_cmd */
+ NULL, /* epo_get_privilege_mask */
};
#endif /* EFSYS_OPT_SIENA */
@@ -32,6 +33,7 @@
ef10_proxy_auth_set_privilege_mask, /* epo_set_privilege_mask */
ef10_proxy_auth_complete_request, /* epo_complete_request */
ef10_proxy_auth_exec_cmd, /* epo_exec_cmd */
+ ef10_proxy_auth_get_privilege_mask, /* epo_get_privilege_mask */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
@@ -296,5 +298,67 @@
return (rc);
}
+ __checkReturn efx_rc_t
+efx_proxy_auth_privilege_mask_get(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __out uint32_t *maskp)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if (epop->epo_get_privilege_mask == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ rc = epop->epo_get_privilege_mask(enp, pf_index, vf_index, maskp);
+ if (rc != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_proxy_auth_privilege_modify(
+ __in efx_nic_t *enp,
+ __in uint32_t pf_index,
+ __in uint32_t vf_index,
+ __in uint32_t add_privileges_mask,
+ __in uint32_t remove_privileges_mask)
+{
+ const efx_proxy_ops_t *epop = enp->en_epop;
+ efx_rc_t rc;
+
+ EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROXY);
+
+ if (epop->epo_privilege_modify == NULL) {
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ rc = epop->epo_privilege_modify(enp, MC_CMD_PRIVILEGE_MODIFY_IN_ONE,
+ pf_index, vf_index, add_privileges_mask,
+ remove_privileges_mask);
+ if (rc != 0)
+ goto fail2;
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
--
1.8.3.1
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver
2019-06-10 7:38 [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Andrew Rybchenko
` (28 preceding siblings ...)
2019-06-10 7:38 ` [dpdk-dev] [PATCH 29/29] net/sfc/base: add APIs for PTP privilege configuration Andrew Rybchenko
@ 2019-06-18 7:52 ` Ferruh Yigit
2019-06-23 22:37 ` Thomas Monjalon
29 siblings, 1 reply; 35+ messages in thread
From: Ferruh Yigit @ 2019-06-18 7:52 UTC (permalink / raw)
To: Andrew Rybchenko, dev
On 6/10/2019 8:38 AM, Andrew Rybchenko wrote:
> checkpatches.sh generates warnings/errors because of a bit different
> coding style in base driver.
>
> Andrew Lee (1):
> net/sfc/base: fix signed/unsigned mismatch errors
>
> Andrew Rybchenko (2):
> net/sfc/base: do not rely on indirect header inclusion
> net/sfc/base: update MCDI headers
>
> Gautam Dawar (14):
> net/sfc/base: enable chained multicast on all EF10 cards
> net/sfc/base: export the zero-based MCDI port number
> net/sfc/base: introduce of EVB module for SR-IOV support
> net/sfc/base: add MCDI wrappers for vPort and vSwitch in EVB
> net/sfc/base: add EVB module vSwitch/vPort/vAdaptor ops
> net/sfc/base: implement vSwitch create/destroy
> net/sfc/base: factor out upstream port vAdaptor allocation
> net/sfc/base: support data path with EVB module
> net/sfc/base: support proxy auth operations for SR-IOV
> net/sfc/base: implement proxy auth MCDI event handling
> net/sfc/base: provide proxy APIs to client drivers
> net/sfc/base: provide APIs to configure and reset vPort
> net/sfc/base: provide API to fetch vPort statistics
> net/sfc/base: add APIs for PTP privilege configuration
>
> Kevin Lampis (1):
> net/sfc/base: add definition of OEM TLV
>
> Mark Spender (2):
> net/sfc/base: fix shift by more bits than field width
> net/sfc/base: improve code style in sensors decoding
>
> Paul Fox (1):
> net/sfc/base: add definition of bundle metadata partition
>
> Richard Houldsworth (8):
> net/sfc/base: add driver version string registration
> net/sfc/base: add capabilities for bundle partition support
> net/sfc/base: add extensible NVRAM info function
> net/sfc/base: add NVRAM info to API
> net/sfc/base: add firmware ID header
> net/sfc/base: support direct FW update for bundle partitions
> net/sfc/base: transition to the extensible NVRAM info API
> net/sfc/base: add background mode firmware updating
Series applied to dpdk-next-net/master, thanks.
Fixed following checkpatch warnings while merging:
ERROR:SPACING: space required before the open brace '{'
#49: FILE: drivers/net/sfc/base/mcdi_mon.c:85:
+ (efx_mon_get_stat_portmap(id, &stat_portmask) != B_TRUE)){
WARNING:TYPO_SPELLING: 'paramter' may be misspelled - perhaps 'parameter'?
#1:
identifier and hence this paramter is unused for EF10 architecture
WARNING:TYPO_SPELLING: 'initilization' may be misspelled - perhaps 'initialization'?
#13:
the changes in NIC initilization flow.
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver
2019-06-18 7:52 ` [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver Ferruh Yigit
@ 2019-06-23 22:37 ` Thomas Monjalon
2019-06-24 7:53 ` Andrew Rybchenko
0 siblings, 1 reply; 35+ messages in thread
From: Thomas Monjalon @ 2019-06-23 22:37 UTC (permalink / raw)
To: Andrew Rybchenko; +Cc: dev, Ferruh Yigit
18/06/2019 09:52, Ferruh Yigit:
> On 6/10/2019 8:38 AM, Andrew Rybchenko wrote:
> > checkpatches.sh generates warnings/errors because of a bit different
> > coding style in base driver.
[...]
> Series applied to dpdk-next-net/master, thanks.
>
> Fixed following checkpatch warnings while merging:
There are a lot more checkpatch warnings in this code.
Is it possible to fix the style of the code in the sfc/base directory?
Or we prefer to continue with so many checkpatch warnings?
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver
2019-06-23 22:37 ` Thomas Monjalon
@ 2019-06-24 7:53 ` Andrew Rybchenko
2019-06-24 11:17 ` Ferruh Yigit
0 siblings, 1 reply; 35+ messages in thread
From: Andrew Rybchenko @ 2019-06-24 7:53 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev, Ferruh Yigit
Hi Thomas,
On 6/24/19 1:37 AM, Thomas Monjalon wrote:
> 18/06/2019 09:52, Ferruh Yigit:
>> On 6/10/2019 8:38 AM, Andrew Rybchenko wrote:
>>> checkpatches.sh generates warnings/errors because of a bit different
>>> coding style in base driver.
> [...]
>> Series applied to dpdk-next-net/master, thanks.
>>
>> Fixed following checkpatch warnings while merging:
> There are a lot more checkpatch warnings in this code.
> Is it possible to fix the style of the code in the sfc/base directory?
> Or we prefer to continue with so many checkpatch warnings?
In short: I'm trying to minimize a number of warnings, but it is not always
possible. I'll pay even more attention to it in the future.
The base driver is used for other OS drivers and coding style in the base
driver is a common denominator of their coding styles plus some kind
of established practices. Unfortunately some points in coding style in
FreeBSD and GLD (Solaris) contradict to DPDK coding style.
Of course, there is a grey area and we're trying to avoid checkpatches.sh
warning there. Sometimes even changing existing practices, but anyway
major changes of coding style in existing sources is not a good idea.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver
2019-06-24 7:53 ` Andrew Rybchenko
@ 2019-06-24 11:17 ` Ferruh Yigit
2019-06-24 13:07 ` Thomas Monjalon
0 siblings, 1 reply; 35+ messages in thread
From: Ferruh Yigit @ 2019-06-24 11:17 UTC (permalink / raw)
To: Andrew Rybchenko, Thomas Monjalon; +Cc: dev
On 6/24/2019 8:53 AM, Andrew Rybchenko wrote:
> Hi Thomas,
>
> On 6/24/19 1:37 AM, Thomas Monjalon wrote:
>> 18/06/2019 09:52, Ferruh Yigit:
>>> On 6/10/2019 8:38 AM, Andrew Rybchenko wrote:
>>>> checkpatches.sh generates warnings/errors because of a bit different
>>>> coding style in base driver.
>> [...]
>>> Series applied to dpdk-next-net/master, thanks.
>>>
>>> Fixed following checkpatch warnings while merging:
>> There are a lot more checkpatch warnings in this code.
>> Is it possible to fix the style of the code in the sfc/base directory?
>> Or we prefer to continue with so many checkpatch warnings?
>
> In short: I'm trying to minimize a number of warnings, but it is not always
> possible. I'll pay even more attention to it in the future.
There are a few known syntax differences between DPDK and sfc/base/*, most of
the warnings are from those,
at least I am OK with them as long as the syntax is consistent in sfc/base/*
which seems the case, I believe this is better than having a mixture of two
different syntax in the code.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [dpdk-dev] [PATCH 00/29] net/sfc/base: update base driver
2019-06-24 11:17 ` Ferruh Yigit
@ 2019-06-24 13:07 ` Thomas Monjalon
0 siblings, 0 replies; 35+ messages in thread
From: Thomas Monjalon @ 2019-06-24 13:07 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: Andrew Rybchenko, dev
24/06/2019 13:17, Ferruh Yigit:
> On 6/24/2019 8:53 AM, Andrew Rybchenko wrote:
> > Hi Thomas,
> >
> > On 6/24/19 1:37 AM, Thomas Monjalon wrote:
> >> 18/06/2019 09:52, Ferruh Yigit:
> >>> On 6/10/2019 8:38 AM, Andrew Rybchenko wrote:
> >>>> checkpatches.sh generates warnings/errors because of a bit different
> >>>> coding style in base driver.
> >> [...]
> >>> Series applied to dpdk-next-net/master, thanks.
> >>>
> >>> Fixed following checkpatch warnings while merging:
> >> There are a lot more checkpatch warnings in this code.
> >> Is it possible to fix the style of the code in the sfc/base directory?
> >> Or we prefer to continue with so many checkpatch warnings?
> >
> > In short: I'm trying to minimize a number of warnings, but it is not always
> > possible. I'll pay even more attention to it in the future.
>
> There are a few known syntax differences between DPDK and sfc/base/*, most of
> the warnings are from those,
>
> at least I am OK with them as long as the syntax is consistent in sfc/base/*
> which seems the case, I believe this is better than having a mixture of two
> different syntax in the code.
OK thanks for the answers
^ permalink raw reply [flat|nested] 35+ messages in thread