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* [dpdk-dev] [PATCH] ip_pipeline: add sample configuration/script files
@ 2015-12-10 21:28 Jasvinder Singh
  2015-12-14 12:12 ` [dpdk-dev] [PATCH v2] " Jasvinder Singh
  0 siblings, 1 reply; 6+ messages in thread
From: Jasvinder Singh @ 2015-12-10 21:28 UTC (permalink / raw)
  To: dev

This patch includes the configuration and script
files of the some applications which can
be built using DPDK Packet Framework. A
configuration file defines the application
structure which include packet processing stages
(knowns as pipelines), their connectivity and
other parameters necessary to start and run the
application. A script file specifies CLI commands
required for loading table entries (rules/routes,
etc). The configuration/script files for simple
applications such as l2 forwarding, l3 forwarding
have been presented. In addition, to demonstrate
the use and inter-connectivity of various pipeline
modules (which are avilable in packet framework),
a complex packet processing workload i.e. vPE
(Virtual Provider Edge)router is considered. The
configuration of the pipeline stages used for
upstream and downstream flow processing has been
specified separately in two configuration files.

Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
 .../ip_pipeline/config/edge_router_downstream.cfg  |  80 ++++++++++++++++
 .../ip_pipeline/config/edge_router_downstream.cli  |  10 ++
 .../ip_pipeline/config/edge_router_upstream.cfg    | 106 +++++++++++++++++++++
 .../ip_pipeline/config/edge_router_upstream.cli    |  38 ++++++++
 examples/ip_pipeline/config/l2fwd.cfg              |  55 +++++++++++
 examples/ip_pipeline/config/l3fwd.cfg              |  63 ++++++++++++
 examples/ip_pipeline/config/l3fwd.cli              |   9 ++
 7 files changed, 361 insertions(+)
 create mode 100644 examples/ip_pipeline/config/edge_router_downstream.cfg
 create mode 100644 examples/ip_pipeline/config/edge_router_downstream.cli
 create mode 100644 examples/ip_pipeline/config/edge_router_upstream.cfg
 create mode 100644 examples/ip_pipeline/config/edge_router_upstream.cli
 create mode 100644 examples/ip_pipeline/config/l2fwd.cfg
 create mode 100644 examples/ip_pipeline/config/l3fwd.cfg
 create mode 100644 examples/ip_pipeline/config/l3fwd.cli

diff --git a/examples/ip_pipeline/config/edge_router_downstream.cfg b/examples/ip_pipeline/config/edge_router_downstream.cfg
new file mode 100644
index 0000000..6b3370c
--- /dev/null
+++ b/examples/ip_pipeline/config/edge_router_downstream.cfg
@@ -0,0 +1,80 @@
+;   BSD LICENSE
+;
+;   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+;   All rights reserved.
+;
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions
+;   are met:
+;
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in
+;       the documentation and/or other materials provided with the
+;       distribution.
+;     * Neither the name of Intel Corporation nor the names of its
+;       contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+; A simple configuration of the vPE(Virtual Provider Edge) downstream
+: pipeline is presented below. The functional components of the downstream
+; pipeline consists of: Packet RX & Routing, Traffic management and Packet
+; TX. The input packets are IPv4, the output packets are QinQ IPv4.
+
+;               Packet Rx &               Traffic Management              Packet Tx
+;                Routing                   (Pass-Through)               (Pass-Through)
+;             ________________    SWQ0    _________________    SWQ4    _________________
+; RXQ0.0 --->|                |--------->|-----> TM0 ----> |--------->|.................|-------> TXQ0.0
+;            |                |   SWQ1   |                 |   SWQ5   |                 |
+; RXQ1.0 --->|                |--------->|-----> TM1 ----> |--------->|.................|-------> TXQ1.0
+;            |     (P1)       |   SWQ2   |      (P2)       |   SWQ6   |      (P3)       |
+; RXQ2.0 --->|                |--------->|-----> TM2 ----> |--------->|.................|-------> TXQ2.0
+;            |                |   SWQ3   |                 |   SWQ7   |                 |
+; RXQ3.0 --->|                |--------->|-----> TM3 ----> |--------->|.................|-------> TXQ3.0
+;            |________________|          |_________________|          |_________________|
+;                    |
+;                    +--> SINK0	(route miss)
+;
+
+
+[PIPELINE0]
+type = MASTER
+core = 0
+
+[PIPELINE1]
+type = ROUTING
+core = 1
+pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
+pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
+encap = ethernet_qinq
+qinq_sched = test
+ip_hdr_offset = 270; mbuf (128) + headroom (128) + ethernet header (14) = 270
+
+[PIPELINE2]
+type = PASS-THROUGH
+core = 2
+pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 TM0 TM1 TM2 TM3
+pktq_out = TM0 TM1 TM2 TM3 SWQ4 SWQ5 SWQ6 SWQ7
+
+[PIPELINE3]
+type = PASS-THROUGH
+core = 3
+pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
+pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0
+
+[MEMPOOL0]
+pool_size = 2M
diff --git a/examples/ip_pipeline/config/edge_router_downstream.cli b/examples/ip_pipeline/config/edge_router_downstream.cli
new file mode 100644
index 0000000..ce46beb
--- /dev/null
+++ b/examples/ip_pipeline/config/edge_router_downstream.cli
@@ -0,0 +1,10 @@
+################################################################################
+# Routing: Ether QinQ, ARP off
+################################################################################
+p 1 route add default 4 #SINK0
+p 1 route add 0.0.0.0 10 port 0 ether a0:b0:c0:d0:e0:f0 qinq 256 257
+p 1 route add 0.64.0.0 10 port 1 ether a1:b1:c1:d1:e1:f1 qinq 258 259
+p 1 route add 0.128.0.0 10 port 2 ether a2:b2:c2:d2:e2:f2 qinq 260 261
+p 1 route add 0.192.0.0 10 port 3 ether a3:b3:c3:d3:e3:f3 qinq 262 263
+
+p 1 route ls
diff --git a/examples/ip_pipeline/config/edge_router_upstream.cfg b/examples/ip_pipeline/config/edge_router_upstream.cfg
new file mode 100644
index 0000000..5cafd3b
--- /dev/null
+++ b/examples/ip_pipeline/config/edge_router_upstream.cfg
@@ -0,0 +1,106 @@
+;   BSD LICENSE
+;
+;   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+;   All rights reserved.
+;
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions
+;   are met:
+;
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in
+;       the documentation and/or other materials provided with the
+;       distribution.
+;     * Neither the name of Intel Corporation nor the names of its
+;       contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+; A simple configuration of the vPE(Virtual Provider Edge) upstream pipeline
+; is presented below. The functional components of the upstream pipeline
+; consists of: Firewall, Pass-through, Flow-Classification, Flow-Actions
+; and Routing.The input packets are ; QinQ IPv4, the output packets are
+; MPLS IPv4.
+
+;
+:              Firewall         Pass-Through    Flow-Classification   Flow-Actions         Routing
+;             __________  SWQ0   __________  SWQ4   __________  SWQ8   __________  SWQ12  __________
+; RXQ0.0 --->|          |------>|..........|------>|          |------>|          |------>|          |------> TXQ0.0
+;            |          | SWQ1  |          | SWQ5  |          | SWQ9  |          | SWQ13 |          |
+; RXQ1.0 --->|          |------>|..........|------>|          |------>|          |------>|          |------> TXQ1.0
+;            |   (P1)   | SWQ2  |  (P2)    | SWQ6  |   (P3)   | SWQ10 |   (P4)   | SWQ14 |   (P5)   |
+; RXQ2.0 --->|          |------>|..........|------>|          |------>|          |------>|          |------> TXQ2.0
+;            |          | SWQ3  |          | SWQ7  |          | SWQ11 |          | SWQ15 |          |
+; RXQ3.0 --->|          |------>|..........|------>|          |------>|          |------>|          |------> TXQ3.0
+;            |__________|       |__________|       |__________|       |__________|       |__________|
+;                 |                                     |                                     |
+;                 +--> SINK0 (Default)                  +--> SINK1 (Default)                  +--> SINK2 (Route Miss)
+
+
+[PIPELINE0]
+type = MASTER
+core = 0
+
+[PIPELINE1]
+type = FIREWALL
+core = 1
+pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
+pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
+n_rules = 4096
+pkt_type = qinq_ipv4
+
+[PIPELINE2]
+type = PASS-THROUGH
+core = 2
+pktq_in = SWQ0 SWQ1 SWQ2 SWQ3
+pktq_out = SWQ4 SWQ5 SWQ6 SWQ7
+dma_size = 8
+dma_dst_offset = 128; mbuf (128)
+dma_src_offset = 268; mbuf (128) + headroom (128) + 1st ethertype offset (12) = 268
+dma_src_mask = 00000FFF00000FFF; qinq
+dma_hash_offset = 136; dma_dst_offset + dma_size = 136
+
+[PIPELINE3]
+type = FLOW_CLASSIFICATION
+core = 2
+pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
+pktq_out = SWQ8 SWQ9 SWQ10 SWQ11 SINK1
+n_flows = 65536
+key_size = 8; dma_size
+key_offset = 128; dma_dst_offset
+hash_offset = 136; dma_hash_offset
+flowid_offset = 192; mbuf (128) + 64
+
+[PIPELINE4]
+type = FLOW_ACTIONS
+core = 3
+pktq_in = SWQ8 SWQ9 SWQ10 SWQ11
+pktq_out = SWQ12 SWQ13 SWQ14 SWQ15
+n_flows = 65536
+n_meters_per_flow = 1
+flow_id_offset = 192; flowid_offset
+ip_hdr_offset = 278; mbuf (128) + headroom (128) + ethernet (14) + qinq (8) = 278
+color_offset = 196; flowid_offset + sizeof(flow_id)
+
+[PIPELINE5]
+type = ROUTING
+core = 4
+pktq_in = SWQ12 SWQ13 SWQ14 SWQ15
+pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK2
+encap = ethernet_mpls
+mpls_color_mark = yes
+ip_hdr_offset = 278; mbuf (128) + headroom (128) + ethernet (14) + qinq (8) = 278
+color_offset = 196; flowid_offset + sizeof(flow_id)
diff --git a/examples/ip_pipeline/config/edge_router_upstream.cli b/examples/ip_pipeline/config/edge_router_upstream.cli
new file mode 100644
index 0000000..eeba600
--- /dev/null
+++ b/examples/ip_pipeline/config/edge_router_upstream.cli
@@ -0,0 +1,38 @@
+################################################
+# Firewall Rules:4 for 4 ports
+################################################
+p 1 firewall add ipv4 1 0.0.0.0 8 0.0.0.0 10 0 0 0 0 6 1 0
+p 1 firewall add ipv4 1 0.0.0.0 8 0.64.0.0 10 0 0 0 0 6 1 1
+p 1 firewall add ipv4 1 0.0.0.0 8 0.128.0.0 10 0 0 0 0 6 1 2
+p 1 firewall add ipv4 1 0.0.0.0 8 0.192.0.0 10 0 0 0 0 6 1 3
+p 1 firewall add default 4 #SINK0
+
+
+################################################################################
+# Flow classification
+################################################################################
+p 3 flow add default 4 #SINK1
+p 3 flow add qinq all 65536 4
+
+################################################################################
+# Flow Actions - Metering
+################################################################################
+p 4 flows 65536 meter 0 trtcm 1250000000 1250000000 100000000 100000000
+p 4 flows 65536 ports 4
+
+################################################################################
+# Routing: Ether MPLS, ARP off
+################################################################################
+p 5 route add default 4 #SINK2
+p 5 route add 0.0.0.0 10 port 0 ether a0:b0:c0:d0:e0:f0 mpls 0:1
+p 5 route add 0.64.0.0 10 port 1 ether a1:b1:c1:d1:e1:f1 mpls 10:11
+p 5 route add 0.128.0.0 10 port 2 ether a2:b2:c2:d2:e2:f2 mpls 20:21
+p 5 route add 0.192.0.0 10 port 3 ether a3:b3:c3:d3:e3:f3 mpls 30:31
+
+################################################################################
+# List all configurations
+################################################################################
+p 1 firewall ls
+#p 3 flow ls
+#p 4 flow actions ls
+p 5 route ls
diff --git a/examples/ip_pipeline/config/l2fwd.cfg b/examples/ip_pipeline/config/l2fwd.cfg
new file mode 100644
index 0000000..181f686
--- /dev/null
+++ b/examples/ip_pipeline/config/l2fwd.cfg
@@ -0,0 +1,55 @@
+;   BSD LICENSE
+;
+;   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+;   All rights reserved.
+;
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions
+;   are met:
+;
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in
+;       the documentation and/or other materials provided with the
+;       distribution.
+;     * Neither the name of Intel Corporation nor the names of its
+;       contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+;
+; The pass-through pipeline below connects the input ports to the output ports
+; as follows: RXQ0.0 -> TXQ1.0, RXQ1.0 -> TXQ0.0, RXQ2.0 -> TXQ3.0 and
+; RXQ3.0 -> TXQ2.0.
+;             ________________
+; RXQ0.0 --->|................|---> TXQ1.0
+;            |                |
+; RXQ1.0 --->|................|---> TXQ0.0
+;            |  Pass-through  |
+; RXQ2.0 --->|................|---> TXQ3.0
+;            |                |
+; RXQ3.0 --->|................|---> TXQ2.0
+;            |________________|
+;
+
+[PIPELINE0]
+type = MASTER
+core = 0
+
+[PIPELINE1]
+type = PASS-THROUGH
+core = 1
+pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
+pktq_out = TXQ1.0 TXQ0.0 TXQ3.0 TXQ2.0
diff --git a/examples/ip_pipeline/config/l3fwd.cfg b/examples/ip_pipeline/config/l3fwd.cfg
new file mode 100644
index 0000000..8c49fdf
--- /dev/null
+++ b/examples/ip_pipeline/config/l3fwd.cfg
@@ -0,0 +1,63 @@
+;   BSD LICENSE
+;
+;   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+;   All rights reserved.
+;
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions
+;   are met:
+;
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in
+;       the documentation and/or other materials provided with the
+;       distribution.
+;     * Neither the name of Intel Corporation nor the names of its
+;       contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+;             _______________
+; RXQ0.0 --->|               |---> TXQ0.0
+;            |               |
+; RXQ1.0 --->|               |---> TXQ1.0
+;            |    Routing    |
+; RXQ2.0 --->|               |---> TXQ2.0
+;            |               |
+; RXQ3.0 --->|               |---> TXQ3.0
+;            |_______________|
+;                    |
+;                    +-----------> SINK0 (route miss)
+;
+; Input packet: Ethernet/IPv4
+;
+; Packet buffer layout:
+; #	Field Name		Offset (Bytes)	Size (Bytes)
+; 0	Mbuf			0 		128
+; 1	Headroom		128 		128
+; 2	Ethernet header		256 		14
+; 3	IPv4 header		270 		20
+
+[PIPELINE0]
+type = MASTER
+core = 0
+
+[PIPELINE1]
+type = ROUTING
+core = 1
+pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
+pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK0
+encap = ethernet; encap = ethernet / ethernet_qinq / ethernet_mpls
+ip_hdr_offset = 270
diff --git a/examples/ip_pipeline/config/l3fwd.cli b/examples/ip_pipeline/config/l3fwd.cli
new file mode 100644
index 0000000..2774010
--- /dev/null
+++ b/examples/ip_pipeline/config/l3fwd.cli
@@ -0,0 +1,9 @@
+################################################################################
+# Routing: encap = ethernet, arp = off
+################################################################################
+p 1 route add default 4 #SINK0
+p 1 route add 0.0.0.0 10 port 0 ether a0:b0:c0:d0:e0:f0
+p 1 route add 0.64.0.0 10 port 1 ether a1:b1:c1:d1:e1:f1
+p 1 route add 0.128.0.0 10 port 2 ether a2:b2:c2:d2:e2:f2
+p 1 route add 0.192.0.0 10 port 3 ether a3:b3:c3:d3:e3:f3
+p 1 route ls
-- 
2.5.0

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-12-14 21:56 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-10 21:28 [dpdk-dev] [PATCH] ip_pipeline: add sample configuration/script files Jasvinder Singh
2015-12-14 12:12 ` [dpdk-dev] [PATCH v2] " Jasvinder Singh
2015-12-14 12:48   ` [dpdk-dev] [PATCH v3] " Jasvinder Singh
2015-12-14 13:28     ` Thomas Monjalon
2015-12-14 14:20     ` [dpdk-dev] [PATCH v4] " Jasvinder Singh
2015-12-14 21:55       ` Thomas Monjalon

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