From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by dpdk.org (Postfix) with ESMTP id C81FF106B for ; Mon, 23 Mar 2015 14:58:46 +0100 (CET) Received: by wixw10 with SMTP id w10so63529496wix.0 for ; Mon, 23 Mar 2015 06:58:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=3CHVGSdPJoVum++l+eZM01uTQ8o0XXkyiGUZcvahu4U=; b=KzYzP/td2RqfMmU08CPL9HO947fap6U/QWjRaul1qQXki8ulp+SRN+sOWXyZPqGvDZ jj0nYGtVYYlrWG5EFIOlycKsQLpIYIf8b/x3Wdc0VwC10QMXi+S//d4iq645vr7R5805 0NsU4zKsLJ+lZ1lXIiY/dkwpTASyrOyxqNYZqRpFa2lFj1PnwLygbNRg/wdikL8KYWY4 z94oJHFldTQm1w0eOswu+iPlruilv7YzMyuNYE0qTC/cDcyVCDMBIKO/4QyOep1IVtR2 zF4sbPHxeOCvAZMRDWaJqC9DyRQGd4GF6tQckBcj4SsUNW55hWN+deb7gDgn0WLKCX89 x0dg== X-Gm-Message-State: ALoCoQle1brqluSsoKq19r0Wtzbd+mRc7Q21sS5yCwLywPxGfsUHOSJT0eGjk4fhc06AzM1RkPt7 X-Received: by 10.180.98.67 with SMTP id eg3mr19845431wib.11.1427119126626; Mon, 23 Mar 2015 06:58:46 -0700 (PDT) Received: from xps13.localnet (136-92-190-109.dsl.ovh.fr. [109.190.92.136]) by mx.google.com with ESMTPSA id pa4sm1536716wjb.11.2015.03.23.06.58.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Mar 2015 06:58:45 -0700 (PDT) From: Thomas Monjalon To: helin.zhang@intel.com Date: Mon, 23 Mar 2015 14:58:05 +0100 Message-ID: <2832198.DltQoaVEDg@xps13> Organization: 6WIND User-Agent: KMail/4.14.4 (Linux/3.18.4-1-ARCH; KDE/4.14.4; x86_64; ; ) In-Reply-To: <7268152.GLh5O7JM1M@xps13> References: <1423637385-25077-1-git-send-email-xuelin.shi@freescale.com> <7268152.GLh5O7JM1M@xps13> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Cc: dev@dpdk.org, xuelin.shi@freescale.com Subject: Re: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe PCI and CPU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Mar 2015 13:58:47 -0000 Helin, any opinion? If nothing wrong is seen, it will be merged in few days. 2015-02-20 11:55, Thomas Monjalon: > Anyone to review this patch? > > 2015-02-11 14:49, xuelin.shi@freescale.com: > > From: Xuelin Shi > > > > make sure: > > CPU read from ixgbe with IXGBE_LE32_TO_CPUS > > CPU write to ixgbe with IXGBE_CPU_TO_LE32 > > > > otherwise, there is endian issue for ixgbe on BIG_ENDIAN CPU. > > > > Signed-off-by: Xuelin Shi > > --- > > .../linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h | 24 ++++++++++++++++------ > > 1 file changed, 18 insertions(+), 6 deletions(-) > > > > diff --git a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > > index d161600..0612632 100644 > > --- a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > > +++ b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > > @@ -53,6 +53,16 @@ > > > > #undef ASSERT > > > > +static inline uint32_t ixgbe_read_addr(volatile void* addr) > > +{ > > + return IXGBE_LE32_TO_CPUS(*((volatile uint32_t *)addr)); > > +} > > + > > +static inline uint32_t ixgbe_write_addr(u32 value, volatile void* addr) > > +{ > > + return writel(IXGBE_CPU_TO_LE32(value), addr); > > +} > > + > > #ifdef DBG > > #define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A) > > #else > > @@ -91,19 +101,20 @@ > > default: \ > > break; \ > > } \ > > - writel((value), ((a)->hw_addr + (reg))); \ > > + ixgbe_write_addr((value), ((a)->hw_addr + (reg))); \ > > } while (0) > > #else > > -#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg))) > > +#define IXGBE_WRITE_REG(a, reg, value) \ > > + ixgbe_write_addr((value), ((a)->hw_addr + (reg))) > > #endif > > > > -#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg)) > > +#define IXGBE_READ_REG(a, reg) ixgbe_read_addr((a)->hw_addr + (reg)) > > > > #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \ > > - writel((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) > > + ixgbe_write_addr((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) > > > > #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \ > > - readl((a)->hw_addr + (reg) + ((offset) << 2))) > > + ixgbe_read_addr((a)->hw_addr + (reg) + ((offset) << 2))) > > > > #ifndef writeq > > #define writeq(val, addr) do { writel((u32) (val), addr); \ > > @@ -111,7 +122,8 @@ > > } while (0); > > #endif > > > > -#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) > > +#define IXGBE_WRITE_REG64(a, reg, value) \ > > + writeq((cpu_to_le64(value)), ((a)->hw_addr + (reg))) > > > > #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) > > struct ixgbe_hw; > > > >